From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628525; cv=none; d=zohomail.com; s=zohoarc; b=h7olGVKtDFmoV8XN3FWdUPvqWDXxgB9KDYhdWVwW9NzuxxPBwpkJXPgI9sp3TbatbeMbj5eT/3gUNOtMKwFC1U84/+E3ugRUlsBBEeMYJLbjaiutj72zTqzw0ocLO2HpbZzrS3jAzp2xhg133fz5lhkCSytF6deg2ahYTjV4rSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628525; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+JIxHWMClVl6mvpALDoBK231PZeNGUQgT3foMweSwl8=; b=JUrSSOlUmNqc9gGTWQ77ZZ3QbZbbwiPL27U7zElo5AVMVaNUi0138Ni8mhQXrcxIr/hiDKGp5Jvfyx3Vb3vj1mZvMCDX4F/VKrBHTIHheM/DmBBoD5ecmDns7F4w8BMPBHlQbjynqXBQ5L/oTrpR+k0SFc9lZH3NydmoziqQXyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 168762852588155.56779979696773; Sat, 24 Jun 2023 10:42:05 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.554640.865938 (Exim 4.92) (envelope-from ) id 1qD7GR-00007v-A4; Sat, 24 Jun 2023 17:41:35 +0000 Received: by outflank-mailman (output) from mailman id 554640.865938; Sat, 24 Jun 2023 17:41:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7GR-00007o-5O; Sat, 24 Jun 2023 17:41:35 +0000 Received: by outflank-mailman (input) for mailman id 554640; Sat, 24 Jun 2023 17:41:34 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7GQ-0008Gp-3v for xen-devel@lists.xenproject.org; Sat, 24 Jun 2023 17:41:34 +0000 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [2a00:1450:4864:20::42a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 5c12750f-12b6-11ee-b237-6b7b168915f2; Sat, 24 Jun 2023 19:41:33 +0200 (CEST) Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3129c55e1d1so2107431f8f.0 for ; Sat, 24 Jun 2023 10:41:33 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id z7-20020a5d6407000000b0030fcf3d75c4sm2609804wru.45.2023.06.24.10.41.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:41:32 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5c12750f-12b6-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628493; x=1690220493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+JIxHWMClVl6mvpALDoBK231PZeNGUQgT3foMweSwl8=; b=d9EPiTdMBS6ezt21TafvsYW1DcHw6rx3bSyGYk02qijZjSVC1xbJv7hrNc8Bln/+KY da9/C7KLlpChs5ekpkEMTLt+8/tTn69sMDTvOr77GosenaKuMVoIqanEcBIaB+x8/IYa sMX5xiZvQgUwCoIYnw0wLy0I8qTh5UNWS2TKXn7vV66wpwVU6Arg9AwvuzGbtx5f2Fr1 NS187HJhnsPP5z7lKj2H5zJ9WFDNB74ee+CLe5qo2TrqCpMy25BW2hi6t3sBgrl2wrMY 3O1uqpNOR6dT7+pTrezI8H96sgMZeN+qygKbA8KQdg//j8BnqU62WE8Pxxa1LGwOWpQ1 C2DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628493; x=1690220493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+JIxHWMClVl6mvpALDoBK231PZeNGUQgT3foMweSwl8=; b=CP0azyf6B9uqDnDA4j8gXrYWU2Sr0tIzI2ieSMROGiGcdTMRuqC/7znKZwf/nUP4mo s5K2+vHVtz1ADVbPa3BihRFE1lnVjh+bUUM0Dg/7e2BkxtnLIrbdzbbQLJI9HT84jWUV uAJUsjqhBzLIDdM4vin9ux68oF10PHE6bzcSSPXsS2tmQF5BlBz61lARPSTw3pX0UrXe 4szB9hwUJBZn3DZEVqBumVoF7zhF2KGgDPMFF3yeff0n5d8IKy5ctu2aiRe05s6muwSW 9iwLJ/z9cAdbaCplrJx8hp1/GxwxvToxmZ+ZJDL1Ibu//cDIvQl91tDEQUb3gnQj4ZEc ccPA== X-Gm-Message-State: AC+VfDxm9FletFeRAEwjclEbiWIICdGxOFu0JmoCjxatR8VMb3eDH2H4 YRNL4XoJoEifSkfmgqGVqb9sEQ== X-Google-Smtp-Source: ACHHUZ4gIjgAKb4rVFXLZjiJdVzXvPynrHKyrgCEdSr0allCKh8ZZswCbWqoo+JLTWwg5/zBqsSxag== X-Received: by 2002:a5d:5344:0:b0:313:df09:ad04 with SMTP id t4-20020a5d5344000000b00313df09ad04mr2110290wrv.57.1687628493050; Sat, 24 Jun 2023 10:41:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 01/16] MAINTAINERS: Update Roman Bolshakov email address Date: Sat, 24 Jun 2023 19:41:06 +0200 Message-Id: <20230624174121.11508-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628527742100001 r.bolshakov@yadro.com is bouncing: Update Roman's email address using one found somewhere on the Internet; this way he can Ack-by. (Reorder Taylor's line to keep the section sorted alphabetically). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Roman Bolshakov --- MAINTAINERS | 4 ++-- .mailmap | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7f323cd2eb..1da135b0c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -497,14 +497,14 @@ F: target/arm/hvf/ =20 X86 HVF CPUs M: Cameron Esfahani -M: Roman Bolshakov +M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: target/i386/hvf/ =20 HVF M: Cameron Esfahani -M: Roman Bolshakov +M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: accel/hvf/ diff --git a/.mailmap b/.mailmap index b57da4827e..64ef9f4de6 100644 --- a/.mailmap +++ b/.mailmap @@ -76,9 +76,10 @@ Paul Burton Philippe Mathieu-Daud=C3=A9 Philippe Mathieu-Daud=C3=A9 Philippe Mathieu-Daud=C3=A9 +Roman Bolshakov Stefan Brankovic -Yongbok Kim Taylor Simpson +Yongbok Kim =20 # Also list preferred name forms where people have changed their # git author config, or had utf8/latin1 encoding issues. --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628523; cv=none; d=zohomail.com; s=zohoarc; b=S9u1JRo4ZSUBRH2wAVrcgcFuXjrr+trH2VW0JlrIw3uudhrkGkAIiEwiG+/LGKHgBSS56sKle8vXTnL1PlvTowKH+9sOpt3McdTYu+prxo0S4p6xI9GwRZITYtySP7Fqyx+vUEimGcjqrLm3RW1LX/UOJtrmT/pAVRZB9QsNj3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628523; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xHLdIwIywOmneOj5eUp5g6ra2t5DF15QteoMLknkUnc=; b=kU4oJrkn+88H/8mTXHjQG65bz0qJuxvMsgjKluZ5N8mYv+JglkOwkdAkJ6/n19jPy3UtdNlRJzgSv7bI/gZ/yz/nkIyDUeTe87dM9xiwHl3R3jkZORStlgM72/sUPmmaV0IBkAIiJGbsL+9CFcU45ZxTOI8YFqcj/Nf1dqv4IJE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687628523422755.2884587724766; Sat, 24 Jun 2023 10:42:03 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.554641.865947 (Exim 4.92) (envelope-from ) id 1qD7GY-0000SE-Fq; Sat, 24 Jun 2023 17:41:42 +0000 Received: by outflank-mailman (output) from mailman id 554641.865947; Sat, 24 Jun 2023 17:41:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7GY-0000Ry-Cq; Sat, 24 Jun 2023 17:41:42 +0000 Received: by outflank-mailman (input) for mailman id 554641; Sat, 24 Jun 2023 17:41:41 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7GX-0008Gp-Fr for xen-devel@lists.xenproject.org; Sat, 24 Jun 2023 17:41:41 +0000 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [2a00:1450:4864:20::333]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 60769381-12b6-11ee-b237-6b7b168915f2; Sat, 24 Jun 2023 19:41:40 +0200 (CEST) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f9bece8d1bso22346845e9.0 for ; Sat, 24 Jun 2023 10:41:40 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id t16-20020a7bc3d0000000b003f17848673fsm2720557wmj.27.2023.06.24.10.41.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:41:39 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 60769381-12b6-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628500; x=1690220500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xHLdIwIywOmneOj5eUp5g6ra2t5DF15QteoMLknkUnc=; b=omrduxic9rR9gPq+8XiHL87viBJ6wPrEMLfMgl5GRT1MGJsF+TtB4IIzUjBDeXNjSP tp/8tj21VJeGWzF0OuqgjS2WgxvAd7ieEEmjLY+I4RrDNy354ZcTaHifbrUEQBN4g/u9 4e/DFqq/MH/KbKaaB92Ppsx49dKlUxgAkumlNe5v3R+Jm/CqIieAk+esoDLYqoEBfLF/ 1f88uKZFICtvcllNPS/mi7pVo0xerJ43s2nY2Z3sJDSCnEe0Pht9v3orZiuam5tqDacn UUqcswJ4Q6QF4/9o+nZDEmVIc9HxLeYNLEDed2aM4/V1htoQbmJH9XmE/hgtRRhOhIST 3Imw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628500; x=1690220500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xHLdIwIywOmneOj5eUp5g6ra2t5DF15QteoMLknkUnc=; b=UhUS+Yw+qubC3nFMj00IuP06x+4UJ99xull6wpvNpRTRRxqRChGqxnQwQwOWFIlkFe EZIt9AHrp9qdXHPIPRvBC8D7Q88kBH5NiG9jgWvUjw4VjjYOjuyPH/qDoMxtbqKcR0x1 HOmS3c6pFtQ1GOg0mpVEp/cxGn8sHUxuZghOn4Qm7O2YPsQ+SH1Y73ru/GWQHzl+gLvT bmwZNgVYG6UX0W1vbaoBgIfErrDwKyu8YsX7psx0HHPECvoDyBLj+C3sz6g6ZXIs0PmH fdTUosxRh0tWteGOYDkFLSUhLcnOOsvZ159j8fzKaNYXK30FahJCDLcCAP3W+96ZdjbN AlLw== X-Gm-Message-State: AC+VfDzY6YLCQCzsY/8q+OacHDgytYhd/fh2OsZg33Jlk/zC0bbwDIR2 dtkj6iok4DXhi/16MMpQovrwFw== X-Google-Smtp-Source: ACHHUZ4U4xeWdaU30+Yq1mmhN/DHgskzeAXZldA07vw+iV02dwa7q8YwoovgGfKWWwqQiGNx3nFeTA== X-Received: by 2002:a1c:f70d:0:b0:3f7:3685:1e10 with SMTP id v13-20020a1cf70d000000b003f736851e10mr19084030wmh.40.1687628500315; Sat, 24 Jun 2023 10:41:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 02/16] accel: Document generic accelerator headers Date: Sat, 24 Jun 2023 19:41:07 +0200 Message-Id: <20230624174121.11508-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628523750100003 These headers are meant to be include by any file to check the availability of accelerators, thus are not accelerator specific. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- include/sysemu/hax.h | 2 ++ include/sysemu/kvm.h | 2 ++ include/sysemu/nvmm.h | 2 ++ include/sysemu/tcg.h | 2 ++ include/sysemu/whpx.h | 2 ++ include/sysemu/xen.h | 2 ++ 6 files changed, 12 insertions(+) diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h index bf8f99a824..80fc716f80 100644 --- a/include/sysemu/hax.h +++ b/include/sysemu/hax.h @@ -19,6 +19,8 @@ * */ =20 +/* header to be included in non-HAX-specific code */ + #ifndef QEMU_HAX_H #define QEMU_HAX_H =20 diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 88f5ccfbce..7902acdfd9 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -11,6 +11,8 @@ * */ =20 +/* header to be included in non-KVM-specific code */ + #ifndef QEMU_KVM_H #define QEMU_KVM_H =20 diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h index 833670fccb..be7bc9a62d 100644 --- a/include/sysemu/nvmm.h +++ b/include/sysemu/nvmm.h @@ -7,6 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-NVMM-specific code */ + #ifndef QEMU_NVMM_H #define QEMU_NVMM_H =20 diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 53352450ff..5e2ca9aab3 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-TCG-specific code */ + #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H =20 diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h index 2889fa2278..781ca5b2b6 100644 --- a/include/sysemu/whpx.h +++ b/include/sysemu/whpx.h @@ -10,6 +10,8 @@ * */ =20 +/* header to be included in non-WHPX-specific code */ + #ifndef QEMU_WHPX_H #define QEMU_WHPX_H =20 diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h index 0ca25697e4..bc13ad5692 100644 --- a/include/sysemu/xen.h +++ b/include/sysemu/xen.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-Xen-specific code */ + #ifndef SYSEMU_XEN_H #define SYSEMU_XEN_H =20 --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628529; cv=none; d=zohomail.com; s=zohoarc; b=ZzVLflzmWB6DOMrXXYEQTKujQ2MYC9yi9PiLy+ZsxvhmCIMDK8VQEdUHuETk9Qw0iDLRh7GfBcmQQ/aiCvICfHMSfhcv8jbRkZmCYasHGkegJb5Mjvzkj7JelRe1FIL4+UM0KCJ5Cm227AvQn/uCgqPhosmQKSzkD6SVVTD5b7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628529; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iG1kgLZ5QV1q9fprOekDS1vi4YDLS9XqOgasp153yeA=; b=iJE26b6S0Rc+3R5kEVKjHgb80t2xsYxgu+iCJ4n/vYBXJhVz+nWC7Utvz4TFA/MOLApWKnrJb9O0TEf1QWv8a4gTq01XQeO2yfFSihMi/H4HuxZIO3nY7f0sBAFJhFSqtbwoz+hsSTEHCkjMgbaAmaU04yF6kMYQSHiuI16aQXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687628529913513.9177797815379; Sat, 24 Jun 2023 10:42:09 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.554643.865957 (Exim 4.92) (envelope-from ) id 1qD7Gg-0000xv-Na; Sat, 24 Jun 2023 17:41:50 +0000 Received: by outflank-mailman (output) from mailman id 554643.865957; Sat, 24 Jun 2023 17:41:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gg-0000xj-KB; Sat, 24 Jun 2023 17:41:50 +0000 Received: by outflank-mailman (input) for mailman id 554643; Sat, 24 Jun 2023 17:41:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gf-0000wd-G6 for xen-devel@lists.xenproject.org; Sat, 24 Jun 2023 17:41:49 +0000 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [2a00:1450:4864:20::329]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6468e15a-12b6-11ee-8611-37d641c3527e; Sat, 24 Jun 2023 19:41:47 +0200 (CEST) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f9bece8d1bso22347675e9.0 for ; Sat, 24 Jun 2023 10:41:47 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id p23-20020a1c7417000000b003f9b0f640b1sm2712454wmc.22.2023.06.24.10.41.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:41:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6468e15a-12b6-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628507; x=1690220507; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iG1kgLZ5QV1q9fprOekDS1vi4YDLS9XqOgasp153yeA=; b=K86GwMMvk4Df7udKOIOJ1vd/414tWjcj7PaRdAJ3QyILeXtNH5ZrXuja1IMnbHcdr6 Y3ebUsAdLPajHQlE39ljJ0fh/t/JOBvYNV3b1NEe+LE9+APH19Ejl4JAt+dbQAuXBfQG APP2deEp7Mz2AHGIykGQohAv+jMZxXlGcUZUUP5eB4eZ+/bp2zpXSpG45gUaftUbbM4h 5VXKPOKiAkaTH9X4aafmA+F7qu6COUvyHTBWEy2hotlnbHYRw86edbr2sm8Jd6RGhxKg UTQS4TDFLjCbZez6jFysEJYiEbh83uGUurvLwpjCbf3TGV5woFHYcA+a7TFnE+XwwpJc rP5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628507; x=1690220507; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iG1kgLZ5QV1q9fprOekDS1vi4YDLS9XqOgasp153yeA=; b=WzV8ca3ZJXh4ugua8NwCEHSBNiQLJQUDlGbFixxopDByGzHMH02exGb7BUfsd0e4VR QO1YAQdF0cgOTW92VSbBEABkW/0buDSzCPX3sKp4+pk8+pLFPxsOjUMTnbMqp/3G5Y9W 5AqPfOgbGIqhSczqEe4+N+k/spBAp9kA+IFIiDbM7JGIErdgLOFqFmNncAqJGwruxn75 MLuxGv6uubr62ThUsMIqridKmwVZdF+BHR+CGExKvxUkh5LlmxGBT+ozsJGLVY/+bCL2 YxRh/3n3PDfop0T/tRHg9tVXWuUM35Qa38ErQXSeoVx2SeBVyn5W3bcagh/q4ysZJbwa Ru3A== X-Gm-Message-State: AC+VfDz7Ko9ahy3tAbuuALmkUaJnS4MY0CNWdI+JaA1VwKLEwc6LEsbX xV8mrwtyBhH5vOMbx2VajiDPnoCZUtTmu0Wk1w0= X-Google-Smtp-Source: ACHHUZ7OfepQue0fzzv7ARVu6MjpgeQ79vp0jBcJMaT0gk3oCOgSw7w1smkAWzCkTRk8bysAFxnFSg== X-Received: by 2002:a1c:7419:0:b0:3f9:b79d:a5fa with SMTP id p25-20020a1c7419000000b003f9b79da5famr10746278wmc.16.1687628507031; Sat, 24 Jun 2023 10:41:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 03/16] accel: Remove unused hThread variable on TCG/WHPX Date: Sat, 24 Jun 2023 19:41:08 +0200 Message-Id: <20230624174121.11508-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628531953100003 On Windows hosts, cpu->hThread is assigned but never accessed: remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops-mttcg.c | 4 ---- accel/tcg/tcg-accel-ops-rr.c | 3 --- target/i386/whpx/whpx-accel-ops.c | 3 --- 3 files changed, 10 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index b320ff0037..b276262007 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -152,8 +152,4 @@ void mttcg_start_vcpu_thread(CPUState *cpu) =20 qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 23e4d0f452..2d523289a8 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -329,9 +329,6 @@ void rr_start_vcpu_thread(CPUState *cpu) =20 single_tcg_halt_cond =3D cpu->halt_cond; single_tcg_cpu_thread =3D cpu->thread; -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } else { /* we share the thread */ cpu->thread =3D single_tcg_cpu_thread; diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-acce= l-ops.c index e8dc4b3a47..67cad86720 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -71,9 +71,6 @@ static void whpx_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, whpx_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } =20 static void whpx_kick_vcpu_thread(CPUState *cpu) --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628537; cv=none; d=zohomail.com; s=zohoarc; b=R1NMyyBPNF4+iQPfIWLJz1DHhN8CXigZ1IB74Nz3Fb1o2SYCfvh9+DtxkDgncz68HmSjrNReCkhbd4a9CCGAPu2MNE2w5TBDKGoRl5++8f9yKiMo7PNaIZHEXapZglKQOBJ3HFausMwe2PuCrZtZkcstQPZE8va28XxVA1rL9xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628537; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=Iux/M3Zb2d9D9Hb/9z05lV6jSkOwKIBow2V4Jsl0YCf60pmWPyqMMCrZvmRPlVVv+NkkXPMlHwB/LRQ/QFlPQWqxdib0gMdpACbx8i8vtSTNkh3SVCMPTqd+GhOhhH91CdI+wfDCLDFams+egOB2HolbyLjRxWEGHRySLo035kw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687628537340106.7653727558718; Sat, 24 Jun 2023 10:42:17 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.554646.865967 (Exim 4.92) (envelope-from ) id 1qD7Gn-0001R6-0D; Sat, 24 Jun 2023 17:41:57 +0000 Received: by outflank-mailman (output) from mailman id 554646.865967; Sat, 24 Jun 2023 17:41:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gm-0001Qz-SX; Sat, 24 Jun 2023 17:41:56 +0000 Received: by outflank-mailman (input) for mailman id 554646; Sat, 24 Jun 2023 17:41:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gl-0000wd-Tg for xen-devel@lists.xenproject.org; Sat, 24 Jun 2023 17:41:55 +0000 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [2a00:1450:4864:20::42e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 687594aa-12b6-11ee-8611-37d641c3527e; Sat, 24 Jun 2023 19:41:54 +0200 (CEST) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-313e714342cso444875f8f.0 for ; Sat, 24 Jun 2023 10:41:54 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id i11-20020adfefcb000000b0030ae3a6be5bsm2589165wrp.78.2023.06.24.10.41.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:41:53 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 687594aa-12b6-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628514; x=1690220514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=JjwltddD/cnNRwVGBpMlwyJ7wVl1Dd+vLMYIA1ed2CA1z7xOvX3DxVnc8gtCpAefSE xo5g1CiCqTPXpIH4UJy5+rsZYpuKE81Z7be0dQTZ7JzdeX9j5u9Mx8Z5FVXetI2JfTyn 47UG4xbVI3FVQad68NuGZMbwNXEiWjQIy56FIAywQDCoHP3eiLzbyyHqhhjC+Qo5u3Cg 4ws7FQYnR+gqZpuWyo+1mj6A2Kgebxl4XbhZ5VUeZWE7itV80GK8EINXxv01Dffpjd6L xbEKH2Df7yWf84jA7YjCpGFhq4pv94jz889H0Vtin/e3lUxP++i7igvK6CJ6NiiQ/q9Z ZPCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628514; x=1690220514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=JbfNmFC+ZW97D6kyq7EyO9PkvjxMOhYQUOkgxf59xCqXhMOvbRa3ev0uFUqSBX11M9 tqjcHWbYKLr7Q3GNhdnzXMBKYQAYtsErX8V44Y/H7QhQb67D99Vb4AlSMEra8l6zAm4W ZN7djHAaT55SUipirWq2BkTHmZLMqeCMRLUZz31MxKNkgiDU5VVO/R0LZ8h1+wYBvuQd lZqZXHZLU6tjk/ZitiI24eoFWs0cadC7qf5mvXv5gCLBbnaRMKcj2NxKohqLGRgvPKXi dOf/ba9KnCyMo44hIvpNl6BiYLCl3bgLlLvnCFomRiNZb0kUyQsz6GGRcOEQiBQP5unz YaAg== X-Gm-Message-State: AC+VfDxhm+KC10g8knWL6XNj4WdM0WrHYOM5DuDR3JJd3N+NDbqWK9P8 nH83VaK3qHoZ9Zor+UjR+zA4Yw== X-Google-Smtp-Source: ACHHUZ4nAed12yC0ATc4y4T6ov4JNqGmFeW1j5VBFhJ02T6YV9zBXbm//g8zhdDQtOShKB4zz31FCw== X-Received: by 2002:a5d:5541:0:b0:311:abb:e377 with SMTP id g1-20020a5d5541000000b003110abbe377mr6323739wrw.39.1687628513811; Sat, 24 Jun 2023 10:41:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 04/16] accel: Fix a leak on Windows HAX Date: Sat, 24 Jun 2023 19:41:09 +0200 Message-Id: <20230624174121.11508-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628539554100009 hThread is only used on the error path in hax_kick_vcpu_thread(). Fixes: b0cb0a66d6 ("Plumb the HAXM-based hardware acceleration support") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/hax/hax-all.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3e5992a63b..a2321a1eff 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -205,6 +205,9 @@ int hax_vcpu_destroy(CPUState *cpu) */ hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; +#ifdef _WIN32 + CloseHandle(cpu->hThread); +#endif g_free(vcpu); return 0; } --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628542; cv=none; d=zohomail.com; s=zohoarc; b=AnGgkTLZkcW6IDmciSkh7F+6vj8eL/CHE4KDqlvmXeZwzpqR3UY4aACvn+JyoU1ALL+aS2h4lIQjP29voG8QIs8Zdx0Ai+UdpR+O/MtVAw9J9BMmjoQUhLYo9hS90dCJKiX5vOO5eBiQrsWwndQMpY0k62qx5tRvtD4ZD33AGqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628542; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iCloP/Ux3IV8UJ0ZKXn7/ebp5dcIIh/2RC3mzeqRGMo=; b=cgJjcaHsiG0EvaL8uxkNQPM9O14xa92VM3PLmUsZsIMLPZE3N3DvadNiimfRFO3SRj6IXQ1Nqcs7QlFSSi6DndI2tj5+nWzdm/6KK/kqkF25kx6NMIb+yTdmNsBrPDeFBoFoI/PxQ2OiRgGnw4LgnmJDMy+dhh8fMe8cvurGzq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687628542057679.9033795838901; Sat, 24 Jun 2023 10:42:22 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.554650.865977 (Exim 4.92) (envelope-from ) id 1qD7Gs-0001sV-Cb; Sat, 24 Jun 2023 17:42:02 +0000 Received: by outflank-mailman (output) from mailman id 554650.865977; Sat, 24 Jun 2023 17:42:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gs-0001sF-9I; Sat, 24 Jun 2023 17:42:02 +0000 Received: by outflank-mailman (input) for mailman id 554650; Sat, 24 Jun 2023 17:42:01 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qD7Gr-0008Gp-Dh for xen-devel@lists.xenproject.org; Sat, 24 Jun 2023 17:42:01 +0000 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [2a00:1450:4864:20::42b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 6c6eb909-12b6-11ee-b237-6b7b168915f2; Sat, 24 Jun 2023 19:42:00 +0200 (CEST) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-307d58b3efbso1638314f8f.0 for ; Sat, 24 Jun 2023 10:42:00 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id u18-20020a5d6ad2000000b00313e90d1d0dsm650617wrw.112.2023.06.24.10.41.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:00 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6c6eb909-12b6-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628520; x=1690220520; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iCloP/Ux3IV8UJ0ZKXn7/ebp5dcIIh/2RC3mzeqRGMo=; b=B5Q6wTHDnyh2KH0MiJh6f7PRNtQ407iOhYbCWpAuAn2/F07ZIUhbhg5RZhnZx5aixo krIptOmRDGX4i+JQ48AmPyA0UMgIN9bZPYWdqQc0zCDEP4Do4gFa4VBPEK3TV2G/qjyK TxY+6y3B+iWbYRlATMU2lY1+o9i90v/HVZQYbeyLm6UdtSQEpYHVUcZ5fxK5VJ1NnEYs iy0BtiVzJy2t5b9awonbad36/jZG14S8MSTnthMeJln51zyNicO+yZr+ObXx88p69pnr S1aw9y9Wlm9wze65oBQ50fPz5m5iQqX+190XTv09khKKIIEk79oKUf1Nr2TcLzDhZUZR Grzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628520; x=1690220520; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iCloP/Ux3IV8UJ0ZKXn7/ebp5dcIIh/2RC3mzeqRGMo=; b=RLOzNh42ffm8wZ3wVwvkI9zk7HA7Gs9fFUWmYtxchm58fH1UGE3Wum2i4A8sH3cfLn xNe/MYp5gfOHEfmbO/FXarBQ+NvMCXZ95tVE3bQAHDLyVPBwKb0xuCE3UOdeYG1znovt ltWth7bc5msTpEnbIV4qSbsBbVhmM0PjKkEw+vk7NzGmx5QpG4kXUcJo1BoZ2G2Ljp9f rg6xE96p+vtGSd8H+pRp/vh/gimVJolezp5lM4R4xxieEQa0qONSffT2f9v+NkpK4Ab6 5alBaj7BK31nbytSaqD6ioyyqL3TXRBZ+nTmnLm28csiM3ISGlEqCtblS3gWlfrUnUcM XCbQ== X-Gm-Message-State: AC+VfDwD2TpkoZnMtScr5Jatvx8lFJ0blPToe4Jb9BhMsMGSPBd15w7r 5fTXX37k8SQ5D4/Ayg6ud4WU3w== X-Google-Smtp-Source: ACHHUZ5/SpC0ZbioPxnpVkbdcutfj7CfDUgxK3ql/H+wAujoV6T+DY7QM+cKCk/JAModrZsCdUekWQ== X-Received: by 2002:a5d:5242:0:b0:313:deda:c444 with SMTP id k2-20020a5d5242000000b00313dedac444mr1551101wrc.24.1687628520556; Sat, 24 Jun 2023 10:42:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 05/16] accel: Destroy HAX vCPU threads once done Date: Sat, 24 Jun 2023 19:41:10 +0200 Message-Id: <20230624174121.11508-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628543802100003 When the vCPU thread finished its processing, destroy it and signal its destruction to generic vCPU management layer. Add a sanity check for the vCPU accelerator context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/hax/hax-accel-ops.c | 3 +++ target/i386/hax/hax-all.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 18114fe34d..0157a628a3 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -53,6 +53,8 @@ static void *hax_cpu_thread_fn(void *arg) =20 qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); + hax_vcpu_destroy(cpu); + cpu_thread_signal_destroyed(cpu); rcu_unregister_thread(); return NULL; } @@ -69,6 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); + assert(cpu->hax_vcpu); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index a2321a1eff..38a4323a3c 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -209,6 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); + cpu->hax_vcpu =3D NULL; return 0; } =20 --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628567; cv=none; d=zohomail.com; s=zohoarc; b=YBprTVdzjv/eAoFZ8DT49ZzyuePVT/jf/TSSX3WfYDj+YHkGUL4Lr81mvZwq8j6NHsL+kdZTImNEapf8MYyAfdvlAxCnLvROQZrRPf2I71nA+ADah6f82wlWBvKWJyEIGi54YiK0W8NFHplk9ZZ49ZCA284x28HgvKVraVOofQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628567; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=JRrcsr+Nz+mKo7aRpGvspBGP/v3nmW7OsaZ+bG4tsOGIgaNTt9LT8xP2ciVuGmItinf5+yEsBIeCMkn30nPFAxhk4vVssd60dSOUAdS6vLguvjj+6abSrQvx3YAT5xZZ2797wwHLNfbD76YXxu/KUgijGxgcIQK3hNG3HnJhl50= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628567373755.5942050841581; Sat, 24 Jun 2023 10:42:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7H3-0006FD-9N; Sat, 24 Jun 2023 13:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7H1-00069u-Ll for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:11 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7Gz-0006Q3-Ok for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:11 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f9ede60140so17662715e9.0 for ; Sat, 24 Jun 2023 10:42:09 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id p4-20020a7bcc84000000b003f9c8c6bf53sm2714753wma.13.2023.06.24.10.42.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628528; x=1690220528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=SMLuGhbM3MaDMV9r6KR7RvXRIKqv+XtIKbKhRTt6D/Vm3gPRwn5blrByxm/Fk9daGq Eb4uDULNXVOFNfUHg3fRZgZ5xRjJUoWuQu17MVMm3n1dxkZmf9mr8seaW6sh6rqV8TYt 6SkaklT3irVTc01XNANs6JtTVfJ/FHNjbknlsytNfopuGsAcWX0i+Bz99JeARomRP7wT 3sX7v4bNKtTFAn7JegwwEUztQwWXg0bS+L/YlefFCRCGukVOw//BD43mbeY6bdWXzIJE 5DKMSwa60c9c1kSx6wlSfXeF1ud/A4ZzVtV5mMPh9L+rICPmtFtVUo1zCaI4F1bzZEU8 8N6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628528; x=1690220528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=eP3rlyHJ7jbAnrnm2/Wgi3rzl736K6uG6rK9OZFL0XdMUzrq2p1ScQl1syOYKDKcAL 3ZkkiBnYYvglc0gV3ZG8AvPsVO71z8Vav5GRDHwgx7Hf7MNLV1P29Yg6nKxMUB/9Wc5d GNzRHp+TS6ARqR465KEbNFdd7BH2ZmgODwargY6l8e2Hr9J9G28lPYGT8Or3N5xBOrXD 8Ma1H2aSgJqkTFLh89hDxtXGou/TUqidK4kfjkGU74DaVSxGIrFfS7THEb9BljzV2ZTk MPXWP8KxXDddKbz56z/ZGnHbxSAHuLUD3xajdc6W7mcubgOJiXvawJzTJWlmNAaT7E6Y tHrQ== X-Gm-Message-State: AC+VfDxqEKklRzks0oCwn80DC+IzOAnATYS4Eu8/PS5JJ6BtbEZEQsGi t8GIily3W0iUn/N8pagTfCIwb2PKcGCbrmFi68c= X-Google-Smtp-Source: ACHHUZ7yOaurvWT1v2FwBkdZ9j/78UpmqCV6GWSwnA9KFjQtIRVj6Tbvs3g7WLhoyLu/xsqSjabGsQ== X-Received: by 2002:a7b:cd97:0:b0:3f9:a6f3:f23d with SMTP id y23-20020a7bcd97000000b003f9a6f3f23dmr13083870wmj.13.1687628527874; Sat, 24 Jun 2023 10:42:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 06/16] accel: Rename 'hax_vcpu' as 'accel' in CPUState Date: Sat, 24 Jun 2023 19:41:11 +0200 Message-Id: <20230624174121.11508-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628568087100003 All accelerators will share a single opaque context in CPUState. Start by renaming 'hax_vcpu' as 'accel'. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 +- target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 18 +++++++++--------- target/i386/nvmm/nvmm-all.c | 6 +++--- target/i386/whpx/whpx-all.c | 6 +++--- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4871ad85f0..84b5a866e7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -441,7 +441,7 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *hax_vcpu; + struct hax_vcpu_state *accel; =20 struct hvf_vcpu_state *hvf; =20 diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 0157a628a3..a8512efcd5 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -71,7 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - assert(cpu->hax_vcpu); + assert(cpu->accel); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 38a4323a3c..3865ff9419 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->hax_vcpu; + struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -209,7 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); - cpu->hax_vcpu =3D NULL; + cpu->accel =3D NULL; return 0; } =20 @@ -223,7 +223,7 @@ int hax_init_vcpu(CPUState *cpu) exit(-1); } =20 - cpu->hax_vcpu =3D hax_global.vm->vcpus[cpu->cpu_index]; + cpu->accel =3D hax_global.vm->vcpus[cpu->cpu_index]; cpu->vcpu_dirty =3D true; qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); =20 @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { @@ -1114,8 +1114,8 @@ void hax_reset_vcpu_state(void *opaque) { CPUState *cpu; for (cpu =3D first_cpu; cpu !=3D NULL; cpu =3D CPU_NEXT(cpu)) { - cpu->hax_vcpu->tunnel->user_event_pending =3D 0; - cpu->hax_vcpu->tunnel->ready_for_interrupt_injection =3D 0; + cpu->accel->tunnel->user_event_pending =3D 0; + cpu->accel->tunnel->ready_for_interrupt_injection =3D 0; } } =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b75738ee9c..cf4f0af24b 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -52,7 +52,7 @@ static struct qemu_machine qemu_mach; static struct qemu_vcpu * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->hax_vcpu; + return (struct qemu_vcpu *)cpu->accel; } =20 static struct nvmm_machine * @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D (struct hax_vcpu_state *)qcpu; =20 return 0; } @@ -1030,7 +1030,7 @@ nvmm_destroy_vcpu(CPUState *cpu) struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); - g_free(cpu->hax_vcpu); + g_free(cpu->accel); } =20 /* -----------------------------------------------------------------------= --- */ diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 52af81683c..d1ad6f156a 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -262,7 +262,7 @@ static bool whpx_has_xsave(void) =20 static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->hax_vcpu; + return (struct whpx_vcpu *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D (struct hax_vcpu_state *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 @@ -2300,7 +2300,7 @@ void whpx_destroy_vcpu(CPUState *cpu) =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); - g_free(cpu->hax_vcpu); + g_free(cpu->accel); return; } =20 --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628561; cv=none; d=zohomail.com; s=zohoarc; b=QUULbrii/U3OEIp9J6dzpAp+sUWjeMB/bmAx05RGISXijeN8CaEGgQqsMs9qg3eX2fmuiF3LuGkK9KL9++7BSgAzWQXf3NAtcL62vptm03/Vg/Z5hT9sZ1w/YtRfsvxs7k48fB1H6VkRH51ETlUdGNroAzeNtMla667CJEqKrgs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628561; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jesYnGv71+FK9NHqSWoHnqh4nOCgnV66g281tGNK4XE=; b=mL8HgTxyl6jDal+qPQO95gWSHXlacGlSlJ30iMszIA14lXv0H2zKcqQi7Gj7tNPzCCBP80vrwRVuIxT+cVONZQITjV1vXpZTYV4dEY/Yyc+NvSnJH4iq2BMYINKV4AkgM7XIQISg+FmVXk4sClOv5Rj+qPJSbSJnfX7nt5oxFrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628561320230.33362363881497; Sat, 24 Jun 2023 10:42:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7HC-0006gk-M9; Sat, 24 Jun 2023 13:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7HB-0006el-0r for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:21 -0400 Received: from mail-lf1-x12f.google.com ([2a00:1450:4864:20::12f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7H9-0006fh-0r for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:20 -0400 Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f871c93a5fso2316486e87.2 for ; Sat, 24 Jun 2023 10:42:18 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id a25-20020a5d4579000000b003048477729asm2596667wrc.81.2023.06.24.10.42.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628537; x=1690220537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jesYnGv71+FK9NHqSWoHnqh4nOCgnV66g281tGNK4XE=; b=PSP13nJmGuGfUIHZYTQrZ7FoGcAETjiVze80Ga5o8kpBQN7EVd6/ZzsWnI0bc5+cf2 7P4AegcanBm6I0AqxSivnZhhIHWzc1EVaUqUBxf50e78O1SpYR4am8GUmpXnKT00dLaD YtjYLG64eb2fi0Z3rW8DTkUaUQ1+9LB1hJizePMmfW38t13xGzSESQ8rr931uMREPgJH P/L9BhrWugNQhyCgnRt4wqGOi+9bLjVPyPkRVECeAFCL4odpYkKQuWMMJuNDEEDTmIji 09xQDF2Yw87T4a6e+eKg+ZG6yJNlTJfQ65Pq4Dryt28VK/9aRDBbVC4TNa/AjZOKojLp qRvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628537; x=1690220537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jesYnGv71+FK9NHqSWoHnqh4nOCgnV66g281tGNK4XE=; b=C+ff/Wx3nbHpOTDYqyw7+AnQRZn+yrdr5+vEmiHQ1ajEWm8decokQYUc8R6+F2U/58 B7VFMBinEqkNI88FpuX35g4ylvinGMuKJWsaaXX38jx28nYhmA/OvOLTwE9JI4hjtBCL 7xgQhnvpKDZpfAF4AqGz/I67Jl5+hw+uoA1MLHKEoednRWSAZ4LHHg3Hyok21WeTKhrm JyKOlmJHdhcsuZf5UFyPvtzYCY4s3ATV1VGyRxFtsin2/3fOJDO7AU69WfPODx/Fhxoi dptGWowTPex0yfUJo8moWYaJMqK7btvn6iCBPoou+4c/DboWnKcw1Qlww0mgR7NGTVkw icaA== X-Gm-Message-State: AC+VfDyrETaftR6b6PrRLpdLAsM0aLKCexM7DJqA8gb0/k2qYtnZvtKJ trCWv/1QV3tKYfusDN8unXXfaDlxDIfT247sPfo= X-Google-Smtp-Source: ACHHUZ5HouryARGSWaT/lKrQvSPsvbth8CsYlYA04KZeOzupF4wiRSUljoLeinX5wljmzo5CwWGLfg== X-Received: by 2002:a05:6512:31c7:b0:4f9:5cb9:5be5 with SMTP id j7-20020a05651231c700b004f95cb95be5mr7691618lfe.65.1687628536208; Sat, 24 Jun 2023 10:42:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 07/16] accel: Rename HAX 'struct hax_vcpu_state' -> AccelCPUState Date: Sat, 24 Jun 2023 19:41:12 +0200 Message-Id: <20230624174121.11508-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=philmd@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628561907100003 We want all accelerators to share the same opaque pointer in CPUState. Start with the HAX context, renaming its forward declarated structure 'hax_vcpu_state' as 'AccelCPUState'. Document the CPUState field. Directly use the typedef. Remove the amusing but now unnecessary casts in NVMM / WHPX. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 5 ++--- include/qemu/typedefs.h | 1 + target/i386/hax/hax-i386.h | 9 +++++---- target/i386/hax/hax-all.c | 16 ++++++++-------- target/i386/hax/hax-posix.c | 4 ++-- target/i386/hax/hax-windows.c | 4 ++-- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 8 files changed, 22 insertions(+), 21 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 84b5a866e7..a7fae8571e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -240,7 +240,6 @@ typedef struct SavedIOTLB { struct KVMState; struct kvm_run; =20 -struct hax_vcpu_state; struct hvf_vcpu_state; =20 /* work queue */ @@ -308,6 +307,7 @@ struct qemu_work_item; * @next_cpu: Next CPU sharing TB cache. * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. + * @accel: Pointer to accelerator specific state. * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. @@ -422,6 +422,7 @@ struct CPUState { uint32_t can_do_io; int32_t exception_index; =20 + AccelCPUState *accel; /* shared by kvm, hax and hvf */ bool vcpu_dirty; =20 @@ -441,8 +442,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *accel; - struct hvf_vcpu_state *hvf; =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 8c1840bfc1..834b0e47a0 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -21,6 +21,7 @@ * Incomplete struct types * Please keep this list in case-insensitive alphabetical order. */ +typedef struct AccelCPUState AccelCPUState; typedef struct AccelState AccelState; typedef struct AdapterInfo AdapterInfo; typedef struct AddressSpace AddressSpace; diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 409ebdb4af..4372ee596d 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -25,7 +25,8 @@ typedef HANDLE hax_fd; #endif =20 extern struct hax_state hax_global; -struct hax_vcpu_state { + +struct AccelCPUState { hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; @@ -46,7 +47,7 @@ struct hax_vm { hax_fd fd; int id; int numvcpus; - struct hax_vcpu_state **vcpus; + AccelCPUState **vcpus; }; =20 /* Functions exported to host specific mode */ @@ -57,7 +58,7 @@ int valid_hax_tunnel_size(uint16_t size); int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion); int hax_inject_interrupt(CPUArchState *env, int vector); struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus); -int hax_vcpu_run(struct hax_vcpu_state *vcpu); +int hax_vcpu_run(AccelCPUState *vcpu); int hax_vcpu_create(int id); void hax_kick_vcpu_thread(CPUState *cpu); =20 @@ -76,7 +77,7 @@ int hax_host_create_vm(struct hax_state *hax, int *vm_id); hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); hax_fd hax_host_open_vcpu(int vmid, int vcpuid); -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu); +int hax_host_setup_vcpu_channel(AccelCPUState *vcpu); hax_fd hax_mod_open(void); void hax_memory_init(void); =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3865ff9419..9d9011cc38 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; + AccelCPUState *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -136,7 +136,7 @@ static int hax_version_support(struct hax_state *hax) =20 int hax_vcpu_create(int id) { - struct hax_vcpu_state *vcpu =3D NULL; + AccelCPUState *vcpu =3D NULL; int ret; =20 if (!hax_global.vm) { @@ -149,7 +149,7 @@ int hax_vcpu_create(int id) return 0; } =20 - vcpu =3D g_new0(struct hax_vcpu_state, 1); + vcpu =3D g_new0(AccelCPUState, 1); =20 ret =3D hax_host_create_vcpu(hax_global.vm->fd, id); if (ret) { @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + AccelCPUState *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -263,7 +263,7 @@ struct hax_vm *hax_vm_create(struct hax_state *hax, int= max_cpus) } =20 vm->numvcpus =3D max_cpus; - vm->vcpus =3D g_new0(struct hax_vcpu_state *, vm->numvcpus); + vm->vcpus =3D g_new0(AccelCPUState *, vm->numvcpus); for (i =3D 0; i < vm->numvcpus; i++) { vm->vcpus[i] =3D NULL; } @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->accel; + AccelCPUState *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + AccelCPUState *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->accel; + AccelCPUState *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index ac1a51096e..a057a5bd94 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -205,7 +205,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return fd; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) { int ret; struct hax_tunnel_info info; @@ -227,7 +227,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(AccelCPUState *vcpu) { return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); } diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 59afa213a6..bf4b0ad941 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -301,7 +301,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return hDeviceVCPU; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) { hax_fd hDeviceVCPU =3D vcpu->fd; int ret; @@ -327,7 +327,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(AccelCPUState *vcpu) { int ret; HANDLE hDeviceVCPU =3D vcpu->fd; diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cf4f0af24b..b3c3adc59a 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D qcpu; =20 return 0; } diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d1ad6f156a..410b34d8ec 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628604; cv=none; d=zohomail.com; s=zohoarc; b=KfhMZV4iORN3kApFovbomi7ux5x3AytP5EAYqta71M1KO+sBNoK3FMVyGgf5ATonnQ0Ab6lD4RrKbhg3XKACuZjr7q+qgsL1dMO63QvaS3+QLwXXbfWx+vG43z0SCK/Tdfe5lh0MSWIqWo9eTqgvHKKzrWqDJuNmkIlNw1bi9Lc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628604; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NN9VasAt75iFOv6bKm088IUAp3WHizK1u2macVzvnVk=; b=fdXMApU9unjMhkHNTNrtEM5/p/ZJEIOgfQcyrveuIAfo5OL8lPwxGv6VHmnkQbs7n22OeArLplYEjUbau9Rr4m8I2kcFzKtVRlqj5oUcNgYzcMh3lJEmIjNqu+UbjwnzGxGgp3r8LsHlIGPX79w7/966t+ezWeqe8xTv3EB3d20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628604553158.22675756964964; Sat, 24 Jun 2023 10:43:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7HJ-0006tg-1e; Sat, 24 Jun 2023 13:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7HH-0006ol-Gl for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:27 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7HF-0006oR-N8 for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:27 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-98dfb3f9af6so84286266b.2 for ; Sat, 24 Jun 2023 10:42:25 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id i10-20020a170906250a00b0096a6be0b66dsm1102885ejb.208.2023.06.24.10.42.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628544; x=1690220544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NN9VasAt75iFOv6bKm088IUAp3WHizK1u2macVzvnVk=; b=TpoTyF2JMLfTdhJFfQDIJVDl7wyit9krNMh5pkE5UD2Z85JsI+MhIJfZq4TxXmpXb/ Jq5HiN89HJ4wr6rXLea/eWyd7618cAZZiB+S4t907FNYoN5Za7XtU53Yo99TffKFQ0cf 44Xmr7D3BCBiDEaJRA6+UHWtBWBj4mZwYkdJuNkFUXvTWvqPJQ+tLi4m5dnTjJoqSct8 IsWj6zhrwB+4NlanWGr0JPLUH/XYLaVY04sIYBZkfBiSkR23DgIuGBjyK/H2gFkyPBbE jt5/4gwPqUFkxozHegLbIIK30roYFKpcZHG+a2L3V4oBZU7sNJ0K7b+DJi29MWniwKkO nrBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628544; x=1690220544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NN9VasAt75iFOv6bKm088IUAp3WHizK1u2macVzvnVk=; b=Wb13caU+iqKPvkKsXo1O2jr0ON3Bg49pwnBoGWx2HBeNerbcHmE2N053Nt8SJbe8pn buyFAv3h65w6xlVwU65W1MLSHoSYtUPsTcSFFgCUdAwle9MxcKGKj3DpCfob/Z+B66BX BD8aJfFeztmVGdqe7AX9zp/hLQmDrZfBN0pxj1SRm/VmFZo5JWFUeyJHhq8FZys2GMCJ QpOPslT0alu0gKnAkmpMGx5T5dKZ7a9AwMOyxuzzBrrqxRti/O8H+v6mwiOtQ1TwkE1C tGhtyg3QOKaMxGqUELyM5eE7o8614PDTFwOEZWq8HUTA6/qu7UmEcl0VpoVe7Au+crP+ KaNw== X-Gm-Message-State: AC+VfDyNizGFNIvcwTawbLv3r3+87+u23rvZ4ty7/fkOmrIx5ORcd2l2 vm8OxsRJfM+4ZIChGqxj3zT1tNJa+X1EDskmpg0= X-Google-Smtp-Source: ACHHUZ6JpBB7yANElxTtai7vYezx6pxHzspfxWNJcM+HOCv+99GHSiTFtorTZQaQzhh9nxIlf7DEgQ== X-Received: by 2002:a17:907:5c8:b0:974:7713:293f with SMTP id wg8-20020a17090705c800b009747713293fmr22846007ejb.41.1687628544073; Sat, 24 Jun 2023 10:42:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 08/16] accel: Move HAX hThread to accelerator context Date: Sat, 24 Jun 2023 19:41:13 +0200 Message-Id: <20230624174121.11508-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628605693100001 hThread variable is only used by the HAX accelerator, so move it to the accelerator specific context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 1 - target/i386/hax/hax-i386.h | 3 +++ target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hax/hax-windows.c | 2 +- 5 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a7fae8571e..8b40946afc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -337,7 +337,6 @@ struct CPUState { =20 struct QemuThread *thread; #ifdef _WIN32 - HANDLE hThread; QemuSemaphore sem; #endif int thread_id; diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 4372ee596d..87153f40ab 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -27,6 +27,9 @@ typedef HANDLE hax_fd; extern struct hax_state hax_global; =20 struct AccelCPUState { +#ifdef _WIN32 + HANDLE hThread; +#endif hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index a8512efcd5..5031096760 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -73,7 +73,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); assert(cpu->accel); #ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); + cpu->accel->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 9d9011cc38..18d78e5b6b 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -206,7 +206,7 @@ int hax_vcpu_destroy(CPUState *cpu) hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; #ifdef _WIN32 - CloseHandle(cpu->hThread); + CloseHandle(vcpu->hThread); #endif g_free(vcpu); cpu->accel =3D NULL; diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index bf4b0ad941..4bf6cc08d2 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -476,7 +476,7 @@ void hax_kick_vcpu_thread(CPUState *cpu) */ cpu->exit_request =3D 1; if (!qemu_cpu_is_self(cpu)) { - if (!QueueUserAPC(dummy_apc_func, cpu->hThread, 0)) { + if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) { fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n", __func__, GetLastError()); exit(1); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628580; cv=none; d=zohomail.com; s=zohoarc; b=VcJhZhN2C40W/bU7RpYfeavWYKlnHOqxnU5C/nf1pyVDz7y75OUPXuWqDFj4ce6ItvHTDi/1qOPNBRDehAQpxJ98EoRVv6atIURTtkRCYljmq4a3tRH588SAmqjoOJnLLsSD7XJ27YwrgUar1gbKFRn3h1uI94P6ANujXZzT09M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628580; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wDJq03Cy4udm0BY/tdQJBSn7cYSDg3Mije1czkKCJYY=; b=f6/pG95ZElAkUbIhzvEjzA+T6ghMVaNDe8EY+aEeEaysZ3nUz+VN1F5qNe1HeLkG984yI5niCc4w6hjtbuulIMqkAUE9mnkac4vmM6WGwp3IC1J+z7AbyuoygAXLGmtrMe7uJet+k0qywnoacYWev7KjADG3QBwIT9RTct3xep0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628580916957.008955212985; Sat, 24 Jun 2023 10:43:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7HQ-0007NL-HJ; Sat, 24 Jun 2023 13:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7HP-0007LW-4S for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:35 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7HN-00070x-I0 for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:34 -0400 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-51bee0c0acbso1695268a12.1 for ; Sat, 24 Jun 2023 10:42:33 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id d15-20020a05640208cf00b0051a3e7d7996sm872902edz.83.2023.06.24.10.42.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628551; x=1690220551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wDJq03Cy4udm0BY/tdQJBSn7cYSDg3Mije1czkKCJYY=; b=RO2avB+FoBAH/Di/V4kIhFyDQH7uIlgC0gwfCgQrD89bwE83AmBBFg0CcRlHBZjeo8 xf712Qc9aR38nPiF+uDaf5yc8gD19WEsCR2svxAprxd1bFxGUA2r4lMmJIlwctgs7QkB EUtMNoLLcY3J6LBbohSpdImmOm/n5GLZ+fA8stYV9O4SnDoSh8DTgNabJ/O9qfxzX4AN 5t1XZJvA/e/bJFTTAZaWg85tev9gNfCnctzxCTxdaNAK3TWI6g6FLKy1iSyDWwm7ICVw UkmuMgdFFe7lQAMN+uYaq3GLpkAMayp43PGSU3d6bHrT+2SGnuNJPvNFppg8VTyk9Otn 2Akg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628551; x=1690220551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wDJq03Cy4udm0BY/tdQJBSn7cYSDg3Mije1czkKCJYY=; b=V3rLE8K1sG81Uofrb9F54dHpbjLugaLQQ754YTVJ81epiaaXzhJAmE5hDQ7AdEDasv m1nXRfuvv0LaP3lDjRIFGW2wq4JvI6mBKbggnRnaXDso69Tw0INT+1khko/cDeoFAyhv uSk3GanpSjnqb9EUUDf10TrNwobU41uFOR0zermH/WRTMOp6X5c1a1pBtTBdFc3f6ssZ CQ89wxG1clUNoPExdjZ/UiPtZse/5Oa/NzTI/2/nhhPLv7Fyd6yEQ+73QFSKgTO4DA0P LJ9yhzR8XxK3YubYtpG6Kp8DBeTKIbCD5ryfkPX3egl9PQrZ5ikx7Xp5RRvUTFs3+gyC 2UXQ== X-Gm-Message-State: AC+VfDwPtxwW+XLXKFFj294uvexyXaYpKzak5Z6MsTaHyugtYoKKhpeV HdQopE2J3g1EWCel//WZJZVqqqE2dH0FUjRvwRE= X-Google-Smtp-Source: ACHHUZ4FYM2a+yRGrt0ZR/p6B5z15VUL79T2BhspQcZnT7ZhY2JGOdCOYx1WSa4ydzRjjHwIT6bFeg== X-Received: by 2002:aa7:cb47:0:b0:51d:9130:3c54 with SMTP id w7-20020aa7cb47000000b0051d91303c54mr196875edt.26.1687628551740; Sat, 24 Jun 2023 10:42:31 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 09/16] accel: Remove NVMM unreachable error path Date: Sat, 24 Jun 2023 19:41:14 +0200 Message-Id: <20230624174121.11508-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628581978100003 g_malloc0() can not fail. Remove the unreachable error path. https://developer-old.gnome.org/glib/stable/glib-Memory-Allocation.html#gli= b-Memory-Allocation.description Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/nvmm/nvmm-all.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b3c3adc59a..90e9e0a5b2 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -943,10 +943,6 @@ nvmm_init_vcpu(CPUState *cpu) } =20 qcpu =3D g_malloc0(sizeof(*qcpu)); - if (qcpu =3D=3D NULL) { - error_report("NVMM: Failed to allocate VCPU context."); - return -ENOMEM; - } =20 ret =3D nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); if (ret =3D=3D -1) { --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628588; cv=none; d=zohomail.com; s=zohoarc; b=gvw/8qh4dQqQnPmX2gUOPgTg99zi7HVax6ylsnc9dmKrVypHwX7VkGFWXSn6SRDVGpHPV9r30FeXgGreH56jPMkUi+hd2Utz+KzJP2uH9PLvqXaqSKQxAq+hrCR28lylRb6/oHyF5u0irHQvUkbeITvCd7d5KaTzQMGtfkIJpic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628588; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6yG7uyZQhQuE8IRVfm1616U0ICNkMM4p4uOU/m5IL/M=; b=DGx6ToGuOsnV2gy2hLEmgD/SjsbbZYQfggKr/SkvLpURfw79/t4BG0etUxT/6Jm3Wh3f0sPgd4LrnpU7qqc0wN38rpnN+cMd4VJm2KLx0qAiPJ6oQIel3TjsFjA/+iAbhXsyQXVcvj4CWAzJwAh7xvJutag3rB//vDlxkFDFyvo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628588008205.5618551552193; Sat, 24 Jun 2023 10:43:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7HY-0007ml-UO; Sat, 24 Jun 2023 13:42:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7HX-0007gH-GN for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:43 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7HV-0007Bk-MK for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:43 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-98746d7f35dso244484866b.2 for ; Sat, 24 Jun 2023 10:42:41 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id t14-20020a170906948e00b009886aaeb722sm1109079ejx.137.2023.06.24.10.42.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628559; x=1690220559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6yG7uyZQhQuE8IRVfm1616U0ICNkMM4p4uOU/m5IL/M=; b=dxyHvFLOjiM5qIEukAG2xMl1n86ITsN2iybJyGEigjKJVlhy51cYS87u2DPnXQ31pC gHAkCCHkCYY16GPiyHKQbc3JgGIWt8KVZKMQ11bQMxI8wmbkhpXTrhSRIis7MvSzXzGA QqIQX7YU8zRGusA6i+PUsjOKGUGI5MyD+m9fQnHJoKgoqtbykvuvRgFuKcOrXiZ5wK82 d4+FrbU+wLhVnWAPZm65aY66PB+II/Npxd/kMcikCaDIXW9+qED/83zvrvxZ25rk5SV9 YL9Y823LfrKqEK09lhq7IjRqf8oiJ0Vir5S+qOmXMiSNmRx8hZhk6ngn/jDc60j75Spz ZjEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628559; x=1690220559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6yG7uyZQhQuE8IRVfm1616U0ICNkMM4p4uOU/m5IL/M=; b=gQ2CFH5IXc3wTpECairfd1ap9S++xk8liWdc5bCQ9ykJbdIu9OUCCRQJuBbUr5ML4t 2mP5NP0/AAj3ItxqS7QESxokKG32QaUQWa4wAPVvnwx620a3tgEXOKGjDyWx+0kLa4mM idzRCh3p2RArWTTVmiQnW1Gck6uMSZI1ENxPAUciH0D+vtz4JBMiPaT3aFBEiZgAlW10 E07M75KYdDG0ByPLiikrt1OwaaHKx/JNY1GAjXYX/kbNEP6MCVJP6Z5GbgVhWTd13YlS mpwUi3Iuo9NBBbXQ+rkdUiiRv8P2MyCcB1gU5vWVXDBHQT5uLmOCF0mdYG+9/42uVxnR bfHQ== X-Gm-Message-State: AC+VfDz3ud9+FiCQWjxiTCHREOyQXnKLuO7vxWee5nSuWdtx3MSCEQcS eKz7hDaC2FadyYZR1z8ruIoZi9Q3htijEPrSRGU= X-Google-Smtp-Source: ACHHUZ60zeHeS0keOdxvMmlIP6tQPqVFwiu+Q/14meF2x41zpcQ/taPA6Be68P7WOGnSc/Te+Ujdng== X-Received: by 2002:a17:907:360e:b0:96a:4ea0:a1e7 with SMTP id bk14-20020a170907360e00b0096a4ea0a1e7mr23798201ejc.50.1687628559647; Sat, 24 Jun 2023 10:42:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 10/16] accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState Date: Sat, 24 Jun 2023 19:41:15 +0200 Message-Id: <20230624174121.11508-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628590067100003 We want all accelerators to share the same opaque pointer in CPUState. Rename NVMM 'qemu_vcpu' as 'AccelCPUState'; directly use the typedef, remove unnecessary casts. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 90e9e0a5b2..e5ee4af084 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -26,7 +26,7 @@ =20 #include =20 -struct qemu_vcpu { +struct AccelCPUState { struct nvmm_vcpu vcpu; uint8_t tpr; bool stop; @@ -49,10 +49,10 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static struct qemu_vcpu * +static AccelCPUState * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->accel; + return cpu->accel; } =20 static struct nvmm_machine * @@ -86,7 +86,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +223,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +347,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +372,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +395,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +478,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +565,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +610,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +686,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +892,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(current_cpu); #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -926,7 +926,7 @@ nvmm_init_vcpu(CPUState *cpu) struct nvmm_vcpu_conf_cpuid cpuid; struct nvmm_vcpu_conf_tpr tpr; Error *local_error =3D NULL; - struct qemu_vcpu *qcpu; + AccelCPUState *qcpu; int ret, err; =20 nvmm_init_cpu_signals(); @@ -942,7 +942,7 @@ nvmm_init_vcpu(CPUState *cpu) } } =20 - qcpu =3D g_malloc0(sizeof(*qcpu)); + qcpu =3D g_new0(AccelCPUState, 1); =20 ret =3D nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); if (ret =3D=3D -1) { @@ -1023,7 +1023,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628670; cv=none; d=zohomail.com; s=zohoarc; b=DM8eokN0gAL2aKCSt1EiRyQVQknCiE+WXbBMPocxtnPwG1UB3TfBEuMJ83LQwhurGG4KaeFZm0GfbPei+riJbO5yCUHUaZooYw2jL1SY5oN5k1yQReCxCG8oc2ElK65uIM2zzCD1Ti5kyN/hoVaNJNro6y4xpDwHjY2rryc8ikU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628670; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=op05vfUAX1M3Sv7qs3sw3v39U7zORQkGDmdogVHbS1k=; b=lvUVPvm1i8xQS453cS1id+u87OqVcoQo6gy5ye3aKm5tOsyx8UuDLJibgnayX+LEsyoclpU0mKuSbPekYjbf9PgQPmzQGPySoxVlqEQ7IBCTJlUX4TDL4MEQlVtmMLOoNQ0lXj5NX1VnfLO1qWLkfZ8IFWGm/9M/NC5kiSe1oCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628670509911.3672631144757; Sat, 24 Jun 2023 10:44:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7Hg-00087w-HF; Sat, 24 Jun 2023 13:42:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7He-00081T-Em for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:50 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7Hc-0007RM-By for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:50 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3fa7cd95dacso21217635e9.3 for ; Sat, 24 Jun 2023 10:42:47 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id q6-20020a7bce86000000b003f7ea771b5dsm2752650wmj.1.2023.06.24.10.42.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628567; x=1690220567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=op05vfUAX1M3Sv7qs3sw3v39U7zORQkGDmdogVHbS1k=; b=RJYQmK2dluQ/bCElwZXIIY1LD41h1/XaVwvVg8wSWNXJc07PlWVevXeiJ5aPZpO0Y7 Z1Mav2iYe3ECYz2tzxRgxo3JHBRfUe20wng9r7Jiv8QfuJqPhx5ajypQ6zgsMeF3mFkE 8Sed9QNqt76GTSbZefh09JZpTjZaNzBhq4efS73Y5DvzVgnD4Qp9rhbnnQXBGUxuvEaq yy7qUcr+89Nv63DXeB02W+9ylYZGNB3FEpFjatx5uZMbKoAxNYWa1O+176v+JwPcDjfv kOBlKV4J96Zi0Gf3gwB1AnoxdGSP6r699mTBZ4haMqN6ZHOlLTbnMhTspiaCics4jkjW rhwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628567; x=1690220567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=op05vfUAX1M3Sv7qs3sw3v39U7zORQkGDmdogVHbS1k=; b=Geh7d8m6L9J4PRfAMsbm/i+dHHEfbXXIFoBB915fcd0kcnMjVXqdYMtCDI1xYeThLq vjBJiApZ48THO/NZqbTdmGd3NLHjTe/PrUl9qwtm520OsiA7qN9ZhUeSm0wwZadyCTz8 NcEvNuvb7ckeX4F7V4wUssEtlq/J2WlgxmHZvQWcCiiHKKr7RgptMwCJyKxFEY2JxPqG lDEn+WnjSx5JXI6RSZU8Z6wLVqETfJ29ERPoHAohJK2kUwGX5S7IfLBwTK4ctQr8ypY2 UVhFb4GzbWW6r2kjWU2xjXmO+8KG5nSS9z0B1PiZ0wAXLzkyb44hDPNSWLil9+xWhVEx mk1Q== X-Gm-Message-State: AC+VfDxIxo7lSZ/RFnwB+TTiNk3pT0d3oLB6aFKHG+cbwVt+C4PEGwmw ZmEgWG27VJCdU5ezT9tiTy8nYM5Q5cQZHaazAik= X-Google-Smtp-Source: ACHHUZ7X7jLi/v3awNWluzxBZUhpVWl7iOZemFneJv8KElxp32UetPs7a+ASZHGCEDVytT3X67X+6Q== X-Received: by 2002:a05:600c:231a:b0:3f9:b430:199b with SMTP id 26-20020a05600c231a00b003f9b430199bmr12673550wmo.15.1687628566856; Sat, 24 Jun 2023 10:42:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 11/16] accel: Inline NVMM get_qemu_vcpu() Date: Sat, 24 Jun 2023 19:41:16 +0200 Message-Id: <20230624174121.11508-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628672326100001 No need for this helper to access the CPUState::accel field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index e5ee4af084..72a3a9e3ae 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -49,12 +49,6 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static AccelCPUState * -get_qemu_vcpu(CPUState *cpu) -{ - return cpu->accel; -} - static struct nvmm_machine * get_nvmm_mach(void) { @@ -86,7 +80,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +217,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +341,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +366,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +389,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +472,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +559,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +604,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +680,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +886,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu =3D current_cpu->accel; #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -1023,7 +1017,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628629; cv=none; d=zohomail.com; s=zohoarc; b=D4Xmqfiiu80YUY3m/SAvYGYq8p5fQAuw0zhgHjB7LSfAWVTw8eo1IL3BbdAdhkbDTdR5Im/PapjciAAMCp9gxfiqPo5czIJx/fAC1o5VQcFuS9toWx7EeUh/h6+QCL9BVlBGq/aPfJWjnZIJMS2luaUITGCYpOioXYTZCvLijRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628629; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lnzdpi/SMqQKnah+FjHhFaYorhth+hVWT4q3k+G9Eas=; b=kQXBbdCIaRI1HZGKfxe3Fd41fzwsv/MsrByMxCo3LuQ6/SzuXSxc8/OIDbsIp6qHGW3plG8pVy7bzXrrjZ/fvjBTbXmH7ltXtGpcyVs779EVQQg0I3Oa+iVKi1mUBt+TDxFL0iWHAGXcprW/DJlTaY0pnp8uWm9D9lWp4pW9zqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628629747956.4766337505268; Sat, 24 Jun 2023 10:43:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7Hn-0008Om-KD; Sat, 24 Jun 2023 13:42:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7Hm-0008Kr-06 for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:58 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7Hj-0007Z4-Lc for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:42:57 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3fa23c3e618so23392815e9.0 for ; Sat, 24 Jun 2023 10:42:55 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id i5-20020a05600c290500b003f9b66a9376sm5651642wmd.42.2023.06.24.10.42.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628573; x=1690220573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lnzdpi/SMqQKnah+FjHhFaYorhth+hVWT4q3k+G9Eas=; b=Rl+gIz/1qET6eDxSMKBlhgEu7TmyZ3qVvdZ/pF7ESuaDiAgqa0TRaV3uHvFx81SIeJ qV48l02FA5t/FTKOknHNBLfCx5Ba1eIp6WEdUkWmn7UkdBYryX6Psh7GsUfx5W+xyxkL 3c8KjhetLy0GIjWOUWB3ntdnDUeOwr94g+1P+m5shTihxl+S6wUTSEMW3Qlx3DI6NP2l vrLr9dXR9+akQkWnsGaMqcGp/3u5JivD0nZdZrXF6pZOBFyTPj2x9FDEPXRcn+qIk9nD 5gqJesBceAKK2qgsqePd5rhjrvRO65NK/VxnJZ9g/MTCIDd+ugMpSpYXChqlyNwCrEuQ lcrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628573; x=1690220573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lnzdpi/SMqQKnah+FjHhFaYorhth+hVWT4q3k+G9Eas=; b=gbqersA2tTAjGEoeHYzbVZLAy2Lk2/aVIGGxd0UAQj4jBQh1M8ZGmJ8VYiFH3RbxPW C6HV0txz5RzfPv1duoNvPaUoqFA9abYFs2h2tYiy12cbJx8uAK8VA+e1mWcainq2fQED 5BFhSqyuu1GQHYJlCivflsDlinTF7AtjfSaBLprRrCYeW8yKSheeqvzK469H50c5edHo n4LBuPsyQuqcBBbUA3YdMVjW3OUHRifVA7Qg5iZ/pkyNn4b/1aAYGhGav68+pcVHRJHn uXIx1ckNpvjmbyS5R9S1Uji2wOgknNyUY36JEULmuX6Rj3qCH8UM4ll8eMJI34ZFht/y oj2w== X-Gm-Message-State: AC+VfDxOQH2WIPzXQvuIdFqQLJ2gq+kDmyFGEvg+PhoE5umoEsWtCqPM 6Uc4KLSboGT1o1IyNCSqHjLPXXU9iJwYdtgKKHk= X-Google-Smtp-Source: ACHHUZ54XAa6Du/8XTOzNhZjWrdIxzwHN95ahuIY8Dglo2ED7aclOY9r3VnonPY6Q+CxQ2enFMDFBQ== X-Received: by 2002:a5d:4c49:0:b0:307:9702:dfc8 with SMTP id n9-20020a5d4c49000000b003079702dfc8mr21407001wrt.48.1687628573655; Sat, 24 Jun 2023 10:42:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 12/16] accel: Remove WHPX unreachable error path Date: Sat, 24 Jun 2023 19:41:17 +0200 Message-Id: <20230624174121.11508-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628630148100003 g_new0() can not fail. Remove the unreachable error path. https://developer-old.gnome.org/glib/stable/glib-Memory-Allocation.html#gli= b-Memory-Allocation.description Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 410b34d8ec..cad7bd0f88 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2179,12 +2179,6 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu =3D g_new0(struct whpx_vcpu, 1); =20 - if (!vcpu) { - error_report("WHPX: Failed to allocte VCPU context."); - ret =3D -ENOMEM; - goto error; - } - hr =3D whp_dispatch.WHvEmulatorCreateEmulator( &whpx_emu_callbacks, &vcpu->emulator); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628676; cv=none; d=zohomail.com; s=zohoarc; b=lboOJMW3lPICDNhMYhXu4k3osT+UqzPYm/wp8XiCmy7AM/y55ZqB3aqjNaiB8pBjDXe2dhx9tPJQQ8FeKLKsPgu/ItjQLm7V2WsfSXJ33lvnL2ZpVq1oeQ+ZksXptEkvoa0RbCPwcODwi+frr6lb+7QAvi9e1ub+w2AwHcjJqIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628676; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F3YC9GFHrwXVDf1ItgmDmu2S/mgeY2SHKESPMbekbhg=; b=GbcyRWRX9y1PefrAsQpMXoNEdakx/jGPewrbxDoMctil0w+OcJHtTm6T6DPEkVE5NRjAo9lPYOL79wu5TFUVoCPv4DYHY8jckTb5GvXNHo/DDNVGLgCWzqKzvO0na/ilfDUlqsZYmWZ6lxLwWitapzK5FRtMlmjIRyDu1wI8PeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628676722406.2020443645122; Sat, 24 Jun 2023 10:44:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7I2-0000WX-5P; Sat, 24 Jun 2023 13:43:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7Ht-0000N0-5M for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:05 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7Hr-0007gm-4A for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:04 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fa79605a3bso15801675e9.0 for ; Sat, 24 Jun 2023 10:43:02 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id x24-20020a05600c21d800b003f858ae8f9dsm5627374wmj.31.2023.06.24.10.42.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628581; x=1690220581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F3YC9GFHrwXVDf1ItgmDmu2S/mgeY2SHKESPMbekbhg=; b=ISbZ7BY9b4/Aq+EjBk8eGpZlBPuqZIMbCL1Z2KOFPMZz5ox8oBaCrkDc4FubFKawGY 1tL2W1BGOVdUJvioaccKvPFxa0fEaw7zU/sU/n+FO2BpC/1IPS2fD/EtnxEeMc5v/tPg VwJX1jKjSp14BD9fIrvVzF/tQyR/m/xhTXl78ZfsDcfFUGIsFaXjG37CDoNuPmVipyz6 TINz55AJXSQbJ3aFJm4lg1dDwZMk2T/PkUao90+jkPyulQ+K2D88yQgTzzMeJPYQvf8G 3ti4QnkgoEQLWxpgFzIGE6kJzwKx6tnpeaUv8ETipQZdlWQyYpmoT8rKxNFuLXCiunZb t+uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628581; x=1690220581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F3YC9GFHrwXVDf1ItgmDmu2S/mgeY2SHKESPMbekbhg=; b=ZpPVZvRSIYMDt0ZAgO2ars0/U9JZB/xUpt+dYLCf+mc0pDgnCc31Gbbmqaa1oOo5mP g0cIwd4x7rsyKNX/58s9WYRAfp4kCVVpk9502KfCPSH+0Fa9waHNLJaPPMAimbKrocxO RXxLR3VA+pgl0G7o/b55t6gQ7DqcNHssDdCeCDfDNiyRZcX8cyFV1aQDseEXbbhK8NO0 PzsFQDAZfEbXB9ukMJYLkUVfbnXGMRaq/JVxP2dby01ON4dZpr/FIsrloD1OZSKXm72Z IwXr8lPKNNr3M6Bw51rMjtm0sFA8AjG77fIYnyVIgC4LLu/C2+eCnEdDu4/fJwhn2jy2 txBw== X-Gm-Message-State: AC+VfDyyUUHhBmv/DZs+cDAZ0fKvdCObsDMY7EoWALv1hBADG/c+knRD aCRyE6XiaqJHSKb1sZx1tIFMrc489fAu1NdzZbg= X-Google-Smtp-Source: ACHHUZ6x1kJtmnLWyDej5xX9yS3xNdJXqxD8xkB+g+E8OEa6HcSaTMV73YfM1pIWCauIJs3hjcdCpQ== X-Received: by 2002:a7b:cb04:0:b0:3f7:ecdf:ab2d with SMTP id u4-20020a7bcb04000000b003f7ecdfab2dmr24480622wmj.20.1687628581315; Sat, 24 Jun 2023 10:43:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 13/16] accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUState Date: Sat, 24 Jun 2023 19:41:18 +0200 Message-Id: <20230624174121.11508-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628678299100001 We want all accelerators to share the same opaque pointer in CPUState. Rename WHPX 'whpx_vcpu' as 'AccelCPUState'; use the typedef. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index cad7bd0f88..4ddd2d076a 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -229,7 +229,7 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct whpx_vcpu { +struct AccelCPUState { WHV_EMULATOR_HANDLE emulator; bool window_registered; bool interruptable; @@ -260,9 +260,9 @@ static bool whpx_has_xsave(void) * VP support */ =20 -static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) +static AccelCPUState *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->accel; + return (AccelCPUState *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -390,7 +390,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +609,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +892,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1417,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1468,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1590,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1617,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1656,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2154,7 +2154,7 @@ int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D NULL; + AccelCPUState *vcpu =3D NULL; Error *local_error =3D NULL; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -2177,7 +2177,7 @@ int whpx_init_vcpu(CPUState *cpu) } } =20 - vcpu =3D g_new0(struct whpx_vcpu, 1); + vcpu =3D g_new0(AccelCPUState, 1); =20 hr =3D whp_dispatch.WHvEmulatorCreateEmulator( &whpx_emu_callbacks, @@ -2290,7 +2290,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628658; cv=none; d=zohomail.com; s=zohoarc; b=CX3WwcW0+uxnEtEg5cgzj6vbrReTbuGVq3z2/+ZG+Sa5zxFHr3e7bgkV6MP1DyyGJlE+k4EHsKPQp/Y+LQdx7n5q9QWba1u3QbE250KmYqcJqdUENfUBu6g/o1zaIFebFt9PDiSHVkdY4W7N8TXLaxgktRut3n89prNzV4eYbX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628658; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AAPkMuMtNtRM9NXu99LXesVy8JoKNyay4INBIgU8fUM=; b=GzaCVVnPM3lkKV7rGur0a1a/IylWuohuUo0c1LvkfALKP6Hq/hoqTcEQEh3GzUEVCcRIX84fAt4L6MIo65P7yuipQU2kZQZyRMKO+UbqFo5uH17SSrokCjVeNyNsjsl9E1mudnMjxgBBMcYl8yJ4DIvUN/qk83fYm1oMoCy10NI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168762865808752.129784359912605; Sat, 24 Jun 2023 10:44:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7I6-0000kM-Pq; Sat, 24 Jun 2023 13:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7I1-0000Wx-7e for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:14 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7Hz-0007iX-IG for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:12 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f918922954so17425355e9.2 for ; Sat, 24 Jun 2023 10:43:11 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id k21-20020a05600c0b5500b003fa88f4c0f5sm339874wmr.21.2023.06.24.10.43.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:43:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628589; x=1690220589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AAPkMuMtNtRM9NXu99LXesVy8JoKNyay4INBIgU8fUM=; b=pDVczrLfie0P29Z7uCw5tOy4PEx87NBQoCGG3m0psbZUusSwEfLQ61OZL6TJ2kB1dJ tATN6G8yFgnC5O7/RtL7/IHp8luOuI9a0CAQzgEMx9UDPTQXlvR8sbrOYZG8bJrmUNQg /3FBzLpY41RnRaYP2NB0XTbSnaGO4aPWfsRV67qdMMOJR8x1sXQNb8tfR8/K7nF4Lssa 0KusLp2BM/Iws8Bzl7b9wq8cOsydsbBlEYgdjHb92A4e1Ui8CCXvSdCXeW32PC8Pi/zU qYoeGCSAHTqFSWULi9I7GFgtd8QD3Ykjh8zHuYSguFeSZJas3CSglD3lc6I5XkKu7nti YLBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628589; x=1690220589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AAPkMuMtNtRM9NXu99LXesVy8JoKNyay4INBIgU8fUM=; b=V947zw48F/gQDexRNV1HDEccef/P0T707hzaomnx6NGqJRded/FzanmDTIBR5yS+bm vTnKAMeUhkCzEulorrKCbh2pAT+HwFuHTOBVt8PHgTazvU8OLtONHPNROzp/jr5VyWdU klaMsEKnTs+l78w0pRGHg1/6yzS0KWJ4xDmybARPtJUTql2Hyk73Xt6TJ3GcZjVQNfSp U802yhhYZvMmO3XnMIa2x58K5rCOBFWoUIUObr2O3+e/7Sc7B1LwLsd54amVaX927t1g lkqptBPzGp3gf7Vb49VRShlcLWSHWmKgzow2/5mQMuPD2iTjhN5jwNxdxw9Y8nG/t01h 5oCg== X-Gm-Message-State: AC+VfDxKw5/Pm0BOdM6NC/Eg68ZaiOXifa9FCnFZDXVuZEEWSX5oSGju 19fQG4JIhFs+KcHoP20mN8+fxCwiuhCFeQxXGxM= X-Google-Smtp-Source: ACHHUZ4238DSm93lZDXfUQaXb230UfiIqG/QwG8MlbO96c7eSEYZDPLm8Y7CfJuFqwRBJ3ZTi98IIA== X-Received: by 2002:a05:600c:2158:b0:3f9:aaa:37e7 with SMTP id v24-20020a05600c215800b003f90aaa37e7mr13332459wml.0.1687628589383; Sat, 24 Jun 2023 10:43:09 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 14/16] accel: Inline WHPX get_whpx_vcpu() Date: Sat, 24 Jun 2023 19:41:19 +0200 Message-Id: <20230624174121.11508-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628660269100003 No need for this helper to access the CPUState::accel field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/whpx/whpx-all.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 4ddd2d076a..0903327ac5 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -256,15 +256,6 @@ static bool whpx_has_xsave(void) return whpx_xsave_cap.XsaveSupport; } =20 -/* - * VP support - */ - -static AccelCPUState *get_whpx_vcpu(CPUState *cpu) -{ - return (AccelCPUState *)cpu->accel; -} - static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, int r86) { @@ -390,7 +381,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +600,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +883,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +908,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1408,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1459,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1581,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1608,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1647,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2290,7 +2281,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628668; cv=none; d=zohomail.com; s=zohoarc; b=JQx4jCB1DxzsijHzXXc5tyHRnVfVZZc6mdjnM9TBc1f120BajdBNEJoQ10KVDn00Hhekq1uuqqpZJQuT7IOir5dGk13HO1imBfHs8Me1O5knQO7X0XsWyQEw9hR3fiRtNn4RHvl4kWAeW1r1wg/6qfP7W6t6aMJUqwtfOuNZLrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628668; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cbsgyJj8b56jpRAu2aJb3zjkuNeKq4dUo/g8B8wkaF0=; b=ipL2181H+s3UuHe2mDpjbC6TlV2AjpBeJB80VV9ne6mlSxjcR7mtGNXYu5l65J9i5WcRVOfFPnL2iXaB15ANo03Xfs7VcH+4Kt3pBjhFeqGk5VHaRHXOHJPG4p22o41iBnXiMHK9FYAoCv+UFEPNCjM42NvyFe1+JMOb6N4HO2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628668037903.1521499341819; Sat, 24 Jun 2023 10:44:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7II-0001S1-AP; Sat, 24 Jun 2023 13:43:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7IA-0001Bv-O5 for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:22 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7I7-0007kX-26 for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:22 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f9189228bcso17661335e9.3 for ; Sat, 24 Jun 2023 10:43:18 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id p9-20020a05600c204900b003f93c450657sm2686567wmg.38.2023.06.24.10.43.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628597; x=1690220597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cbsgyJj8b56jpRAu2aJb3zjkuNeKq4dUo/g8B8wkaF0=; b=XOyq/hOpaM8SFEeLc2i/ZJNmFV8x6n66YcKZE2GZIGtdj5zxHMC6g2SOgudJ4+fZ8h nZbhJ/kN1HwORDYtYdsoPyEYbVf23TRKqu5FYSP2ZazSRUBKekkGRd4kdk/awn5igQ1b zRbp90njgUwVUvHLjJjw1VUI0PSgwJx2yKIq6pzmwo0CZ0h41Is+JoQ2NFOjUSKN7ddg 2GEubtihnZjS3H6yCF/eDUnSwwvtRfp9CMO8gnycmk2HCWoaHaTwjTKz2lKM5XQW5Ijt Cp/V+iKSJYRw6t+f3yeVYB1hJkUg77nYhVIA3BADg2m1Rh/JyQG9mvHJtmL//kiubREW 5pNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628597; x=1690220597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cbsgyJj8b56jpRAu2aJb3zjkuNeKq4dUo/g8B8wkaF0=; b=bzvAG7msJYaUBwvJRa4xvEUUHXDLOjov1mLz/dW/LNQ0bZwiiPU5v2apqphoKzrnux rWzhGyPypVJBiZou15R2zUFAPJwzKTrCUOo5WuLmVY6VpzZMex4UzpB7TLSLHhdy/Ufw rhEWTzyHlDj4BfcXDXb7CKZMMlSCXYIthyk15bZpAmsXWyD/6o2DVPIAUzqpelaPivSO wNpoMe6Ut/nSRKRANqBD+JFHAXRsLWqFssFLjd/qsm7jEY9w2i218hYLTSZcmHnWU4Tc QWh6R6qw1C42xSecn4uZi+B8iQpOKGO1J2CBzH5WIFi/g0FUQQDj7GGwq3Ekrheb7gYc NYJw== X-Gm-Message-State: AC+VfDxT4ZxviUrtngafqXCKrLE04xOfuB1OxmPgZdfT0POQ8WMySvfK 7+5Aljjwuy+rsroDqM5ngXTTFSap7AN6BEW+OP4= X-Google-Smtp-Source: ACHHUZ5H7hPQWwMqXf2hx68EQXiiQZxhhcXxw3MPT5pLhxKkCEnfSo/f+IE4+5mJ6cAP66+MRBOCFw== X-Received: by 2002:a05:600c:3797:b0:3fa:838a:1dcf with SMTP id o23-20020a05600c379700b003fa838a1dcfmr1426420wmr.6.1687628597127; Sat, 24 Jun 2023 10:43:17 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 15/16] accel: Rename 'cpu_state' -> 'cs' Date: Sat, 24 Jun 2023 19:41:20 +0200 Message-Id: <20230624174121.11508-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628668793100003 Most of the codebase uses 'CPUState *cpu' or 'CPUState *cs'. While 'cpu_state' is kind of explicit, it makes the code harder to review. Simply rename as 'cs'. Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Peter Maydell --- target/i386/hvf/x86hvf.h | 18 +- target/i386/hvf/x86hvf.c | 372 +++++++++++++++++++-------------------- 2 files changed, 195 insertions(+), 195 deletions(-) diff --git a/target/i386/hvf/x86hvf.h b/target/i386/hvf/x86hvf.h index db6003d6bd..423a89b6ad 100644 --- a/target/i386/hvf/x86hvf.h +++ b/target/i386/hvf/x86hvf.h @@ -20,15 +20,15 @@ #include "cpu.h" #include "x86_descr.h" =20 -int hvf_process_events(CPUState *); -bool hvf_inject_interrupts(CPUState *); -void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, +int hvf_process_events(CPUState *cs); +bool hvf_inject_interrupts(CPUState *cs); +void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr); void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg); -void hvf_put_xsave(CPUState *cpu_state); -void hvf_put_msrs(CPUState *cpu_state); -void hvf_get_xsave(CPUState *cpu_state); -void hvf_get_msrs(CPUState *cpu_state); -void vmx_clear_int_window_exiting(CPUState *cpu); -void vmx_update_tpr(CPUState *cpu); +void hvf_put_xsave(CPUState *cs); +void hvf_put_msrs(CPUState *cs); +void hvf_get_xsave(CPUState *cs); +void hvf_get_msrs(CPUState *cs); +void vmx_clear_int_window_exiting(CPUState *cs); +void vmx_update_tpr(CPUState *cs); #endif diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 69d4fb8cf5..92dfd26a01 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -32,14 +32,14 @@ #include #include =20 -void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, +void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) { vmx_seg->sel =3D qseg->selector; vmx_seg->base =3D qseg->base; vmx_seg->limit =3D qseg->limit; =20 - if (!qseg->selector && !x86_is_real(cpu) && !is_tr) { + if (!qseg->selector && !x86_is_real(cs) && !is_tr) { /* the TR register is usable after processor reset despite * having a null selector */ vmx_seg->ar =3D 1 << 16; @@ -70,279 +70,279 @@ void hvf_get_segment(SegmentCache *qseg, struct vmx_s= egment *vmx_seg) (((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT); } =20 -void hvf_put_xsave(CPUState *cpu_state) +void hvf_put_xsave(CPUState *cs) { - void *xsave =3D X86_CPU(cpu_state)->env.xsave_buf; - uint32_t xsave_len =3D X86_CPU(cpu_state)->env.xsave_buf_len; + void *xsave =3D X86_CPU(cs)->env.xsave_buf; + uint32_t xsave_len =3D X86_CPU(cs)->env.xsave_buf_len; =20 - x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave, xsave_len); + x86_cpu_xsave_all_areas(X86_CPU(cs), xsave, xsave_len); =20 - if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_write_fpstate(cs->hvf->fd, xsave, xsave_len)) { abort(); } } =20 -static void hvf_put_segments(CPUState *cpu_state) +static void hvf_put_segments(CPUState *cs) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cs)->env; struct vmx_segment seg; =20 - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); =20 - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); =20 - /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); - vmx_update_tpr(cpu_state); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); + /* wvmcs(cs->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cs->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); + vmx_update_tpr(cs); + wvmcs(cs->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]); - macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]); + macvm_set_cr4(cs->hvf->fd, env->cr[4]); + macvm_set_cr0(cs->hvf->fd, env->cr[0]); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_CS); + hvf_set_segment(cs, &seg, &env->segs[R_CS], false); + vmx_write_segment_descriptor(cs, &seg, R_CS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_DS); + hvf_set_segment(cs, &seg, &env->segs[R_DS], false); + vmx_write_segment_descriptor(cs, &seg, R_DS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_ES); + hvf_set_segment(cs, &seg, &env->segs[R_ES], false); + vmx_write_segment_descriptor(cs, &seg, R_ES); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_SS); + hvf_set_segment(cs, &seg, &env->segs[R_SS], false); + vmx_write_segment_descriptor(cs, &seg, R_SS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_FS); + hvf_set_segment(cs, &seg, &env->segs[R_FS], false); + vmx_write_segment_descriptor(cs, &seg, R_FS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_GS); + hvf_set_segment(cs, &seg, &env->segs[R_GS], false); + vmx_write_segment_descriptor(cs, &seg, R_GS); =20 - hvf_set_segment(cpu_state, &seg, &env->tr, true); - vmx_write_segment_descriptor(cpu_state, &seg, R_TR); + hvf_set_segment(cs, &seg, &env->tr, true); + vmx_write_segment_descriptor(cs, &seg, R_TR); =20 - hvf_set_segment(cpu_state, &seg, &env->ldt, false); - vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); + hvf_set_segment(cs, &seg, &env->ldt, false); + vmx_write_segment_descriptor(cs, &seg, R_LDTR); } =20 -void hvf_put_msrs(CPUState *cpu_state) +void hvf_put_msrs(CPUState *cs) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cs)->env; =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cs->hvf->fd, MSR_STAR, env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsb= ase); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cs->hvf->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cs->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); + hv_vcpu_write_msr(cs->hvf->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cs->hvf->fd, MSR_LSTAR, env->lstar); #endif =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base= ); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base= ); + hv_vcpu_write_msr(cs->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); + hv_vcpu_write_msr(cs->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); } =20 =20 -void hvf_get_xsave(CPUState *cpu_state) +void hvf_get_xsave(CPUState *cs) { - void *xsave =3D X86_CPU(cpu_state)->env.xsave_buf; - uint32_t xsave_len =3D X86_CPU(cpu_state)->env.xsave_buf_len; + void *xsave =3D X86_CPU(cs)->env.xsave_buf; + uint32_t xsave_len =3D X86_CPU(cs)->env.xsave_buf_len; =20 - if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_read_fpstate(cs->hvf->fd, xsave, xsave_len)) { abort(); } =20 - x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave, xsave_len); + x86_cpu_xrstor_all_areas(X86_CPU(cs), xsave, xsave_len); } =20 -static void hvf_get_segments(CPUState *cpu_state) +static void hvf_get_segments(CPUState *cs) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cs)->env; =20 struct vmx_segment seg; =20 env->interrupt_injected =3D -1; =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_CS); + vmx_read_segment_descriptor(cs, &seg, R_CS); hvf_get_segment(&env->segs[R_CS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_DS); + vmx_read_segment_descriptor(cs, &seg, R_DS); hvf_get_segment(&env->segs[R_DS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_ES); + vmx_read_segment_descriptor(cs, &seg, R_ES); hvf_get_segment(&env->segs[R_ES], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_FS); + vmx_read_segment_descriptor(cs, &seg, R_FS); hvf_get_segment(&env->segs[R_FS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_GS); + vmx_read_segment_descriptor(cs, &seg, R_GS); hvf_get_segment(&env->segs[R_GS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_SS); + vmx_read_segment_descriptor(cs, &seg, R_SS); hvf_get_segment(&env->segs[R_SS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_TR); + vmx_read_segment_descriptor(cs, &seg, R_TR); hvf_get_segment(&env->tr, &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); + vmx_read_segment_descriptor(cs, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); =20 - env->idt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit =3D rvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base =3D rvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_BASE); =20 - env->cr[0] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0); + env->cr[0] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR0); env->cr[2] =3D 0; - env->cr[3] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3); - env->cr[4] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4); + env->cr[3] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR3); + env->cr[4] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR4); =20 - env->efer =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER); + env->efer =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IA32_EFER); } =20 -void hvf_get_msrs(CPUState *cpu_state) +void hvf_get_msrs(CPUState *cs) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cs)->env; uint64_t tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cs->hvf->fd, MSR_STAR, &env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsb= ase); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cs->hvf->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cs->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); + hv_vcpu_read_msr(cs->hvf->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cs->hvf->fd, MSR_LSTAR, &env->lstar); #endif =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_APICBASE, &tmp); =20 - env->tsc =3D rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET); + env->tsc =3D rdtscp() + rvmcs(cs->hvf->fd, VMCS_TSC_OFFSET); } =20 -int hvf_put_registers(CPUState *cpu_state) +int hvf_put_registers(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86cpu->env; =20 - wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]); - wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]); - wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]); - wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]); - wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]); - wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]); - wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]); - wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]); - wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags); - wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip); + wreg(cs->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cs->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cs->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cs->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cs->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cs->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cs->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cs->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cs->hvf->fd, HV_X86_R8, env->regs[8]); + wreg(cs->hvf->fd, HV_X86_R9, env->regs[9]); + wreg(cs->hvf->fd, HV_X86_R10, env->regs[10]); + wreg(cs->hvf->fd, HV_X86_R11, env->regs[11]); + wreg(cs->hvf->fd, HV_X86_R12, env->regs[12]); + wreg(cs->hvf->fd, HV_X86_R13, env->regs[13]); + wreg(cs->hvf->fd, HV_X86_R14, env->regs[14]); + wreg(cs->hvf->fd, HV_X86_R15, env->regs[15]); + wreg(cs->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cs->hvf->fd, HV_X86_RIP, env->eip); =20 - wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0); + wreg(cs->hvf->fd, HV_X86_XCR0, env->xcr0); =20 - hvf_put_xsave(cpu_state); + hvf_put_xsave(cs); =20 - hvf_put_segments(cpu_state); + hvf_put_segments(cs); =20 - hvf_put_msrs(cpu_state); + hvf_put_msrs(cs); =20 - wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]); - wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]); - wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]); - wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]); - wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]); - wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]); - wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]); - wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]); + wreg(cs->hvf->fd, HV_X86_DR0, env->dr[0]); + wreg(cs->hvf->fd, HV_X86_DR1, env->dr[1]); + wreg(cs->hvf->fd, HV_X86_DR2, env->dr[2]); + wreg(cs->hvf->fd, HV_X86_DR3, env->dr[3]); + wreg(cs->hvf->fd, HV_X86_DR4, env->dr[4]); + wreg(cs->hvf->fd, HV_X86_DR5, env->dr[5]); + wreg(cs->hvf->fd, HV_X86_DR6, env->dr[6]); + wreg(cs->hvf->fd, HV_X86_DR7, env->dr[7]); =20 return 0; } =20 -int hvf_get_registers(CPUState *cpu_state) +int hvf_get_registers(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86cpu->env; =20 - env->regs[R_EAX] =3D rreg(cpu_state->hvf->fd, HV_X86_RAX); - env->regs[R_EBX] =3D rreg(cpu_state->hvf->fd, HV_X86_RBX); - env->regs[R_ECX] =3D rreg(cpu_state->hvf->fd, HV_X86_RCX); - env->regs[R_EDX] =3D rreg(cpu_state->hvf->fd, HV_X86_RDX); - env->regs[R_EBP] =3D rreg(cpu_state->hvf->fd, HV_X86_RBP); - env->regs[R_ESP] =3D rreg(cpu_state->hvf->fd, HV_X86_RSP); - env->regs[R_ESI] =3D rreg(cpu_state->hvf->fd, HV_X86_RSI); - env->regs[R_EDI] =3D rreg(cpu_state->hvf->fd, HV_X86_RDI); - env->regs[8] =3D rreg(cpu_state->hvf->fd, HV_X86_R8); - env->regs[9] =3D rreg(cpu_state->hvf->fd, HV_X86_R9); - env->regs[10] =3D rreg(cpu_state->hvf->fd, HV_X86_R10); - env->regs[11] =3D rreg(cpu_state->hvf->fd, HV_X86_R11); - env->regs[12] =3D rreg(cpu_state->hvf->fd, HV_X86_R12); - env->regs[13] =3D rreg(cpu_state->hvf->fd, HV_X86_R13); - env->regs[14] =3D rreg(cpu_state->hvf->fd, HV_X86_R14); - env->regs[15] =3D rreg(cpu_state->hvf->fd, HV_X86_R15); + env->regs[R_EAX] =3D rreg(cs->hvf->fd, HV_X86_RAX); + env->regs[R_EBX] =3D rreg(cs->hvf->fd, HV_X86_RBX); + env->regs[R_ECX] =3D rreg(cs->hvf->fd, HV_X86_RCX); + env->regs[R_EDX] =3D rreg(cs->hvf->fd, HV_X86_RDX); + env->regs[R_EBP] =3D rreg(cs->hvf->fd, HV_X86_RBP); + env->regs[R_ESP] =3D rreg(cs->hvf->fd, HV_X86_RSP); + env->regs[R_ESI] =3D rreg(cs->hvf->fd, HV_X86_RSI); + env->regs[R_EDI] =3D rreg(cs->hvf->fd, HV_X86_RDI); + env->regs[8] =3D rreg(cs->hvf->fd, HV_X86_R8); + env->regs[9] =3D rreg(cs->hvf->fd, HV_X86_R9); + env->regs[10] =3D rreg(cs->hvf->fd, HV_X86_R10); + env->regs[11] =3D rreg(cs->hvf->fd, HV_X86_R11); + env->regs[12] =3D rreg(cs->hvf->fd, HV_X86_R12); + env->regs[13] =3D rreg(cs->hvf->fd, HV_X86_R13); + env->regs[14] =3D rreg(cs->hvf->fd, HV_X86_R14); + env->regs[15] =3D rreg(cs->hvf->fd, HV_X86_R15); =20 - env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); - env->eip =3D rreg(cpu_state->hvf->fd, HV_X86_RIP); + env->eflags =3D rreg(cs->hvf->fd, HV_X86_RFLAGS); + env->eip =3D rreg(cs->hvf->fd, HV_X86_RIP); =20 - hvf_get_xsave(cpu_state); - env->xcr0 =3D rreg(cpu_state->hvf->fd, HV_X86_XCR0); + hvf_get_xsave(cs); + env->xcr0 =3D rreg(cs->hvf->fd, HV_X86_XCR0); =20 - hvf_get_segments(cpu_state); - hvf_get_msrs(cpu_state); + hvf_get_segments(cs); + hvf_get_msrs(cs); =20 - env->dr[0] =3D rreg(cpu_state->hvf->fd, HV_X86_DR0); - env->dr[1] =3D rreg(cpu_state->hvf->fd, HV_X86_DR1); - env->dr[2] =3D rreg(cpu_state->hvf->fd, HV_X86_DR2); - env->dr[3] =3D rreg(cpu_state->hvf->fd, HV_X86_DR3); - env->dr[4] =3D rreg(cpu_state->hvf->fd, HV_X86_DR4); - env->dr[5] =3D rreg(cpu_state->hvf->fd, HV_X86_DR5); - env->dr[6] =3D rreg(cpu_state->hvf->fd, HV_X86_DR6); - env->dr[7] =3D rreg(cpu_state->hvf->fd, HV_X86_DR7); + env->dr[0] =3D rreg(cs->hvf->fd, HV_X86_DR0); + env->dr[1] =3D rreg(cs->hvf->fd, HV_X86_DR1); + env->dr[2] =3D rreg(cs->hvf->fd, HV_X86_DR2); + env->dr[3] =3D rreg(cs->hvf->fd, HV_X86_DR3); + env->dr[4] =3D rreg(cs->hvf->fd, HV_X86_DR4); + env->dr[5] =3D rreg(cs->hvf->fd, HV_X86_DR5); + env->dr[6] =3D rreg(cs->hvf->fd, HV_X86_DR6); + env->dr[7] =3D rreg(cs->hvf->fd, HV_X86_DR7); =20 x86_update_hflags(env); return 0; } =20 -static void vmx_set_int_window_exiting(CPUState *cpu) +static void vmx_set_int_window_exiting(CPUState *cs) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 -void vmx_clear_int_window_exiting(CPUState *cpu) +void vmx_clear_int_window_exiting(CPUState *cs) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 -bool hvf_inject_interrupts(CPUState *cpu_state) +bool hvf_inject_interrupts(CPUState *cs) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86cpu->env; =20 uint8_t vector; @@ -372,89 +372,89 @@ bool hvf_inject_interrupts(CPUState *cpu_state) uint64_t info =3D 0; if (have_event) { info =3D vector | intr_type | VMCS_INTR_VALID; - uint64_t reason =3D rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON); + uint64_t reason =3D rvmcs(cs->hvf->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { - vmx_clear_nmi_blocking(cpu_state); + vmx_clear_nmi_blocking(cs); } =20 if (!(env->hflags2 & HF2_NMI_MASK) || intr_type !=3D VMCS_INTR_T_N= MI) { info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins= _len); + wvmcs(cs->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); } =20 if (env->has_error_code) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cs->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |=3D VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, info); }; } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) { + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, info); } else { - vmx_set_nmi_window_exiting(cpu_state); + vmx_set_nmi_window_exiting(cs); } } =20 if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && - (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && + (cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { int line =3D cpu_get_pic_interrupt(&x86cpu->env); - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } - if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) { - vmx_set_int_window_exiting(cpu_state); + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + vmx_set_int_window_exiting(cs); } - return (cpu_state->interrupt_request + return (cs->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)); } =20 -int hvf_process_events(CPUState *cpu_state) +int hvf_process_events(CPUState *cs) { - X86CPU *cpu =3D X86_CPU(cpu_state); + X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 - if (!cpu_state->vcpu_dirty) { + if (!cs->vcpu_dirty) { /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ - env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cs->hvf->fd, HV_X86_RFLAGS); } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { - cpu_synchronize_state(cpu_state); + if (cs->interrupt_request & CPU_INTERRUPT_INIT) { + cpu_synchronize_state(cs); do_cpu_init(cpu); } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + if (cs->interrupt_request & CPU_INTERRUPT_POLL) { + cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); } - if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && + if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) { - cpu_state->halted =3D 0; + (cs->interrupt_request & CPU_INTERRUPT_NMI)) { + cs->halted =3D 0; } - if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { - cpu_synchronize_state(cpu_state); + if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { + cpu_synchronize_state(cs); do_cpu_sipi(cpu); } - if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_TPR; - cpu_synchronize_state(cpu_state); + if (cs->interrupt_request & CPU_INTERRUPT_TPR) { + cs->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + cpu_synchronize_state(cs); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); } - return cpu_state->halted; + return cs->halted; } --=20 2.38.1 From nobody Sun May 12 04:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687628638; cv=none; d=zohomail.com; s=zohoarc; b=kY+AW6Vf//7Czx5HXEbzP+HKQ9CjOa9hZgnOLRemQFClhBGKz3laKegsrvMy3kDX0PoRlneBh0E1Wb+Mrr1FHH8f1oUjgjbRrGIXor7AbKZRPb/VR8rDFixfagLHEzK4wU75J+py5lfm1llq3ocEJeRJmiKMn2Gp5xbFuqYodmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687628638; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C0Bvqma/PIbc9szv5rXD5PzzsFB6qHMXrjecr7RadWU=; b=h7e8mJKTfpV5IJEQpTkiV5oEVjB8GqG7bxZMVYh6isKVI3zXYwhMoEvjj7uVZcVldSf4a8ETmJcuPWePrZE+K1CmlXFCXG/Y/hUxTrUuNe6C/N5C14wmgTibOcMCJb+UrPT5uX+SPytGJv2H5nh8WLTwg7p3S7Yv6/o1ebFRaNk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687628638055749.4524000256853; Sat, 24 Jun 2023 10:43:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qD7IY-0001nY-Mt; Sat, 24 Jun 2023 13:43:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qD7IJ-0001WT-Nh for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:32 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qD7IF-0007lq-Hg for qemu-devel@nongnu.org; Sat, 24 Jun 2023 13:43:31 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f9b0f139feso23083065e9.3 for ; Sat, 24 Jun 2023 10:43:27 -0700 (PDT) Received: from m1x-phil.lan ([176.187.217.150]) by smtp.gmail.com with ESMTPSA id y12-20020a05600c364c00b003f7f249e7dfsm5700086wmq.4.2023.06.24.10.43.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 24 Jun 2023 10:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687628606; x=1690220606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C0Bvqma/PIbc9szv5rXD5PzzsFB6qHMXrjecr7RadWU=; b=IxyiXwFOUTB2k4fUsiDG4PjBDtKmXZ/H0RRK6FbQGL6dhNvM9eM9VsKz8ZrLn3wNPm nuXnWGhuJNQ9KmqCoT9LGoXrJqhuJM0RTuBJmBW3WJzFzbliEATNqyxMNjNcW4jgxNsD fuJeuRKsoa4f66qzpHCmch357722qBVaF34Ut/Xkdo7Wd5Yhnil9aJxPk1XDlzV+995Z ybRRqbmBuq8fbmDKb5kP2eQ9YxrJZO1e4547tk/awkwCnEcOs4OhXkKqLvvajERmajwK PGOU0jMuzvR3Ur6Dc4ujO+CKZtWNTt3u0NJn/Kwpeop+39t9o4+LlvBaxcZTjJmj1Xz3 LLJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687628606; x=1690220606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C0Bvqma/PIbc9szv5rXD5PzzsFB6qHMXrjecr7RadWU=; b=hEeBzpQ9dd7WMLliaAytIMkftf9tYqfeyO6Pw89n9UiVhrWrN4bfn+NlAydpQYQbbS CPSk80CsZ+dkn0w4BAnveesot9Z80SDLjUAa70IfZ74Kq5LlBn+LFUW6EFiJ5PcM/NXU K7NoBZ6x0Uzv9jFLzWwasI1ZT6MUcJeDsSghz9l+dGAgF2+AY/EcbD3pCpg3qZy6CCpu KckaMyYzKlCa7W5MdZg0P/G6j1iXnk9VDgBhay+WeejwidMtTHJv/ZSTJKz2/LWKuoCE s3u+2BbokE5FPPp//WHXdid74ftKBgrhDlMF0GtRT40dD9Q6JjnUxkFQGVOfGfX8mxr/ 5E5Q== X-Gm-Message-State: AC+VfDwex45ACTWTkRQSjZSJClQKIrjY3B//YJCBS5gLRYhOaz/jZz8Y 4pkbyQ5wTZ/vsZ0hubyD5oaYh9y0gBH1SGYrrDA= X-Google-Smtp-Source: ACHHUZ5HltMJmzvYTBE0TkT8wKWtTPaC1UYEA2DegWtnQnY1S7XP4JoV5kk01yfeAA81LjTPtObXPw== X-Received: by 2002:a7b:cb99:0:b0:3f9:c9bc:401 with SMTP id m25-20020a7bcb99000000b003f9c9bc0401mr8386273wmi.33.1687628605005; Sat, 24 Jun 2023 10:43:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 16/16] accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUState Date: Sat, 24 Jun 2023 19:41:21 +0200 Message-Id: <20230624174121.11508-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628640198100003 We want all accelerators to share the same opaque pointer in CPUState. Rename the 'hvf_vcpu_state' structure as 'AccelCPUState'. Use the generic 'accel' field of CPUState instead of 'hvf'. Replace g_malloc0() by g_new0() for readability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Peter Maydell --- Not even built on x86! --- include/hw/core/cpu.h | 4 - include/sysemu/hvf_int.h | 2 +- target/i386/hvf/vmx.h | 22 ++-- accel/hvf/hvf-accel-ops.c | 18 ++-- target/arm/hvf/hvf.c | 108 +++++++++---------- target/i386/hvf/hvf.c | 104 +++++++++--------- target/i386/hvf/x86.c | 28 ++--- target/i386/hvf/x86_descr.c | 26 ++--- target/i386/hvf/x86_emu.c | 62 +++++------ target/i386/hvf/x86_mmu.c | 4 +- target/i386/hvf/x86_task.c | 10 +- target/i386/hvf/x86hvf.c | 208 ++++++++++++++++++------------------ 12 files changed, 296 insertions(+), 300 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8b40946afc..44c91240f2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -240,8 +240,6 @@ typedef struct SavedIOTLB { struct KVMState; struct kvm_run; =20 -struct hvf_vcpu_state; - /* work queue */ =20 /* The union type allows passing of 64 bit target pointers on 32 bit @@ -441,8 +439,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hvf_vcpu_state *hvf; - /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; }; diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 6ab119e49f..718beddcdd 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -49,7 +49,7 @@ struct HVFState { }; extern HVFState *hvf_state; =20 -struct hvf_vcpu_state { +struct AccelCPUState { uint64_t fd; void *exit; bool vtimer_masked; diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index fcd9a95e5b..0fffcfa46c 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -180,15 +180,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint6= 4_t rip) uint64_t val; =20 /* BUG, should take considering overlap.. */ - wreg(cpu->hvf->fd, HV_X86_RIP, rip); + wreg(cpu->accel->fd, HV_X86_RIP, rip); env->eip =3D rip; =20 /* after moving forward in rip, we need to clean INTERRUPTABILITY */ - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); } @@ -200,9 +200,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 &=3D ~HF2_NMI_MASK; - uint32_t gi =3D (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBI= LITY); + uint32_t gi =3D (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTI= BILITY); gi &=3D ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_blocking(CPUState *cpu) @@ -211,16 +211,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 |=3D HF2_NMI_MASK; - uint32_t gi =3D (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBIL= ITY); + uint32_t gi =3D (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIB= ILITY); gi |=3D VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); =20 } @@ -229,8 +229,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUStat= e *cpu) { =20 uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); } =20 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 9c3da03c94..444d6aaaec 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -372,19 +372,19 @@ type_init(hvf_type_init); =20 static void hvf_vcpu_destroy(CPUState *cpu) { - hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf->fd); + hv_return_t ret =3D hv_vcpu_destroy(cpu->accel->fd); assert_hvf_ok(ret); =20 hvf_arch_vcpu_destroy(cpu); - g_free(cpu->hvf); - cpu->hvf =3D NULL; + g_free(cpu->accel); + cpu->accel =3D NULL; } =20 static int hvf_init_vcpu(CPUState *cpu) { int r; =20 - cpu->hvf =3D g_malloc0(sizeof(*cpu->hvf)); + cpu->accel =3D g_new0(AccelCPUState, 1); =20 /* init cpu signals */ struct sigaction sigact; @@ -393,18 +393,18 @@ static int hvf_init_vcpu(CPUState *cpu) sigact.sa_handler =3D dummy_signal; sigaction(SIG_IPI, &sigact, NULL); =20 - pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); - sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); + pthread_sigmask(SIG_BLOCK, NULL, &cpu->accel->unblock_ipi_mask); + sigdelset(&cpu->accel->unblock_ipi_mask, SIG_IPI); =20 #ifdef __aarch64__ - r =3D hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit= , NULL); + r =3D hv_vcpu_create(&cpu->accel->fd, (hv_vcpu_exit_t **)&cpu->accel->= exit, NULL); #else - r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); + r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->accel->fd, HV_VCPU_DEFAULT); #endif cpu->vcpu_dirty =3D 1; assert_hvf_ok(r); =20 - cpu->hvf->guest_debug_enabled =3D false; + cpu->accel->guest_debug_enabled =3D false; =20 return hvf_arch_init_vcpu(cpu); } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8f72624586..8fce64bbf6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -544,29 +544,29 @@ int hvf_get_registers(CPUState *cpu) int i; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); *(uint64_t *)((void *)env + hvf_reg_match[i].offset) =3D val; assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { - ret =3D hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, &fpval); memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpv= al)); assert_hvf_ok(ret); } =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); assert_hvf_ok(ret); vfp_set_fpcr(env, val); =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); assert_hvf_ok(ret); vfp_set_fpsr(env, val); =20 - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); assert_hvf_ok(ret); pstate_write(env, val); =20 @@ -575,7 +575,7 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { case HV_SYS_REG_DBGBVR0_EL1: @@ -661,7 +661,7 @@ int hvf_get_registers(CPUState *cpu) } } =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &= val); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= &val); assert_hvf_ok(ret); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -684,24 +684,24 @@ int hvf_put_registers(CPUState *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpv= al)); - ret =3D hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, fpval); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); assert_hvf_ok(ret); =20 aarch64_save_sp(env, arm_current_el(env)); @@ -712,7 +712,7 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { case HV_SYS_REG_DBGBVR0_EL1: @@ -789,11 +789,11 @@ int hvf_put_registers(CPUState *cpu) } =20 val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, v= al); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= val); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offs= et); + ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 return 0; @@ -814,7 +814,7 @@ static void hvf_set_reg(CPUState *cpu, int rt, uint64_t= val) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); assert_hvf_ok(r); } } @@ -827,7 +827,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); assert_hvf_ok(r); } =20 @@ -969,22 +969,22 @@ int hvf_arch_init_vcpu(CPUState *cpu) assert(write_cpustate_to_list(arm_cpu, false)); =20 /* Set CP_NO_RAW system registers on init */ - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, arm_cpu->midr); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, arm_cpu->mp_affinity); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = &pfr); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , &pfr); assert_hvf_ok(ret); pfr |=3D env->gicv3state ? (1 << 24) : 0; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = pfr); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , pfr); assert_hvf_ok(ret); =20 /* We're limited to underlying hardware caps, override internal versio= ns */ - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, &arm_cpu->isar.id_aa64mmfr0); assert_hvf_ok(ret); =20 @@ -994,7 +994,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_kick_vcpu_thread(CPUState *cpu) { cpus_kick_thread(cpu); - hv_vcpus_exit(&cpu->hvf->fd, 1); + hv_vcpus_exit(&cpu->accel->fd, 1); } =20 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, @@ -1678,13 +1678,13 @@ static int hvf_inject_interrupts(CPUState *cpu) { if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { trace_hvf_inject_fiq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FI= Q, true); } =20 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { trace_hvf_inject_irq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IR= Q, true); } =20 @@ -1718,7 +1718,7 @@ static void hvf_wait_for_ipi(CPUState *cpu, struct ti= mespec *ts) */ qatomic_set_mb(&cpu->thread_kicked, false); qemu_mutex_unlock_iothread(); - pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); + pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); qemu_mutex_lock_iothread(); } =20 @@ -1739,7 +1739,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 if (!(ctl & 1) || (ctl & 2)) { @@ -1748,7 +1748,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cva= l); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &c= val); assert_hvf_ok(r); =20 ticks_to_sleep =3D cval - hvf_vtimer_val(); @@ -1781,12 +1781,12 @@ static void hvf_sync_vtimer(CPUState *cpu) uint64_t ctl; bool irq_state; =20 - if (!cpu->hvf->vtimer_masked) { + if (!cpu->accel->vtimer_masked) { /* We will get notified on vtimer changes by hvf, nothing to do */ return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 irq_state =3D (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS= )) =3D=3D @@ -1795,8 +1795,8 @@ static void hvf_sync_vtimer(CPUState *cpu) =20 if (!irq_state) { /* Timer no longer asserting, we can unmask it */ - hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); - cpu->hvf->vtimer_masked =3D false; + hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); + cpu->accel->vtimer_masked =3D false; } } =20 @@ -1805,7 +1805,7 @@ int hvf_vcpu_exec(CPUState *cpu) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; int ret; - hv_vcpu_exit_t *hvf_exit =3D cpu->hvf->exit; + hv_vcpu_exit_t *hvf_exit =3D cpu->accel->exit; hv_return_t r; bool advance_pc =3D false; =20 @@ -1821,7 +1821,7 @@ int hvf_vcpu_exec(CPUState *cpu) flush_cpu_state(cpu); =20 qemu_mutex_unlock_iothread(); - assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); + assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); =20 /* handle VMEXIT */ uint64_t exit_reason =3D hvf_exit->reason; @@ -1836,7 +1836,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; case HV_EXIT_REASON_VTIMER_ACTIVATED: qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); - cpu->hvf->vtimer_masked =3D true; + cpu->accel->vtimer_masked =3D true; return 0; case HV_EXIT_REASON_CANCELED: /* we got kicked, no exit to process */ @@ -1990,10 +1990,10 @@ int hvf_vcpu_exec(CPUState *cpu) =20 flush_cpu_state(cpu); =20 - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); assert_hvf_ok(r); pc +=3D 4; - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); assert_hvf_ok(r); =20 /* Handle single-stepping over instructions which trigger a VM exi= t */ @@ -2113,29 +2113,29 @@ static void hvf_put_gdbstub_debug_registers(CPUStat= e *cpu) =20 for (i =3D 0; i < cur_hw_bps; i++) { HWBreakpoint *bp =3D get_hw_bp(i); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], bp->bcr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], bp->bvr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); assert_hvf_ok(r); } for (i =3D cur_hw_bps; i < max_hw_bps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); assert_hvf_ok(r); } =20 for (i =3D 0; i < cur_hw_wps; i++) { HWWatchpoint *wp =3D get_hw_wp(i); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], wp->wcr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], wp->wvr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); assert_hvf_ok(r); } for (i =3D cur_hw_wps; i < max_hw_wps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); assert_hvf_ok(r); } } @@ -2152,19 +2152,19 @@ static void hvf_put_guest_debug_registers(CPUState = *cpu) int i; =20 for (i =3D 0; i < max_hw_bps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], env->cp15.dbgbcr[i]); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], env->cp15.dbgbvr[i]); assert_hvf_ok(r); } =20 for (i =3D 0; i < max_hw_wps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], env->cp15.dbgwcr[i]); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], env->cp15.dbgwvr[i]); assert_hvf_ok(r); } @@ -2184,16 +2184,16 @@ static void hvf_arch_set_traps(void) /* Check whether guest debugging is enabled for at least one vCPU; if = it * is, enable exiting the guest on all vCPUs */ CPU_FOREACH(cpu) { - should_enable_traps |=3D cpu->hvf->guest_debug_enabled; + should_enable_traps |=3D cpu->accel->guest_debug_enabled; } CPU_FOREACH(cpu) { /* Set whether debug exceptions exit the guest */ - r =3D hv_vcpu_set_trap_debug_exceptions(cpu->hvf->fd, + r =3D hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, should_enable_traps); assert_hvf_ok(r); =20 /* Set whether accesses to debug registers exit the guest */ - r =3D hv_vcpu_set_trap_debug_reg_accesses(cpu->hvf->fd, + r =3D hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, should_enable_traps); assert_hvf_ok(r); } @@ -2205,12 +2205,12 @@ void hvf_arch_update_guest_debug(CPUState *cpu) CPUARMState *env =3D &arm_cpu->env; =20 /* Check whether guest debugging is enabled */ - cpu->hvf->guest_debug_enabled =3D cpu->singlestep_enabled || + cpu->accel->guest_debug_enabled =3D cpu->singlestep_enabled || hvf_sw_breakpoints_active(cpu) || hvf_arm_hw_debug_active(cpu); =20 /* Update debug registers */ - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { hvf_put_gdbstub_debug_registers(cpu); } else { hvf_put_guest_debug_registers(cpu); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index f6775c942a..06ea5033c2 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -81,11 +81,11 @@ void vmx_update_tpr(CPUState *cpu) int tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state) << 4; int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 - wreg(cpu->hvf->fd, HV_X86_TPR, tpr); + wreg(cpu->accel->fd, HV_X86_TPR, tpr); if (irr =3D=3D -1) { - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); } else { - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4); } } @@ -93,7 +93,7 @@ void vmx_update_tpr(CPUState *cpu) static void update_apic_tpr(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); - int tpr =3D rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; + int tpr =3D rreg(cpu->accel->fd, HV_X86_TPR) >> 4; cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } =20 @@ -256,12 +256,12 @@ int hvf_arch_init_vcpu(CPUState *cpu) } =20 /* set VMCS control fields */ - wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, VMCS_PIN_BASED_CTLS_EXTINT | VMCS_PIN_BASED_CTLS_NMI | VMCS_PIN_BASED_CTLS_VNMI)); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, VMCS_PRI_PROC_BASED_CTLS_HLT | VMCS_PRI_PROC_BASED_CTLS_MWAIT | @@ -276,14 +276,14 @@ int hvf_arch_init_vcpu(CPUState *cpu) reqCap |=3D VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; } =20 - wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); =20 - wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx= _cap_entry, + wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->v= mx_cap_entry, 0)); - wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ + wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ =20 - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); =20 x86cpu =3D X86_CPU(cpu); x86cpu->env.xsave_buf_len =3D 4096; @@ -295,18 +295,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) */ assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <=3D x86cpu->env.xsave_b= uf_len); =20 - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1); =20 return 0; } @@ -347,16 +347,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t = ins_len, uint64_t idtvec_in } if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { env->has_error_code =3D true; - env->error_code =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERR= OR); + env->error_code =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_E= RROR); } } - if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & + if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { env->hflags2 |=3D HF2_NMI_MASK; } else { env->hflags2 &=3D ~HF2_NMI_MASK; } - if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & + if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags |=3D HF_INHIBIT_IRQ_MASK; @@ -435,20 +435,20 @@ int hvf_vcpu_exec(CPUState *cpu) return EXCP_HLT; } =20 - hv_return_t r =3D hv_vcpu_run(cpu->hvf->fd); + hv_return_t r =3D hv_vcpu_run(cpu->accel->fd); assert_hvf_ok(r); =20 /* handle VMEXIT */ - uint64_t exit_reason =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); - uint64_t exit_qual =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION= ); - uint32_t ins_len =3D (uint32_t)rvmcs(cpu->hvf->fd, + uint64_t exit_reason =3D rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); + uint64_t exit_qual =3D rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATI= ON); + uint32_t ins_len =3D (uint32_t)rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH); =20 - uint64_t idtvec_info =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_IN= FO); + uint64_t idtvec_info =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_= INFO); =20 hvf_store_events(cpu, ins_len, idtvec_info); - rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + rip =3D rreg(cpu->accel->fd, HV_X86_RIP); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); =20 qemu_mutex_lock_iothread(); =20 @@ -478,7 +478,7 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_EPT_FAULT: { hvf_slot *slot; - uint64_t gpa =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRE= SS); + uint64_t gpa =3D rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADD= RESS); =20 if (((idtvec_info & VMCS_IDT_VEC_VALID) =3D=3D 0) && ((exit_qual & EXIT_QUAL_NMIUDTI) !=3D 0)) { @@ -523,7 +523,7 @@ int hvf_vcpu_exec(CPUState *cpu) store_regs(cpu); break; } else if (!string && !in) { - RAX(env) =3D rreg(cpu->hvf->fd, HV_X86_RAX); + RAX(env) =3D rreg(cpu->accel->fd, HV_X86_RAX); hvf_handle_io(env, port, &RAX(env), 1, size, 1); macvm_set_rip(cpu, rip + ins_len); break; @@ -539,21 +539,21 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_CPUID: { - uint32_t rax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); - uint32_t rbx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); - uint32_t rcx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); - uint32_t rdx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); + uint32_t rax =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); + uint32_t rbx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX); + uint32_t rcx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); + uint32_t rdx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); =20 if (rax =3D=3D 1) { /* CPUID1.ecx.OSXSAVE needs to know CR4 */ - env->cr[4] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); + env->cr[4] =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); } hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); =20 - wreg(cpu->hvf->fd, HV_X86_RAX, rax); - wreg(cpu->hvf->fd, HV_X86_RBX, rbx); - wreg(cpu->hvf->fd, HV_X86_RCX, rcx); - wreg(cpu->hvf->fd, HV_X86_RDX, rdx); + wreg(cpu->accel->fd, HV_X86_RAX, rax); + wreg(cpu->accel->fd, HV_X86_RBX, rbx); + wreg(cpu->accel->fd, HV_X86_RCX, rcx); + wreg(cpu->accel->fd, HV_X86_RDX, rdx); =20 macvm_set_rip(cpu, rip + ins_len); break; @@ -561,16 +561,16 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_XSETBV: { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; - uint32_t eax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); - uint32_t ecx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); - uint32_t edx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); + uint32_t eax =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); + uint32_t ecx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); + uint32_t edx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); =20 if (ecx) { macvm_set_rip(cpu, rip + ins_len); break; } env->xcr0 =3D ((uint64_t)edx << 32) | eax; - wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); + wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1); macvm_set_rip(cpu, rip + ins_len); break; } @@ -609,11 +609,11 @@ int hvf_vcpu_exec(CPUState *cpu) =20 switch (cr) { case 0x0: { - macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); + macvm_set_cr0(cpu->accel->fd, RRX(env, reg)); break; } case 4: { - macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); + macvm_set_cr4(cpu->accel->fd, RRX(env, reg)); break; } case 8: { @@ -649,7 +649,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_TASK_SWITCH: { - uint64_t vinfo =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO= ); + uint64_t vinfo =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_IN= FO); x68_segment_selector sel =3D {.sel =3D exit_qual & 0xffff}; vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, = vinfo @@ -662,8 +662,8 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_RDPMC: - wreg(cpu->hvf->fd, HV_X86_RAX, 0); - wreg(cpu->hvf->fd, HV_X86_RDX, 0); + wreg(cpu->accel->fd, HV_X86_RAX, 0); + wreg(cpu->accel->fd, HV_X86_RDX, 0); macvm_set_rip(cpu, rip + ins_len); break; case VMX_REASON_VMCALL: diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index d086584f26..8ceea6398e 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -61,11 +61,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, } =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -84,11 +84,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, uint32_t limit; =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -102,8 +102,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_de= sc, int gate) { - target_ulong base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); - uint32_t limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + target_ulong base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); + uint32_t limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); =20 memset(idt_desc, 0, sizeof(*idt_desc)); if (gate * 8 >=3D limit) { @@ -117,7 +117,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x8= 6_call_gate *idt_desc, =20 bool x86_is_protected(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE_MASK; } =20 @@ -135,7 +135,7 @@ bool x86_is_v8086(struct CPUState *cpu) =20 bool x86_is_long_mode(struct CPUState *cpu) { - return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; + return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } =20 bool x86_is_long64_mode(struct CPUState *cpu) @@ -148,13 +148,13 @@ bool x86_is_long64_mode(struct CPUState *cpu) =20 bool x86_is_paging_mode(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG_MASK; } =20 bool x86_is_pae_enabled(struct CPUState *cpu) { - uint64_t cr4 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); + uint64_t cr4 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE_MASK; } =20 diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index a484942cfc..c2d2e9ee84 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -47,47 +47,47 @@ static const struct vmx_segment_field { =20 uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); + return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); } =20 uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); + return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_byte= s); } =20 uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) { - return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); + return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); } =20 x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) { x68_segment_selector sel; - sel.sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); + sel.sel =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); return sel; } =20 void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector= selector, X86Seg seg) { - wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel); + wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); } =20 void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment = *desc, X86Seg seg) { - desc->sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); - desc->base =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); - desc->limit =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); - desc->ar =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); + desc->sel =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); + desc->base =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); + desc->limit =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); + desc->ar =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); } =20 void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,= X86Seg seg) { const struct vmx_segment_field *sf =3D &vmx_segment_fields[seg]; =20 - wvmcs(cpu->hvf->fd, sf->base, desc->base); - wvmcs(cpu->hvf->fd, sf->limit, desc->limit); - wvmcs(cpu->hvf->fd, sf->selector, desc->sel); - wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar); + wvmcs(cpu->accel->fd, sf->base, desc->base); + wvmcs(cpu->accel->fd, sf->limit, desc->limit); + wvmcs(cpu->accel->fd, sf->selector, desc->sel); + wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); } =20 void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selec= tor selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_= desc) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index f5704f63e8..ccda568478 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -673,7 +673,7 @@ void simulate_rdmsr(struct CPUState *cpu) =20 switch (msr) { case MSR_IA32_TSC: - val =3D rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); + val =3D rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(X86_CPU(cpu)->apic_state); @@ -682,16 +682,16 @@ void simulate_rdmsr(struct CPUState *cpu) val =3D x86_cpu->ucode_rev; break; case MSR_EFER: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -779,13 +779,13 @@ void simulate_wrmsr(struct CPUState *cpu) cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -798,9 +798,9 @@ void simulate_wrmsr(struct CPUState *cpu) break; case MSR_EFER: /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_invalidate_tlb(cpu->accel->fd); } break; case MSR_MTRRphysBase(0): @@ -1424,21 +1424,21 @@ void load_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - RRX(env, R_EAX) =3D rreg(cpu->hvf->fd, HV_X86_RAX); - RRX(env, R_EBX) =3D rreg(cpu->hvf->fd, HV_X86_RBX); - RRX(env, R_ECX) =3D rreg(cpu->hvf->fd, HV_X86_RCX); - RRX(env, R_EDX) =3D rreg(cpu->hvf->fd, HV_X86_RDX); - RRX(env, R_ESI) =3D rreg(cpu->hvf->fd, HV_X86_RSI); - RRX(env, R_EDI) =3D rreg(cpu->hvf->fd, HV_X86_RDI); - RRX(env, R_ESP) =3D rreg(cpu->hvf->fd, HV_X86_RSP); - RRX(env, R_EBP) =3D rreg(cpu->hvf->fd, HV_X86_RBP); + RRX(env, R_EAX) =3D rreg(cpu->accel->fd, HV_X86_RAX); + RRX(env, R_EBX) =3D rreg(cpu->accel->fd, HV_X86_RBX); + RRX(env, R_ECX) =3D rreg(cpu->accel->fd, HV_X86_RCX); + RRX(env, R_EDX) =3D rreg(cpu->accel->fd, HV_X86_RDX); + RRX(env, R_ESI) =3D rreg(cpu->accel->fd, HV_X86_RSI); + RRX(env, R_EDI) =3D rreg(cpu->accel->fd, HV_X86_RDI); + RRX(env, R_ESP) =3D rreg(cpu->accel->fd, HV_X86_RSP); + RRX(env, R_EBP) =3D rreg(cpu->accel->fd, HV_X86_RBP); for (i =3D 8; i < 16; i++) { - RRX(env, i) =3D rreg(cpu->hvf->fd, HV_X86_RAX + i); + RRX(env, i) =3D rreg(cpu->accel->fd, HV_X86_RAX + i); } =20 - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + env->eip =3D rreg(cpu->accel->fd, HV_X86_RIP); } =20 void store_regs(struct CPUState *cpu) @@ -1447,20 +1447,20 @@ void store_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env)); - wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env)); - wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env)); - wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env)); - wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env)); - wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env)); - wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env)); - wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env)); + wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); + wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); + wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); + wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); + wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); + wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); + wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); + wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); for (i =3D 8; i < 16; i++) { - wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i)); + wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i)); } =20 lflags_to_rflags(env); - wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags); macvm_set_rip(cpu, env->eip); } =20 diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 96d117567e..8cd08622a1 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -126,7 +126,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct = gpt_translation *pt, pt->err_code |=3D MMU_PAGE_PT; } =20 - uint32_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint32_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); /* check protection */ if (cr0 & CR0_WP_MASK) { if (pt->write_access && !pte_write_access(pte)) { @@ -171,7 +171,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong= addr, int err_code, { int top_level, level; bool is_large =3D false; - target_ulong cr3 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); + target_ulong cr3 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR3); uint64_t page_mask =3D pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; =20 memset(pt, 0, sizeof(*pt)); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index beaeec0687..f09bfbdda5 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -61,7 +61,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x= 86_tss_segment32 *tss) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3); + wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); =20 env->eip =3D tss->eip; env->eflags =3D tss->eflags | 2; @@ -110,11 +110,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_= selector tss_sel, x68_segme =20 void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, i= nt reason, bool gate_valid, uint8_t gate, uint64_t gate_type) { - uint64_t rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + uint64_t rip =3D rreg(cpu->accel->fd, HV_X86_RIP); if (!gate_valid || (gate_type !=3D VMCS_INTR_T_HWEXCEPTION && gate_type !=3D VMCS_INTR_T_HWINTR && gate_type !=3D VMCS_INTR_T_NMI)) { - int ins_len =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); + int ins_len =3D rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH= ); macvm_set_rip(cpu, rip + ins_len); return; } @@ -173,12 +173,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segmen= t_selector tss_sel, int rea //ret =3D task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, = &next_tss_desc); VM_PANIC("task_switch_16"); =20 - macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | + macvm_set_cr0(cpu->accel->fd, rvmcs(cpu->accel->fd, VMCS_GUEST_CR0) | CR0_TS_MASK); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); =20 store_regs(cpu); =20 - hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_invalidate_tlb(cpu->accel->fd); } diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 92dfd26a01..3b1ef5f49a 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -77,7 +77,7 @@ void hvf_put_xsave(CPUState *cs) =20 x86_cpu_xsave_all_areas(X86_CPU(cs), xsave, xsave_len); =20 - if (hv_vcpu_write_fpstate(cs->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_write_fpstate(cs->accel->fd, xsave, xsave_len)) { abort(); } } @@ -87,19 +87,19 @@ static void hvf_put_segments(CPUState *cs) CPUX86State *env =3D &X86_CPU(cs)->env; struct vmx_segment seg; =20 - wvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); =20 - wvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); =20 - /* wvmcs(cs->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cs->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); + /* wvmcs(cs->accel->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]); vmx_update_tpr(cs); - wvmcs(cs->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); + wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cs->hvf->fd, env->cr[4]); - macvm_set_cr0(cs->hvf->fd, env->cr[0]); + macvm_set_cr4(cs->accel->fd, env->cr[4]); + macvm_set_cr0(cs->accel->fd, env->cr[0]); =20 hvf_set_segment(cs, &seg, &env->segs[R_CS], false); vmx_write_segment_descriptor(cs, &seg, R_CS); @@ -130,24 +130,24 @@ void hvf_put_msrs(CPUState *cs) { CPUX86State *env =3D &X86_CPU(cs)->env; =20 - hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cs->hvf->fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); =20 - hv_vcpu_write_msr(cs->hvf->fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cs->accel->fd, MSR_STAR, env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cs->hvf->fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cs->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); - hv_vcpu_write_msr(cs->hvf->fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cs->hvf->fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cs->accel->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cs->accel->fd, MSR_KERNELGSBASE, env->kernelgsbase); + hv_vcpu_write_msr(cs->accel->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cs->accel->fd, MSR_LSTAR, env->lstar); #endif =20 - hv_vcpu_write_msr(cs->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); - hv_vcpu_write_msr(cs->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); + hv_vcpu_write_msr(cs->accel->fd, MSR_GSBASE, env->segs[R_GS].base); + hv_vcpu_write_msr(cs->accel->fd, MSR_FSBASE, env->segs[R_FS].base); } =20 =20 @@ -156,7 +156,7 @@ void hvf_get_xsave(CPUState *cs) void *xsave =3D X86_CPU(cs)->env.xsave_buf; uint32_t xsave_len =3D X86_CPU(cs)->env.xsave_buf_len; =20 - if (hv_vcpu_read_fpstate(cs->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_read_fpstate(cs->accel->fd, xsave, xsave_len)) { abort(); } =20 @@ -195,17 +195,17 @@ static void hvf_get_segments(CPUState *cs) vmx_read_segment_descriptor(cs, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); =20 - env->idt.limit =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit =3D rvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base =3D rvmcs(cs->hvf->fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit =3D rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base =3D rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit =3D rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base =3D rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE); =20 - env->cr[0] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR0); + env->cr[0] =3D rvmcs(cs->accel->fd, VMCS_GUEST_CR0); env->cr[2] =3D 0; - env->cr[3] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR3); - env->cr[4] =3D rvmcs(cs->hvf->fd, VMCS_GUEST_CR4); + env->cr[3] =3D rvmcs(cs->accel->fd, VMCS_GUEST_CR3); + env->cr[4] =3D rvmcs(cs->accel->fd, VMCS_GUEST_CR4); =20 - env->efer =3D rvmcs(cs->hvf->fd, VMCS_GUEST_IA32_EFER); + env->efer =3D rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); } =20 void hvf_get_msrs(CPUState *cs) @@ -213,27 +213,27 @@ void hvf_get_msrs(CPUState *cs) CPUX86State *env =3D &X86_CPU(cs)->env; uint64_t tmp; =20 - hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs =3D tmp; =20 - hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp =3D tmp; =20 - hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip =3D tmp; =20 - hv_vcpu_read_msr(cs->hvf->fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cs->accel->fd, MSR_STAR, &env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cs->hvf->fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cs->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); - hv_vcpu_read_msr(cs->hvf->fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cs->hvf->fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cs->accel->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cs->accel->fd, MSR_KERNELGSBASE, &env->kernelgsbase); + hv_vcpu_read_msr(cs->accel->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cs->accel->fd, MSR_LSTAR, &env->lstar); #endif =20 - hv_vcpu_read_msr(cs->hvf->fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_APICBASE, &tmp); =20 - env->tsc =3D rdtscp() + rvmcs(cs->hvf->fd, VMCS_TSC_OFFSET); + env->tsc =3D rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); } =20 int hvf_put_registers(CPUState *cs) @@ -241,26 +241,26 @@ int hvf_put_registers(CPUState *cs) X86CPU *x86cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86cpu->env; =20 - wreg(cs->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cs->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cs->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cs->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cs->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cs->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cs->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cs->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cs->hvf->fd, HV_X86_R8, env->regs[8]); - wreg(cs->hvf->fd, HV_X86_R9, env->regs[9]); - wreg(cs->hvf->fd, HV_X86_R10, env->regs[10]); - wreg(cs->hvf->fd, HV_X86_R11, env->regs[11]); - wreg(cs->hvf->fd, HV_X86_R12, env->regs[12]); - wreg(cs->hvf->fd, HV_X86_R13, env->regs[13]); - wreg(cs->hvf->fd, HV_X86_R14, env->regs[14]); - wreg(cs->hvf->fd, HV_X86_R15, env->regs[15]); - wreg(cs->hvf->fd, HV_X86_RFLAGS, env->eflags); - wreg(cs->hvf->fd, HV_X86_RIP, env->eip); + wreg(cs->accel->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cs->accel->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cs->accel->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cs->accel->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cs->accel->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cs->accel->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cs->accel->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cs->accel->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cs->accel->fd, HV_X86_R8, env->regs[8]); + wreg(cs->accel->fd, HV_X86_R9, env->regs[9]); + wreg(cs->accel->fd, HV_X86_R10, env->regs[10]); + wreg(cs->accel->fd, HV_X86_R11, env->regs[11]); + wreg(cs->accel->fd, HV_X86_R12, env->regs[12]); + wreg(cs->accel->fd, HV_X86_R13, env->regs[13]); + wreg(cs->accel->fd, HV_X86_R14, env->regs[14]); + wreg(cs->accel->fd, HV_X86_R15, env->regs[15]); + wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags); + wreg(cs->accel->fd, HV_X86_RIP, env->eip); =20 - wreg(cs->hvf->fd, HV_X86_XCR0, env->xcr0); + wreg(cs->accel->fd, HV_X86_XCR0, env->xcr0); =20 hvf_put_xsave(cs); =20 @@ -268,14 +268,14 @@ int hvf_put_registers(CPUState *cs) =20 hvf_put_msrs(cs); =20 - wreg(cs->hvf->fd, HV_X86_DR0, env->dr[0]); - wreg(cs->hvf->fd, HV_X86_DR1, env->dr[1]); - wreg(cs->hvf->fd, HV_X86_DR2, env->dr[2]); - wreg(cs->hvf->fd, HV_X86_DR3, env->dr[3]); - wreg(cs->hvf->fd, HV_X86_DR4, env->dr[4]); - wreg(cs->hvf->fd, HV_X86_DR5, env->dr[5]); - wreg(cs->hvf->fd, HV_X86_DR6, env->dr[6]); - wreg(cs->hvf->fd, HV_X86_DR7, env->dr[7]); + wreg(cs->accel->fd, HV_X86_DR0, env->dr[0]); + wreg(cs->accel->fd, HV_X86_DR1, env->dr[1]); + wreg(cs->accel->fd, HV_X86_DR2, env->dr[2]); + wreg(cs->accel->fd, HV_X86_DR3, env->dr[3]); + wreg(cs->accel->fd, HV_X86_DR4, env->dr[4]); + wreg(cs->accel->fd, HV_X86_DR5, env->dr[5]); + wreg(cs->accel->fd, HV_X86_DR6, env->dr[6]); + wreg(cs->accel->fd, HV_X86_DR7, env->dr[7]); =20 return 0; } @@ -285,40 +285,40 @@ int hvf_get_registers(CPUState *cs) X86CPU *x86cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86cpu->env; =20 - env->regs[R_EAX] =3D rreg(cs->hvf->fd, HV_X86_RAX); - env->regs[R_EBX] =3D rreg(cs->hvf->fd, HV_X86_RBX); - env->regs[R_ECX] =3D rreg(cs->hvf->fd, HV_X86_RCX); - env->regs[R_EDX] =3D rreg(cs->hvf->fd, HV_X86_RDX); - env->regs[R_EBP] =3D rreg(cs->hvf->fd, HV_X86_RBP); - env->regs[R_ESP] =3D rreg(cs->hvf->fd, HV_X86_RSP); - env->regs[R_ESI] =3D rreg(cs->hvf->fd, HV_X86_RSI); - env->regs[R_EDI] =3D rreg(cs->hvf->fd, HV_X86_RDI); - env->regs[8] =3D rreg(cs->hvf->fd, HV_X86_R8); - env->regs[9] =3D rreg(cs->hvf->fd, HV_X86_R9); - env->regs[10] =3D rreg(cs->hvf->fd, HV_X86_R10); - env->regs[11] =3D rreg(cs->hvf->fd, HV_X86_R11); - env->regs[12] =3D rreg(cs->hvf->fd, HV_X86_R12); - env->regs[13] =3D rreg(cs->hvf->fd, HV_X86_R13); - env->regs[14] =3D rreg(cs->hvf->fd, HV_X86_R14); - env->regs[15] =3D rreg(cs->hvf->fd, HV_X86_R15); + env->regs[R_EAX] =3D rreg(cs->accel->fd, HV_X86_RAX); + env->regs[R_EBX] =3D rreg(cs->accel->fd, HV_X86_RBX); + env->regs[R_ECX] =3D rreg(cs->accel->fd, HV_X86_RCX); + env->regs[R_EDX] =3D rreg(cs->accel->fd, HV_X86_RDX); + env->regs[R_EBP] =3D rreg(cs->accel->fd, HV_X86_RBP); + env->regs[R_ESP] =3D rreg(cs->accel->fd, HV_X86_RSP); + env->regs[R_ESI] =3D rreg(cs->accel->fd, HV_X86_RSI); + env->regs[R_EDI] =3D rreg(cs->accel->fd, HV_X86_RDI); + env->regs[8] =3D rreg(cs->accel->fd, HV_X86_R8); + env->regs[9] =3D rreg(cs->accel->fd, HV_X86_R9); + env->regs[10] =3D rreg(cs->accel->fd, HV_X86_R10); + env->regs[11] =3D rreg(cs->accel->fd, HV_X86_R11); + env->regs[12] =3D rreg(cs->accel->fd, HV_X86_R12); + env->regs[13] =3D rreg(cs->accel->fd, HV_X86_R13); + env->regs[14] =3D rreg(cs->accel->fd, HV_X86_R14); + env->regs[15] =3D rreg(cs->accel->fd, HV_X86_R15); =20 - env->eflags =3D rreg(cs->hvf->fd, HV_X86_RFLAGS); - env->eip =3D rreg(cs->hvf->fd, HV_X86_RIP); + env->eflags =3D rreg(cs->accel->fd, HV_X86_RFLAGS); + env->eip =3D rreg(cs->accel->fd, HV_X86_RIP); =20 hvf_get_xsave(cs); - env->xcr0 =3D rreg(cs->hvf->fd, HV_X86_XCR0); + env->xcr0 =3D rreg(cs->accel->fd, HV_X86_XCR0); =20 hvf_get_segments(cs); hvf_get_msrs(cs); =20 - env->dr[0] =3D rreg(cs->hvf->fd, HV_X86_DR0); - env->dr[1] =3D rreg(cs->hvf->fd, HV_X86_DR1); - env->dr[2] =3D rreg(cs->hvf->fd, HV_X86_DR2); - env->dr[3] =3D rreg(cs->hvf->fd, HV_X86_DR3); - env->dr[4] =3D rreg(cs->hvf->fd, HV_X86_DR4); - env->dr[5] =3D rreg(cs->hvf->fd, HV_X86_DR5); - env->dr[6] =3D rreg(cs->hvf->fd, HV_X86_DR6); - env->dr[7] =3D rreg(cs->hvf->fd, HV_X86_DR7); + env->dr[0] =3D rreg(cs->accel->fd, HV_X86_DR0); + env->dr[1] =3D rreg(cs->accel->fd, HV_X86_DR1); + env->dr[2] =3D rreg(cs->accel->fd, HV_X86_DR2); + env->dr[3] =3D rreg(cs->accel->fd, HV_X86_DR3); + env->dr[4] =3D rreg(cs->accel->fd, HV_X86_DR4); + env->dr[5] =3D rreg(cs->accel->fd, HV_X86_DR5); + env->dr[6] =3D rreg(cs->accel->fd, HV_X86_DR6); + env->dr[7] =3D rreg(cs->accel->fd, HV_X86_DR7); =20 x86_update_hflags(env); return 0; @@ -327,16 +327,16 @@ int hvf_get_registers(CPUState *cs) static void vmx_set_int_window_exiting(CPUState *cs) { uint64_t val; - val =3D rvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 void vmx_clear_int_window_exiting(CPUState *cs) { uint64_t val; - val =3D rvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cs->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 @@ -372,7 +372,7 @@ bool hvf_inject_interrupts(CPUState *cs) uint64_t info =3D 0; if (have_event) { info =3D vector | intr_type | VMCS_INTR_VALID; - uint64_t reason =3D rvmcs(cs->hvf->fd, VMCS_EXIT_REASON); + uint64_t reason =3D rvmcs(cs->accel->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { vmx_clear_nmi_blocking(cs); } @@ -381,17 +381,17 @@ bool hvf_inject_interrupts(CPUState *cs) info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cs->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); + wvmcs(cs->accel->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); } =20 if (env->has_error_code) { - wvmcs(cs->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cs->accel->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |=3D VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info); }; } =20 @@ -399,7 +399,7 @@ bool hvf_inject_interrupts(CPUState *cs) if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info); } else { vmx_set_nmi_window_exiting(cs); } @@ -411,7 +411,7 @@ bool hvf_inject_interrupts(CPUState *cs) int line =3D cpu_get_pic_interrupt(&x86cpu->env); cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { - wvmcs(cs->hvf->fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } @@ -429,7 +429,7 @@ int hvf_process_events(CPUState *cs) =20 if (!cs->vcpu_dirty) { /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ - env->eflags =3D rreg(cs->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cs->accel->fd, HV_X86_RFLAGS); } =20 if (cs->interrupt_request & CPU_INTERRUPT_INIT) { --=20 2.38.1