[v1] RISC-V: Convert the CSR access functions to use

[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use

Alistair Francis posted 5 patches 4 years, 8 months ago

Diff against v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1616002766.git.alistair.francis@wdc.com

Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>

There is a newer version of this series

target/riscv/cpu.h        |  28 +-
target/riscv/cpu_bits.h   |  44 +--
target/riscv/cpu.c        |   2 +-
target/riscv/cpu_helper.c |   4 +-
target/riscv/csr.c        | 753 ++++++++++++++++++++++----------------
target/riscv/gdbstub.c    |   8 +-
target/riscv/op_helper.c  |  18 +-
7 files changed, 499 insertions(+), 358 deletions(-)

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[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use

Posted by Alistair Francis 4 years, 8 months ago

Alistair Francis (5):
  target/riscv: Convert the RISC-V exceptions to an enum
  target/riscv: Use the RiscVException enum for CSR predicates
  target/riscv: Fix 32-bit HS mode access permissions
  target/riscv: Use the RiscVException enum for CSR operations
  target/riscv: Use RiscVException enum for CSR access

 target/riscv/cpu.h        |  28 +-
 target/riscv/cpu_bits.h   |  44 +--
 target/riscv/cpu.c        |   2 +-
 target/riscv/cpu_helper.c |   4 +-
 target/riscv/csr.c        | 753 ++++++++++++++++++++++----------------
 target/riscv/gdbstub.c    |   8 +-
 target/riscv/op_helper.c  |  18 +-
 7 files changed, 499 insertions(+), 358 deletions(-)

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2.30.1