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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 44 ++++++++++++++++++++------------------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..8ae404c32a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -527,27 +527,29 @@ #define DEFAULT_RSTVEC 0x1000 =20 /* Exception causes */ -#define EXCP_NONE -1 /* sentinel value */ -#define RISCV_EXCP_INST_ADDR_MIS 0x0 -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 -#define RISCV_EXCP_ILLEGAL_INST 0x2 -#define RISCV_EXCP_BREAKPOINT 0x3 -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 -#define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_VS_ECALL 0xa -#define RISCV_EXCP_M_ECALL 0xb -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0= */ -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0= */ -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ -#define RISCV_EXCP_SEMIHOST 0x10 -#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 -#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 -#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 -#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 +typedef enum RiscVException { + RISCV_EXCP_NONE =3D -1, /* sentinel value */ + RISCV_EXCP_INST_ADDR_MIS =3D 0x0, + RISCV_EXCP_INST_ACCESS_FAULT =3D 0x1, + RISCV_EXCP_ILLEGAL_INST =3D 0x2, + RISCV_EXCP_BREAKPOINT =3D 0x3, + RISCV_EXCP_LOAD_ADDR_MIS =3D 0x4, + RISCV_EXCP_LOAD_ACCESS_FAULT =3D 0x5, + RISCV_EXCP_STORE_AMO_ADDR_MIS =3D 0x6, + RISCV_EXCP_STORE_AMO_ACCESS_FAULT =3D 0x7, + RISCV_EXCP_U_ECALL =3D 0x8, + RISCV_EXCP_S_ECALL =3D 0x9, + RISCV_EXCP_VS_ECALL =3D 0xa, + RISCV_EXCP_M_ECALL =3D 0xb, + RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ + RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ + RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SEMIHOST =3D 0x10, + RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, + RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15, + RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16, + RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT =3D 0x17, +} RiscVException; =20 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a990f6253..63584b4a20 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -357,7 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mcause =3D 0; env->pc =3D env->resetvec; #endif - cs->exception_index =3D EXCP_NONE; + cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 83a6bcfad0..af702f65b1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) if (irqs) { return ctz64(irqs); /* since non-zero */ } else { - return EXCP_NONE; /* indicates no pending interrupt */ + return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } #endif @@ -1017,5 +1017,5 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ =20 #endif - cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ + cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */ } --=20 2.30.1 From nobody Wed Nov 19 12:13:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1616003334; cv=none; d=zohomail.com; s=zohoarc; b=UPfPsYaGJTzpRcAG6ERjyw/4i1QjJdA2+O+LP55maXTLsZ1lmiiAuSSPiJSaufo3N58l77WIoCf0eYOjfJOjB/UD9mnxfSy0USftvPKDQENoOSwXPv7Tm5xSfqdyWJuKdOgRTHKbj3MNSFy0M/mZCfko5j0Y5rsQyvpncloTf6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616003334; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BBB7utcdKbFmcNHoos2Hb8W5Bh7KT4nxRujZpV4TbK8=; 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IronPort-SDR: 2fW1tsaiXarUZL2gpzKj2JQIA53kq16qYK4GyxS7Oczmd7u+VScKsjWBCFspcY1lx2GrPzq1M3 137VGXhvFTcG4/1FhEevpcTIgc/X/BsOShOYKmfv98oqa7s9ID0Ra1I+jikfE69fEUpP99rrfK PMsBw+VQl10TX7xEEnjzNIEnuNaVH28MoIkT5P03vDqFuNyfFq0EqDb21HOdUmOdZOShQsTS6w y0CCgcN8mI3xkJIFXDfOLE/PWS9OtQ1RB5gtoKL/xW29/DYfDjRb1jUGDJiedHHBnf6SdmLVeG Eno= X-IronPort-AV: E=Sophos;i="5.81,257,1610380800"; d="scan'208";a="266778849" IronPort-SDR: X/ZRz6jIob9OnKfBDYWOkyF4iEYyJ0aEIR34k4Ev8lATTPdwbze/W/lMQVr5Za0r+WN2PtHelK 0PB94WDw9MvgW6Q1QWU8IAl7y9U2SQxoQaajhyKeFfTY59I2ZYJ/n/KTDCt0Z5bapTMQV7vpvt C+mloXJEwx/r/7Mi36B1HKAnIZ7EjhVEkjds9XdqJQpZQgsfmb1dFnOVffvh9U6Q4Gugq92uYn CXJc/qwXJp83mZQaMxizP/w0exUoVxD3bfsEXDej6b1N6WkrKS+kGWz4/uFC4KBVOmtUpHXMxk q7d96C5AGDmEI4r8Wjs4CEz6 IronPort-SDR: dyPSCbQrXbeGjhmjhGLqcOnyRzrb70+seRzF19vqTD3k2Pn+OukAIpybstuqot/VvB5k7UqKC2 9bfHm2wVD/SjBWSjlWobZs62tW1ZRgkfoDIv9t9gmvovHpBqTRKlhnSFS+JPjLQWXZMoQjtkHT t19ZGZZDUCZzknTCd7NqkPInRqafOar88TQMWQMQ6z4w2Rl5VFL6/eTqQGCGDosNW8Ep/eAFXB OuLniI1egCtPJjsNoxEeVPgYSTxFU+iyfXuu8EFYD4ptcgfGK4TmbSyHsQjSzyE2MQ7X4L2L7D YmM= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates Date: Wed, 17 Mar 2021 13:39:52 -0400 Message-Id: <9c0fa7d4f191d83ac2e70e830d141f4f4105e061.1616002766.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 80 +++++++++++++++++++++++++--------------------- 2 files changed, 46 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0edb2826a2..073a994d13 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -469,7 +469,8 @@ static inline target_ulong riscv_csr_read(CPURISCVState= *env, int csrno) return val; } =20 -typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); +typedef RiscVException (*riscv_csr_predicate_fn)(CPURISCVState *env, + int csrno); typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, target_ulong *ret_value); typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e6363f3..da9baff6fb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -35,29 +35,29 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops) } =20 /* Predicates */ -static int fs(CPURISCVState *env, int csrno) +static RiscVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ if ((csrno =3D=3D CSR_FCSR) && (env->misa & RVV)) { - return 0; + return RISCV_EXCP_INST_ACCESS_FAULT; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int vs(CPURISCVState *env, int csrno) +static RiscVException vs(CPURISCVState *env, int csrno) { if (env->misa & RVV) { - return 0; + return RISCV_EXCP_NONE; } - return -1; + return RISCV_EXCP_INST_ACCESS_FAULT; } =20 -static int ctr(CPURISCVState *env, int csrno) +static RiscVException ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); @@ -65,7 +65,7 @@ static int ctr(CPURISCVState *env, int csrno) =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_virt_enabled(env)) { @@ -73,25 +73,25 @@ static int ctr(CPURISCVState *env, int csrno) case CSR_CYCLE: if (!get_field(env->hcounteren, HCOUNTEREN_CY) && get_field(env->mcounteren, HCOUNTEREN_CY)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_TIME: if (!get_field(env->hcounteren, HCOUNTEREN_TM) && get_field(env->mcounteren, HCOUNTEREN_TM)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_INSTRET: if (!get_field(env->hcounteren, HCOUNTEREN_IR) && get_field(env->mcounteren, HCOUNTEREN_IR)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; } @@ -100,93 +100,101 @@ static int ctr(CPURISCVState *env, int csrno) case CSR_CYCLEH: if (!get_field(env->hcounteren, HCOUNTEREN_CY) && get_field(env->mcounteren, HCOUNTEREN_CY)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_TIMEH: if (!get_field(env->hcounteren, HCOUNTEREN_TM) && get_field(env->mcounteren, HCOUNTEREN_TM)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_INSTRETH: if (!get_field(env->hcounteren, HCOUNTEREN_IR) && get_field(env->mcounteren, HCOUNTEREN_IR)) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNT= ER3H)) && get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTE= R3H))) { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; } } } #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int ctr32(CPURISCVState *env, int csrno) +static RiscVException ctr32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 return ctr(env, csrno); } =20 #if !defined(CONFIG_USER_ONLY) -static int any(CPURISCVState *env, int csrno) +static RiscVException any(CPURISCVState *env, int csrno) { - return 0; + return RISCV_EXCP_NONE; } =20 -static int any32(CPURISCVState *env, int csrno) +static RiscVException any32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 return any(env, csrno); =20 } =20 -static int smode(CPURISCVState *env, int csrno) +static RiscVException smode(CPURISCVState *env, int csrno) { - return -!riscv_has_ext(env, RVS); + if (riscv_has_ext(env, RVS)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; } =20 -static int hmode(CPURISCVState *env, int csrno) +static RiscVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) { /* Hypervisor extension is supported */ if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv =3D=3D PRV_M) { - return 0; + return RISCV_EXCP_NONE; } else { - return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } =20 - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 -static int hmode32(CPURISCVState *env, int csrno) +static RiscVException hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return 0; + return RISCV_EXCP_NONE; } =20 return hmode(env, csrno); =20 } =20 -static int pmp(CPURISCVState *env, int csrno) +static RiscVException pmp(CPURISCVState *env, int csrno) { - return -!riscv_feature(env, RISCV_FEATURE_PMP); + if (riscv_feature(env, RISCV_FEATURE_PMP)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; } #endif =20 @@ -1312,8 +1320,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, return -RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); - if (ret < 0) { - return ret; + if (ret > 0) { + return -ret; } =20 /* execute combined read/write operation if it exists */ --=20 2.30.1 From nobody Wed Nov 19 12:13:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="266778852" IronPort-SDR: zkVy/U+FvSQ2XZC7djU5InjGr8dwJcBsA7xKDOu6wWZjHsXT/Dw2CFGr8GcVdJZFLqhlXYobH5 HFt6ditLDsP6Wo76VX9Mf6eYyTvaftGluhcQoq6KwSmi9XiwcjUDeyNKm1MondWNNhdAmSpH6Y k4OfEpZdjEDCrozEYFi8lzh8mYkTmoa/ji8cQgQ6gSDRZcb0PmhLWiMlP7+W0OsSm2YgSv7lCf Bvo5jt2tZO1Nxa5sNy1EF2MxuEVNPzz4S8HVpv6uhaBh4wC4R1+RSRDRN/zvz7KYZPuvBsIGHg jzlqgRJA5wjYbowYgxmHGJyq IronPort-SDR: AVFyNUFnF3/BWC4uiXgEDdW7bdA+m9omB+YrGmOE4d2wYZDvy6YBDnDItKEYrjvAhw9DG9jxAY iOLpHueRVKTUIMAm4RzGxRMCJohLH7u7FffqtoYopoca0UFnTphexF9Z14e/w0a/K4u6d0+lje x//wj8eKOZ1cwRelHvlMPSWTszcxEgBwduUtkjoQoySgKdSMQih78xlNoi4mDZkyGgl8zO9d+P dIeDX6nkp2LtD4kFKgrx0KRrJJOah+1+SJII0rJJsutA2l5TOTep1gBM8Eq3Rr9JK7sY58W2Al ydo= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions Date: Wed, 17 Mar 2021 13:39:55 -0400 Message-Id: <36b83d45e6cdc072574363b6ea937b0a5dad245a.1616002766.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/csr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da9baff6fb..d10f47c3fb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -181,7 +181,11 @@ static RiscVException hmode(CPURISCVState *env, int cs= rno) static RiscVException hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return RISCV_EXCP_NONE; + if (riscv_cpu_virt_enabled(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } else { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } } =20 return hmode(env, csrno); --=20 2.30.1 From nobody Wed Nov 19 12:13:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1616004162; cv=none; d=zohomail.com; s=zohoarc; b=GAxGIAEBH+VHl8404YG1Li2JhQyX76h5eU+d0a+6FljrGJdEsD2wjKr/AYntx7xgjP3Yswx30g5YEiZLIcbYm+9tjR9NlomTDCtwaQOyNmYSKQeylKIPQBkRnW/k+ClN75UToZMuXpTNK7LCiql4gTS+MVDIiycfP0CctLSzY6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616004162; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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IronPort-SDR: Kv6WeSDuYBAyz2Bfx5aEOPcUBh+d6IU5C7R6IGzoWxBgGTsQxhGFgJBfnRTJgVqfW0lXjuUQ9W JiWJ7SrimODlWrKlTHuR5MgXLtXuMKBnBgP2O9YiqyMbrB6LRE+ZHvQMuIf5pMygdb5p2nMPbb +JYSaKiSgl722wTtEvupAdrUPxLPvTqLOcdchumhBAdb14nsnZlQ0KowMVIXGeGwcCEGhyKELr AVSenKeos1JhZQNp96XWUxvMP2S8iHzTER3whHFoVuXm/iW8bjMMxkKOG0iZ/Df7Vv/pSIbpKC tuY= X-IronPort-AV: E=Sophos;i="5.81,257,1610380800"; d="scan'208";a="266778859" IronPort-SDR: pko2lAbeGNJ8xMIgFaDFO4I1wFOcEBvI1rNJMoGOKQqIMGmjTIlg8hcq3wm9AoTOp5BFw2Rqzg W9+Mal6xR7lEEQ79UN7OBnRdviASy84+nHqb3s4ip45Eq4qvj2XL0zitA9RAGpksLMJAS0vrYt D7zyE7dhsLHAvsLPcY712bQT/X3NYXjZWirtvwUTSSDhFZbsSjgG/iHtmHDkxrxp0UoSt02vq3 0VtGQzEHDss3EnA5RoN2L1bxsogMneHLY9Zg10Wv4nVxMksS1GV5V1XPFP6rSt/4fTUa3c+pWO WY7E2rBEEVACTikCrvRZwTU9 IronPort-SDR: vUBEzki3wZyINZE6OcUTSHymT+NQe0WiGrnjQj5z8/326z/jvofzT9AOXUJZTq30nlaNyY2beg Ff/SIsDArSMtPXbG4w0mjKJl7MjMbvSRh218Ifx9ais7suLdmLVJrwQjpL2t/fj74aai6PpWJP xG661unaf/d5xdp+qgskyWIj9Z8Uu9pD5VwP4Aj6o8PeZIgooq3QkQGEfhX83X2rFybpdXvYy2 o8Xgs7ze3bWut7j8nzlWRKv86wuipteviEjI4+dAk0qP1nCBZa545KsJMD0bUNcGJaJSjTPX1j Xfw= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations Date: Wed, 17 Mar 2021 13:39:59 -0400 Message-Id: <2be01f1201bdb0ce8795eed332ae1fb1678c2e2e.1616002766.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 658 +++++++++++++++++++++++++++------------------ 2 files changed, 398 insertions(+), 274 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 073a994d13..7af9fff776 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -471,12 +471,14 @@ static inline target_ulong riscv_csr_read(CPURISCVSta= te *env, int csrno) =20 typedef RiscVException (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); -typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value); -typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value); -typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); +typedef RiscVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value); +typedef RiscVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, + target_ulong new_value); +typedef RiscVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); =20 typedef struct { const char *name; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d10f47c3fb..61b2abdc14 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -203,57 +203,62 @@ static RiscVException pmp(CPURISCVState *env, int csr= no) #endif =20 /* User Floating-Point CSRs */ -static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_fflags(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D riscv_cpu_get_fflags(env); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_fflags(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_frm(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D env->frm; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_frm(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_frm(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_fcsr(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -262,14 +267,15 @@ static int read_fcsr(CPURISCVState *env, int csrno, t= arget_ulong *val) *val |=3D (env->vxrm << FSR_VXRM_SHIFT) | (env->vxsat << FSR_VXSAT_SHIFT); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_fcsr(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -279,59 +285,68 @@ static int write_fcsr(CPURISCVState *env, int csrno, = target_ulong val) env->vxsat =3D (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vtype(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vtype; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vl(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vl; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vxrm(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vxrm; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vxrm(CPURISCVState *env, int csrno, + target_ulong val) { env->vxrm =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vxsat(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vxsat; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vxsat(CPURISCVState *env, int csrno, + target_ulong val) { env->vxsat =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vstart(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vstart; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vstart(CPURISCVState *env, int csrno, + target_ulong val) { env->vstart =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* User Timers and Counters */ -static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_instret(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { @@ -342,10 +357,11 @@ static int read_instret(CPURISCVState *env, int csrno= , target_ulong *val) #else *val =3D cpu_get_host_ticks(); #endif - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_instreth(CPURISCVState *env, int csrno, + target_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { @@ -356,46 +372,50 @@ static int read_instreth(CPURISCVState *env, int csrn= o, target_ulong *val) #else *val =3D cpu_get_host_ticks() >> 32; #endif - return 0; + return RISCV_EXCP_NONE; } =20 #if defined(CONFIG_USER_ONLY) -static int read_time(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_time(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D cpu_get_host_ticks(); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_timeh(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D cpu_get_host_ticks() >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 #else /* CONFIG_USER_ONLY */ =20 -static int read_time(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_time(CPURISCVState *env, int csrno, + target_ulong *val) { uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_timeh(CPURISCVState *env, int csrno, + target_ulong *val) { uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine constants */ @@ -448,22 +468,26 @@ static const char valid_vm_1_10_64[16] =3D { }; =20 /* Machine Information Registers */ -static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_zero(CPURISCVState *env, int csrno, + target_ulong *val) { - return *val =3D 0; + *val =3D 0; + return RISCV_EXCP_NONE; } =20 -static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mhartid(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mhartid; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine Trap Setup */ -static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mstatus; - return 0; + return RISCV_EXCP_NONE; } =20 static int validate_vm(CPURISCVState *env, target_ulong vm) @@ -475,7 +499,8 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) } } =20 -static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mstatus(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; @@ -506,16 +531,18 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mstatush(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mstatus >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mstatush(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; @@ -526,26 +553,28 @@ static int write_mstatush(CPURISCVState *env, int csr= no, target_ulong val) =20 env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_misa(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->misa; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_misa(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_misa(CPURISCVState *env, int csrno, + target_ulong val) { if (!riscv_feature(env, RISCV_FEATURE_MISA)) { /* drop write to misa */ - return 0; + return RISCV_EXCP_NONE; } =20 /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ - return 0; + return RISCV_EXCP_NONE; } =20 /* 'E' excludes all other extensions */ @@ -553,7 +582,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) /* when we support 'E' we can do "val =3D RVE;" however * for now we just drop writes if 'E' is present. */ - return 0; + return RISCV_EXCP_NONE; } =20 /* Mask extensions that are not supported by this hart */ @@ -584,55 +613,63 @@ static int write_misa(CPURISCVState *env, int csrno, = target_ulong val) =20 env->misa =3D val; =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_medeleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->medeleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_medeleg(CPURISCVState *env, int csrno, + target_ulong val) { env->medeleg =3D (env->medeleg & ~delegable_excps) | (val & delegable_= excps); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mideleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mideleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mideleg(CPURISCVState *env, int csrno, + target_ulong val) { env->mideleg =3D (env->mideleg & ~delegable_ints) | (val & delegable_i= nts); if (riscv_has_ext(env, RVH)) { env->mideleg |=3D VS_MODE_INTERRUPTS; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mie(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mie; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mie(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mie(CPURISCVState *env, int csrno, + target_ulong val) { env->mie =3D (env->mie & ~all_ints) | (val & all_ints); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mtvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mtvec(CPURISCVState *env, int csrno, + target_ulong val) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -640,92 +677,105 @@ static int write_mtvec(CPURISCVState *env, int csrno= , target_ulong val) } else { qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RiscVException read_mcounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mcounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RiscVException write_mcounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->mcounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) +static RiscVException read_mscounteren(CPURISCVState *env, int csrno, + target_ulong *val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } *val =3D env->mcounteren; - return 0; + return RISCV_EXCP_NONE; } =20 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ -static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) +static RiscVException write_mscounteren(CPURISCVState *env, int csrno, + target_ulong val) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } env->mcounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Machine Trap Handling */ -static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->mscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mepc(CPURISCVState *env, int csrno, + target_ulong val) { env->mepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mcause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mcause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mcause(CPURISCVState *env, int csrno, + target_ulong val) { env->mcause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mbadaddr(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mbadaddr; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mbadaddr(CPURISCVState *env, int csrno, + target_ulong val) { env->mbadaddr =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RiscVException rmw_mip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ @@ -742,25 +792,28 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, *ret_value =3D old_mip; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 /* Supervisor Trap Setup */ -static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_sstatus(CPURISCVState *env, int csrno, + target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); *val =3D env->mstatus & mask; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_sstatus(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } =20 -static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_sie(CPURISCVState *env, int csrno, + target_ulong *val) { if (riscv_cpu_virt_enabled(env)) { /* Tell the guest the VS bits, shifted to the S bit locations */ @@ -768,10 +821,11 @@ static int read_sie(CPURISCVState *env, int csrno, ta= rget_ulong *val) } else { *val =3D env->mie & env->mideleg; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_sie(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong newval; =20 @@ -786,13 +840,15 @@ static int write_sie(CPURISCVState *env, int csrno, t= arget_ulong val) return write_mie(env, CSR_MIE, newval); } =20 -static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_stvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->stvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_stvec(CPURISCVState *env, int csrno, + target_ulong val) { /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D reserv= ed */ if ((val & 3) < 2) { @@ -800,72 +856,83 @@ static int write_stvec(CPURISCVState *env, int csrno,= target_ulong val) } else { qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RiscVException read_scounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->scounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_scounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RiscVException write_scounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->scounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Supervisor Trap Handling */ -static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_sscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->sscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_sscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->sscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_sepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->sepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_sepc(CPURISCVState *env, int csrno, + target_ulong val) { env->sepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_scause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->scause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_scause(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_scause(CPURISCVState *env, int csrno, + target_ulong val) { env->scause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_sbadaddr(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->sbadaddr; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_sbadaddr(CPURISCVState *env, int csrno, + target_ulong val) { env->sbadaddr =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RiscVException rmw_sip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { int ret; =20 @@ -873,8 +940,8 @@ static int rmw_sip(CPURISCVState *env, int csrno, targe= t_ulong *ret_value, /* Shift the new values to line up with the VS bits */ ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, (write_mask & sip_writable_mask) << 1 & env->mideleg= ); - ret &=3D vsip_writable_mask; - ret >>=3D 1; + *ret_value &=3D vsip_writable_mask; + *ret_value >>=3D 1; } else { ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); @@ -885,32 +952,34 @@ static int rmw_sip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, } =20 /* Supervisor Protection and Translation */ -static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_satp(CPURISCVState *env, int csrno, + target_ulong *val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; - return 0; + return RISCV_EXCP_NONE; } =20 if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_satp(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_satp(CPURISCVState *env, int csrno, + target_ulong val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - return 0; + return RISCV_EXCP_NONE; } if (validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } else { if ((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); @@ -918,11 +987,12 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) env->satp =3D val; } } - return 0; + return RISCV_EXCP_NONE; } =20 /* Hypervisor Extensions */ -static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hstatus; if (!riscv_cpu_is_32bit(env)) { @@ -931,10 +1001,11 @@ static int read_hstatus(CPURISCVState *env, int csrn= o, target_ulong *val) } /* We only support little endian */ *val =3D set_field(*val, HSTATUS_VSBE, 0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hstatus(CPURISCVState *env, int csrno, + target_ulong val) { env->hstatus =3D val; if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) !=3D 2) { @@ -943,35 +1014,40 @@ static int write_hstatus(CPURISCVState *env, int csr= no, target_ulong val) if (get_field(val, HSTATUS_VSBE) !=3D 0) { qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hedeleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hedeleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hedeleg(CPURISCVState *env, int csrno, + target_ulong val) { env->hedeleg =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hideleg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hideleg; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hideleg(CPURISCVState *env, int csrno, + target_ulong val) { env->hideleg =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RiscVException rmw_hvip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_= mask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); @@ -981,8 +1057,9 @@ static int rmw_hvip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, return ret; } =20 -static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RiscVException rmw_hip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_m= ask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); @@ -992,103 +1069,119 @@ static int rmw_hip(CPURISCVState *env, int csrno, = target_ulong *ret_value, return ret; } =20 -static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hie(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mie & VS_MODE_INTERRUPTS; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hie(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hie(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_M= ODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); } =20 -static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) +static RiscVException read_hcounteren(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hcounteren; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong va= l) +static RiscVException write_hcounteren(CPURISCVState *env, int csrno, + target_ulong val) { env->hcounteren =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hgeie(CPURISCVState *env, int csrno, + target_ulong *val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hgeie(CPURISCVState *env, int csrno, + target_ulong val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_htval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->htval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htval(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_htval(CPURISCVState *env, int csrno, + target_ulong val) { env->htval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_htinst(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->htinst; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_htinst(CPURISCVState *env, int csrno, + target_ulong val) { - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hgeip(CPURISCVState *env, int csrno, + target_ulong *val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hgeip(CPURISCVState *env, int csrno, + target_ulong val) { qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_hgatp(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->hgatp; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_hgatp(CPURISCVState *env, int csrno, + target_ulong val) { env->hgatp =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *va= l) +static RiscVException read_htimedelta(CPURISCVState *env, int csrno, + target_ulong *val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong va= l) +static RiscVException write_htimedelta(CPURISCVState *env, int csrno, + target_ulong val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_is_32bit(env)) { @@ -1096,182 +1189,208 @@ static int write_htimedelta(CPURISCVState *env, i= nt csrno, target_ulong val) } else { env->htimedelta =3D val; } - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *v= al) +static RiscVException read_htimedeltah(CPURISCVState *env, int csrno, + target_ulong *val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong v= al) +static RiscVException write_htimedeltah(CPURISCVState *env, int csrno, + target_ulong val) { if (!env->rdtime_fn) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); - return 0; + return RISCV_EXCP_NONE; } =20 /* Virtual CSR Registers */ -static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vsstatus(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsstatus; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vsstatus(CPURISCVState *env, int csrno, + target_ulong val) { uint64_t mask =3D (target_ulong)-1; env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +static RiscVException rmw_vsip(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_= mask) { - int ret =3D rmw_mip(env, 0, ret_value, new_value, - write_mask & env->mideleg & vsip_writable_mask); - return ret; + return rmw_mip(env, 0, ret_value, new_value, + write_mask & env->mideleg & vsip_writable_mask); } =20 -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vsie(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mie & env->mideleg & VS_MODE_INTERRUPTS; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vsie(CPURISCVState *env, int csrno, + target_ulong val) { target_ulong newval =3D (env->mie & ~env->mideleg) | (val & env->midel= eg & MIP_VSSIP); return write_mie(env, CSR_MIE, newval); } =20 -static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vstvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vstvec; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vstvec(CPURISCVState *env, int csrno, + target_ulong val) { env->vstvec =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vsscratch(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsscratch; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vsscratch(CPURISCVState *env, int csrno, + target_ulong val) { env->vsscratch =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vsepc(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsepc; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vsepc(CPURISCVState *env, int csrno, + target_ulong val) { env->vsepc =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vscause(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vscause; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vscause(CPURISCVState *env, int csrno, + target_ulong val) { env->vscause =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vstval(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vstval; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vstval(CPURISCVState *env, int csrno, + target_ulong val) { env->vstval =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_vsatp(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->vsatp; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_vsatp(CPURISCVState *env, int csrno, + target_ulong val) { env->vsatp =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mtval2(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtval2; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mtval2(CPURISCVState *env, int csrno, + target_ulong val) { env->mtval2 =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_mtinst(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D env->mtinst; - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_mtinst(CPURISCVState *env, int csrno, + target_ulong val) { env->mtinst =3D val; - return 0; + return RISCV_EXCP_NONE; } =20 /* Physical Memory Protection */ -static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_pmpcfg(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_pmpcfg(CPURISCVState *env, int csrno, + target_ulong val) { pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); - return 0; + return RISCV_EXCP_NONE; } =20 -static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) +static RiscVException read_pmpaddr(CPURISCVState *env, int csrno, + target_ulong *val) { *val =3D pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); - return 0; + return RISCV_EXCP_NONE; } =20 -static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) +static RiscVException write_pmpaddr(CPURISCVState *env, int csrno, + target_ulong val) { pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); - return 0; + return RISCV_EXCP_NONE; } =20 #endif @@ -1324,24 +1443,27 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, return -RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); - if (ret > 0) { + if (ret !=3D RISCV_EXCP_NONE) { return -ret; } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { - return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); + ret =3D csr_ops[csrno].op(env, csrno, ret_value, new_value, write_= mask); + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; + } + return 0; } =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { return -RISCV_EXCP_ILLEGAL_INST; } - /* read old value */ ret =3D csr_ops[csrno].read(env, csrno, &old_value); - if (ret < 0) { - return ret; + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; } =20 /* write value if writable and write mask set, otherwise drop writes */ @@ -1349,8 +1471,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, new_value =3D (old_value & ~write_mask) | (new_value & write_mask); if (csr_ops[csrno].write) { ret =3D csr_ops[csrno].write(env, csrno, new_value); - if (ret < 0) { - return ret; + if (ret !=3D RISCV_EXCP_NONE) { + return -ret; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 11 +++++++---- target/riscv/csr.c | 37 ++++++++++++++++++------------------- target/riscv/gdbstub.c | 8 ++++---- target/riscv/op_helper.c | 18 +++++++++--------- 4 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7af9fff776..179685d07b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -451,10 +451,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *pflags =3D flags; } =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask); +RiscVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask= ); +RiscVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); =20 static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 61b2abdc14..fbe38dd261 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1404,10 +1404,11 @@ static RiscVException write_pmpaddr(CPURISCVState *= env, int csrno, * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); */ =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +RiscVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) { - int ret; + RiscVException ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -1429,41 +1430,37 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { - ret =3D csr_ops[csrno].op(env, csrno, ret_value, new_value, write_= mask); - if (ret !=3D RISCV_EXCP_NONE) { - return -ret; - } - return 0; + return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); } =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } /* read old value */ ret =3D csr_ops[csrno].read(env, csrno, &old_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* write value if writable and write mask set, otherwise drop writes */ @@ -1472,7 +1469,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, if (csr_ops[csrno].write) { ret =3D csr_ops[csrno].write(env, csrno, new_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } } } @@ -1482,17 +1479,19 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, *ret_value =3D old_value; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. */ -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask) +RiscVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) { - int ret; + RiscVException ret; #if !defined(CONFIG_USER_ONLY) env->debugger =3D true; #endif diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a..fdc51ea165 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -71,7 +71,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArr= ay *buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, &val, 0, 0); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -94,7 +94,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t = *mem_buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, NULL, val, -1); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } @@ -108,7 +108,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteA= rray *buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, &val, 0, 0); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -122,7 +122,7 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_= t *mem_buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, NULL, val, -1); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eddcb94de..c84b9f8557 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -42,10 +42,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ul= ong src, target_ulong csr) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, src, -1); + RiscVException ret =3D riscv_csrrw(env, csr, &val, src, -1); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -54,10 +54,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + RiscVException ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src = : 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -66,10 +66,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + RiscVException ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src := 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } --=20 2.30.1