[v2] RISC-V: Convert the CSR access functions to use

[PATCH v2 0/5] RISC-V: Convert the CSR access functions to use

Alistair Francis posted 5 patches 3 years ago

Diff against v1
Download series mbox

Test checkpatch passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1617290165.git.alistair.francis@wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Alistair Francis <Alistair.Francis@wdc.com>

target/riscv/cpu.h        |  28 +-
target/riscv/cpu_bits.h   |  44 +--
target/riscv/cpu.c        |   2 +-
target/riscv/cpu_helper.c |   4 +-
target/riscv/csr.c        | 740 ++++++++++++++++++++++----------------
target/riscv/gdbstub.c    |   8 +-
target/riscv/op_helper.c  |  18 +-
7 files changed, 492 insertions(+), 352 deletions(-)

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[PATCH v2 0/5] RISC-V: Convert the CSR access functions to use

Posted by Alistair Francis 3 years ago

V2:
     - Renmae the enum
     - Rebase on master
     - Fix a few incorrect returns

Alistair Francis (5):
  target/riscv: Convert the RISC-V exceptions to an enum
  target/riscv: Use the RISCVException enum for CSR predicates
  target/riscv: Fix 32-bit HS mode access permissions
  target/riscv: Use the RISCVException enum for CSR operations
  target/riscv: Use RISCVException enum for CSR access

 target/riscv/cpu.h        |  28 +-
 target/riscv/cpu_bits.h   |  44 +--
 target/riscv/cpu.c        |   2 +-
 target/riscv/cpu_helper.c |   4 +-
 target/riscv/csr.c        | 740 ++++++++++++++++++++++----------------
 target/riscv/gdbstub.c    |   8 +-
 target/riscv/op_helper.c  |  18 +-
 7 files changed, 492 insertions(+), 352 deletions(-)

-- 
2.31.0

Re: [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use

Posted by Alistair Francis 3 years ago

On Thu, Apr 1, 2021 at 11:19 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> V2:
>      - Renmae the enum
>      - Rebase on master
>      - Fix a few incorrect returns
>
> Alistair Francis (5):
>   target/riscv: Convert the RISC-V exceptions to an enum
>   target/riscv: Use the RISCVException enum for CSR predicates
>   target/riscv: Fix 32-bit HS mode access permissions
>   target/riscv: Use the RISCVException enum for CSR operations
>   target/riscv: Use RISCVException enum for CSR access

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h        |  28 +-
>  target/riscv/cpu_bits.h   |  44 +--
>  target/riscv/cpu.c        |   2 +-
>  target/riscv/cpu_helper.c |   4 +-
>  target/riscv/csr.c        | 740 ++++++++++++++++++++++----------------
>  target/riscv/gdbstub.c    |   8 +-
>  target/riscv/op_helper.c  |  18 +-
>  7 files changed, 492 insertions(+), 352 deletions(-)
>
> --
> 2.31.0
>