[v3] target/riscv: parametrize debug trigger number

[PATCH v3 0/3] target/riscv: parametrize debug trigger number

Posted by Daniel Henrique Barboza 1 month, 2 weeks ago

Hi,

In this new version we're adding Phil's comments in v2, in particular
the need for an unrealize() callback to free the stuff we're now
allocating.

Patches based on alistair/riscv-to-apply.next.

Changes from v2:
- patch 1 (new):
  - add RISC-V CPU unrealize callback
- patch 2 (former 1):
  - free allocated debug trigger arrays during unrealize()
  - change version_id and minimum_version from vmstate_debug
- patch 3 (former 2):
  - do not touch vmstate_debug version_id/minimum_version_id 
  - added Phil's R-b
- v2 link: https://lore.kernel.org/qemu-devel/20260610205457.1868701-1-daniel.barboza@oss.qualcomm.com/


Daniel Henrique Barboza (3):
  target/riscv/cpu: add CPU unrealize callback
  target/riscv: dynamic alloc of debug trigger arrays
  target/riscv: add 'num-triggers' debug property

 target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
 target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
 target/riscv/csr.c     |  2 +-
 target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
 target/riscv/debug.h   |  1 +
 target/riscv/machine.c | 16 ++++++++++-----
 6 files changed, 109 insertions(+), 21 deletions(-)

-- 
2.43.0

Re: [PATCH v3 0/3] target/riscv: parametrize debug trigger number

Posted by Alistair Francis 1 month, 1 week ago

On Thu, Jun 11, 2026 at 10:34 PM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
> Hi,
>
> In this new version we're adding Phil's comments in v2, in particular
> the need for an unrealize() callback to free the stuff we're now
> allocating.
>
> Patches based on alistair/riscv-to-apply.next.

Hmm... I can't get this to apply. Mind resending?

Alistair

>
> Changes from v2:
> - patch 1 (new):
>   - add RISC-V CPU unrealize callback
> - patch 2 (former 1):
>   - free allocated debug trigger arrays during unrealize()
>   - change version_id and minimum_version from vmstate_debug
> - patch 3 (former 2):
>   - do not touch vmstate_debug version_id/minimum_version_id
>   - added Phil's R-b
> - v2 link: https://lore.kernel.org/qemu-devel/20260610205457.1868701-1-daniel.barboza@oss.qualcomm.com/
>
>
> Daniel Henrique Barboza (3):
>   target/riscv/cpu: add CPU unrealize callback
>   target/riscv: dynamic alloc of debug trigger arrays
>   target/riscv: add 'num-triggers' debug property
>
>  target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
>  target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
>  target/riscv/csr.c     |  2 +-
>  target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
>  target/riscv/debug.h   |  1 +
>  target/riscv/machine.c | 16 ++++++++++-----
>  6 files changed, 109 insertions(+), 21 deletions(-)
>
> --
> 2.43.0
>
>

Re: [PATCH v3 0/3] target/riscv: parametrize debug trigger number

Posted by Daniel Henrique Barboza 1 month, 1 week ago


On 6/16/2026 2:37 AM, Alistair Francis wrote:
> On Thu, Jun 11, 2026 at 10:34 PM Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com> wrote:
>>
>> Hi,
>>
>> In this new version we're adding Phil's comments in v2, in particular
>> the need for an unrealize() callback to free the stuff we're now
>> allocating.
>>
>> Patches based on alistair/riscv-to-apply.next.
> 
> Hmm... I can't get this to apply. Mind resending?

Sure thing.  I'll rebase and send a v4.

Cheers,
Daniel

> 
> Alistair
> 
>>
>> Changes from v2:
>> - patch 1 (new):
>>    - add RISC-V CPU unrealize callback
>> - patch 2 (former 1):
>>    - free allocated debug trigger arrays during unrealize()
>>    - change version_id and minimum_version from vmstate_debug
>> - patch 3 (former 2):
>>    - do not touch vmstate_debug version_id/minimum_version_id
>>    - added Phil's R-b
>> - v2 link: https://lore.kernel.org/qemu-devel/20260610205457.1868701-1-daniel.barboza@oss.qualcomm.com/
>>
>>
>> Daniel Henrique Barboza (3):
>>    target/riscv/cpu: add CPU unrealize callback
>>    target/riscv: dynamic alloc of debug trigger arrays
>>    target/riscv: add 'num-triggers' debug property
>>
>>   target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
>>   target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
>>   target/riscv/csr.c     |  2 +-
>>   target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
>>   target/riscv/debug.h   |  1 +
>>   target/riscv/machine.c | 16 ++++++++++-----
>>   6 files changed, 109 insertions(+), 21 deletions(-)
>>
>> --
>> 2.43.0
>>
>>