[v4] target/riscv: parametrize debug trigger number

[PATCH v4 0/3] target/riscv: parametrize debug trigger number

Daniel Henrique Barboza posted 3 patches 1 month, 1 week ago

Diff against v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260617131710.1855353-1-daniel.barboza@oss.qualcomm.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
target/riscv/csr.c     |  2 +-
target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
target/riscv/debug.h   |  1 +
target/riscv/machine.c | 16 ++++++++++-----
6 files changed, 109 insertions(+), 21 deletions(-)

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[PATCH v4 0/3] target/riscv: parametrize debug trigger number

Posted by Daniel Henrique Barboza 1 month, 1 week ago

Hi,

This is a re-send after rebase with current master after the recent
RISC-V PR got merged.  No other changes made.

Changes from v4:
- rebased to 'master'
- v3 link: https://lore.kernel.org/qemu-devel/20260611123412.2135600-1-daniel.barboza@oss.qualcomm.com/

Daniel Henrique Barboza (3):
  target/riscv/cpu: add CPU unrealize callback
  target/riscv: dynamic alloc of debug trigger arrays
  target/riscv: add 'num-triggers' debug property

 target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
 target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
 target/riscv/csr.c     |  2 +-
 target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
 target/riscv/debug.h   |  1 +
 target/riscv/machine.c | 16 ++++++++++-----
 6 files changed, 109 insertions(+), 21 deletions(-)

-- 
2.43.0

Re: [PATCH v4 0/3] target/riscv: parametrize debug trigger number

Posted by Alistair Francis 1 month ago

On Wed, Jun 17, 2026 at 11:18 PM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
> Hi,
>
> This is a re-send after rebase with current master after the recent
> RISC-V PR got merged.  No other changes made.
>
> Changes from v4:
> - rebased to 'master'
> - v3 link: https://lore.kernel.org/qemu-devel/20260611123412.2135600-1-daniel.barboza@oss.qualcomm.com/
>
> Daniel Henrique Barboza (3):
>   target/riscv/cpu: add CPU unrealize callback
>   target/riscv: dynamic alloc of debug trigger arrays
>   target/riscv: add 'num-triggers' debug property

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c     | 26 ++++++++++++++++++++++++
>  target/riscv/cpu.h     | 39 ++++++++++++++++++++++++++++-------
>  target/riscv/csr.c     |  2 +-
>  target/riscv/debug.c   | 46 ++++++++++++++++++++++++++++++++++--------
>  target/riscv/debug.h   |  1 +
>  target/riscv/machine.c | 16 ++++++++++-----
>  6 files changed, 109 insertions(+), 21 deletions(-)
>
> --
> 2.43.0
>
>