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Thu, 11 Jun 2026 05:34:23 -0700 (PDT) X-Received: by 2002:a05:620a:2681:b0:915:9047:940b with SMTP id af79cd13be357-9160ac9ffa8mr369783185a.1.1781181262632; Thu, 11 Jun 2026 05:34:22 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, philmd@oss.qualcomm.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v3 1/3] target/riscv/cpu: add CPU unrealize callback Date: Thu, 11 Jun 2026 09:34:10 -0300 Message-ID: <20260611123412.2135600-2-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611123412.2135600-1-daniel.barboza@oss.qualcomm.com> References: <20260611123412.2135600-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: P-AcnCCqjVicWyvnKzJzoBpy7DRLfXhU X-Authority-Analysis: v=2.4 cv=B9eJFutM c=1 sm=1 tr=0 ts=6a2aab4f cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=MITIYaLR+oYcSln1dApPwg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=-V4TLcwJ7WInddZtJMgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDEyNSBTYWx0ZWRfX3Fbc0ZTS4SKl vBmqp8pSeerjrBAJ/yvJLR2bhxHUraSqc0PSFLkl4uaXfCoDjbZxBlAEs/SODE0+LnFyEyNifoI l4zKsWAgdiiom2XRfSW1v5mQaW0T6Kr2UjUwRb9YckAO3MJkzQDtQ+ov7QGJicgqBi1Ia2TACTV D/+KKkBFj98hlbmijAqKz0bVmCS/d/PhDUvKCBnwulQ3lBXaJj//qa7bbrZfwreLPd0qQ40Knnh z23fwtvAfM0ObePB8vXmxTiC5+vAUtq2qsgGGal4yBbzMIMH6XbcrSzUMdfNRH4VH+fQiJGOzH5 1Zd1UP/ZhoxyBn12U4Uksv2JCLgR4DVeCo133BpKforIxhOn5XMGL3+zqraeFJkSiGQfe30wAPD zz0xDfNy5fYHIuewI1owp2PWE6a0x6YqMF14ELO/B066qvVjvmFcrubQoHNb4BbI63YaEDmHzj1 N9tis5E/gQ9QKnC0gIw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDEyNSBTYWx0ZWRfXxvHocEBJpP6s RCCsfUegEa4qJbz7zwxXVnXge3/qYAqgyq9ZTz1m756VxthfWp/LuyJPazMmPIdlobC9CQ47rnU BF+6a922rcnw8K949GkoT28Nxka5F1o= X-Proofpoint-ORIG-GUID: P-AcnCCqjVicWyvnKzJzoBpy7DRLfXhU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_02,2026-06-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110125 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781181300023158500 Next patch is going to dynamically allocate debug trigger arrays during realize() time. We need a way of freeing them during unrealize(), which doesn't exist at this moment. There's a lot going on in that patch already so we're adding the callback infrastructure beforehand. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1b10cc7ef..5b2133d811 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1012,6 +1012,13 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) mcc->parent_realize(dev, errp); } =20 +static void riscv_cpu_unrealize(DeviceState *dev) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + + mcc->parent_unrealize(dev); +} + bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) { if (tcg_enabled()) { @@ -2667,6 +2674,8 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, const void *data) =20 device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); + device_class_set_parent_unrealize(dc, riscv_cpu_unrealize, + &mcc->parent_unrealize); =20 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NUL= L, &mcc->parent_phases); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c98652cd62..11cd710990 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -575,6 +575,7 @@ typedef struct RISCVCPUDef { /** * RISCVCPUClass: * @parent_realize: The parent class' realize handler. + * @parent_unrealize: The parent class' unrealize handler. * @parent_phases: The parent class' reset phase handlers. * * A RISCV CPU model. @@ -583,6 +584,7 @@ struct RISCVCPUClass { CPUClass parent_class; =20 DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; ResettablePhases parent_phases; RISCVCPUDef *def; }; --=20 2.43.0 From nobody Sun Jul 26 13:29:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781181306; cv=none; d=zohomail.com; s=zohoarc; b=IEmUq18bxtjFkMB8MucysC89G/33SsmxpYqoj209V8KfSffvV4yC3iy6vp6M4ynIQBVMHDEOo68maiQi+xDD7GzJUI0c9kgerO7dF2VOvAfX1phuj8PJxO3O97sISmMN6RpipBTgwI5XWlMs9uc4IHoodNQgT8tlOK7O8v1Kzug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781181306; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x3+hg7CD2aE+8MtDu9XIz3W62m6/gYV7CTzdEVS2dvo=; b=Mm0/bpmDNbDjP3NUpPdXfJJhzYbeUmUoQePuz4tDntp7mqykX50DzuLcCZG1sm4aTz44DnbGPzRt40rln4bjnkDC3rvEto4GfG2CGO5Fejbc0x+wLULBAg2TYnVnRAul84ypsKLs0QZC678KsJsTzEhnDsQnpUF207pHzGKLJ7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781181306598317.7913617643112; Thu, 11 Jun 2026 05:35:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXecD-0000so-N1; Thu, 11 Jun 2026 08:34:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXecC-0000rN-Ff for qemu-devel@nongnu.org; Thu, 11 Jun 2026 08:34:32 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXecA-0003FD-4m for qemu-devel@nongnu.org; Thu, 11 Jun 2026 08:34:32 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65BCSnWT617049 for ; Thu, 11 Jun 2026 12:34:28 GMT Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eqe6tkdpx-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 11 Jun 2026 12:34:27 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-915767b341eso880112485a.3 for ; Thu, 11 Jun 2026 05:34:27 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com (201-26-7-9.dsl.telesp.net.br. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781181307973158500 Content-Type: text/plain; charset="utf-8" The debug trigger facility consists of a set of arrays: tdata1-3, cpu_breakpoint, cpu_watchpoint and itrigger_timer. All of them are static allocated with RV_MAX_TRIGGERS (2). This means that all RISC-V cpus will have 2 triggers per hart. The RISC-V Server Ref demands at least 11 triggers per hart, and several CPUs in the wild works with 4+ triggers. We need more flexibility, ergo we need to parametrize the amount of triggers and make it configurable. Before doing that we need to handle a situation faced in a previous attempt [1]. We were unable to set the tdataN array length in vmstate_debug, meaning that we would always migrate RV_MAX_TRIGGERS regardless of the actual amount of triggers in play. To fix that we need to change the tdata arrays from static to dynamic, allowing us to use VMSTATE_VARRAY_UINT32(). This also means that, in contrast with [1], we have the opportunity to turn all trigger arrays into dynamic allocation and reduce the amount of stuff being carried by CPURISCVState, or in other words, we can carry just what we're using instead of a static max value. All the forementioned trigger facility arrays are now dynamic. They are allocated and freed during realize/unrealize, and their size is expressed by env->num_triggers. All relevant code is changed to use env->num_triggers instead of the RV_MAX_TRIGGERS to loop through each array. This will make it easier for the next patch to parametrize env->num_triggers. [1] https://lore.kernel.org/qemu-devel/94c772b0-5231-40e4-9cab-6ac39b9e4d45= @oss.qualcomm.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 18 +++++++++++------ target/riscv/csr.c | 2 +- target/riscv/debug.c | 46 ++++++++++++++++++++++++++++++++++-------- target/riscv/debug.h | 1 + target/riscv/machine.c | 16 ++++++++++----- 6 files changed, 69 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5b2133d811..b20271a220 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1015,7 +1015,13 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) static void riscv_cpu_unrealize(DeviceState *dev) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); +#ifndef CONFIG_USER_ONLY + RISCVCPU *cpu =3D RISCV_CPU(dev); =20 + if (cpu->cfg.debug) { + riscv_trigger_unrealize(&cpu->env); + } +#endif mcc->parent_unrealize(dev); } =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11cd710990..ea92e2c68c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -467,12 +467,18 @@ struct CPUArchState { /* trigger module */ uint16_t mcontext; uint8_t trigger_cur; - uint64_t tdata1[RV_MAX_TRIGGERS]; - uint64_t tdata2[RV_MAX_TRIGGERS]; - uint64_t tdata3[RV_MAX_TRIGGERS]; - struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; - struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; - QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; + /* + * num_triggers is the length of tdata1, tdata2, tdata3, + * cpu_breakpoint, cpu_watchpoint and itrigger_timer + * arrays. + */ + uint32_t num_triggers; + uint64_t *tdata1; + uint64_t *tdata2; + uint64_t *tdata3; + struct CPUBreakpoint **cpu_breakpoint; + struct CPUWatchpoint **cpu_watchpoint; + QEMUTimer **itrigger_timer; int64_t last_icount; bool itrigger_enabled; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ec931a8c3d..82afad82db 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5436,7 +5436,7 @@ static RISCVException read_tdata(CPURISCVState *env, = int csrno, target_ulong *val) { /* return 0 in tdata1 to end the trigger enumeration */ - if (env->trigger_cur >=3D RV_MAX_TRIGGERS && csrno =3D=3D CSR_TDATA1) { + if (env->trigger_cur >=3D env->num_triggers && csrno =3D=3D CSR_TDATA1= ) { *val =3D 0; return RISCV_EXCP_NONE; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 30d39ee5cd..9a4910c431 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -172,7 +172,7 @@ target_ulong tselect_csr_read(CPURISCVState *env) =20 void tselect_csr_write(CPURISCVState *env, target_ulong val) { - if (val < RV_MAX_TRIGGERS) { + if (val < env->num_triggers) { env->trigger_cur =3D val; } } @@ -701,7 +701,7 @@ static bool check_itrigger_priv(CPURISCVState *env, int= index) bool riscv_itrigger_enabled(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -721,7 +721,7 @@ bool riscv_itrigger_enabled(CPURISCVState *env) void helper_itrigger_match(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -750,7 +750,7 @@ static void riscv_itrigger_update_count(CPURISCVState *= env) int64_t last_icount =3D env->last_icount, current_icount; current_icount =3D env->last_icount =3D icount_get_raw(); =20 - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -950,7 +950,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) int i; =20 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -996,7 +996,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) int flags; int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -1049,19 +1049,49 @@ void riscv_trigger_realize(CPURISCVState *env) { int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + /* + * Alloc env->tdata1/2/3, cpu_breakpoint, cpu_watchpoint and + * itrigger_timer dynamically. This is overkill now + * given that they could be static arrays with RV_MAX_TRIGGERS + * but we'll parametrize the trigger number later, i.e. the + * array length won't be static. + */ + env->num_triggers =3D RV_MAX_TRIGGERS; + env->tdata1 =3D g_new0(uint64_t, env->num_triggers); + env->tdata2 =3D g_new0(uint64_t, env->num_triggers); + env->tdata3 =3D g_new0(uint64_t, env->num_triggers); + env->cpu_breakpoint =3D g_new0(struct CPUBreakpoint *, env->num_trigge= rs); + env->cpu_watchpoint =3D g_new0(struct CPUWatchpoint *, env->num_trigge= rs); + env->itrigger_timer =3D g_new0(QEMUTimer *, env->num_triggers); + + for (i =3D 0; i < env->num_triggers; i++) { env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_itrigger_timer_cb, env= ); } } =20 +void riscv_trigger_unrealize(CPURISCVState *env) +{ + g_free(env->tdata1); + g_free(env->tdata2); + g_free(env->tdata3); + + g_free(env->cpu_breakpoint); + g_free(env->cpu_watchpoint); + + for (int i =3D 0; i < env->num_triggers; i++) { + timer_del(env->itrigger_timer[i]); + } + g_free(env->itrigger_timer); +} + void riscv_trigger_reset_hold(CPURISCVState *env) { target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; =20 /* init to type 2 triggers */ - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { /* * type =3D TRIGGER_TYPE_AD_MATCH * dmode =3D 0 (both debug and M-mode can write tdata) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 55a3ac72e6..a25d099b37 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -148,6 +148,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 void riscv_trigger_realize(CPURISCVState *env); +void riscv_trigger_unrealize(CPURISCVState *env); void riscv_trigger_reset_hold(CPURISCVState *env); =20 bool riscv_itrigger_enabled(CPURISCVState *env); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 6e70b145a5..ba96ceceef 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -240,16 +240,22 @@ static int debug_post_load(void *opaque, int version_= id) =20 static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .needed =3D debug_needed, .post_load =3D debug_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT16(env.mcontext, RISCVCPU), VMSTATE_UINT8(env.trigger_cur, RISCVCPU), - VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_VARRAY_UINT32(env.tdata1, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_VARRAY_UINT32(env.tdata2, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_VARRAY_UINT32(env.tdata3, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), VMSTATE_END_OF_LIST() } }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781181322137158500 All CPUs have the same amount of triggers: 2 triggers per hart, set via RV_MAX_TRIGGERS. This is not enough anymore: we'll have at least one future CPU that will demand more triggers per hart when implementing the RISC-V Server Ref Platform, requiring at least 11 triggers per hart. Parametrize the trigger amount using a new 'num_triggers' property. The default amount is kept at 2 for backwards compatibility. The new maximum is bumped to a generous 1024 triggers per hart, which hopefully will be enough for the foreseeable future. The property can be set in two ways: - a '.num_triggers' CPU definition flag, allowing CPUs to set a custom amount inside the CPU def in DEFINE_RISCV_CPU(); - a new 'num-triggers' user property. The user property has a higher priority than an existing '.num_triggers' CPU def setting. Assuming a hypothetical case where a CPU 'X' is defined with '.num_triggers =3D 8': - -cpu X,num-triggers=3D30 =3D> num_triggers set to 30 - -cpu X (...) =3D> num_triggers set to 8 For a CPU that doesn't set '.num_triggers': - -cpu rv64,num-triggers=3D30 =3D> num_triggers set to 30 - -cpu rv64 (...) =3D> num_triggers set to 2 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu.h | 19 ++++++++++++++++++- target/riscv/debug.c | 16 ++++++++-------- 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b20271a220..6d8f9ad3a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1167,6 +1167,11 @@ static void riscv_cpu_init(Object *obj) IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, "riscv.cpu.rnmi", RNMI_MAX); + + if (mcc->def->num_triggers) { + env->num_triggers =3D mcc->def->num_triggers; + } + #endif /* CONFIG_USER_ONLY */ =20 general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); @@ -2619,6 +2624,8 @@ static const Property riscv_cpu_properties[] =3D { DEFAULT_RNMI_IRQVEC), DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, DEFAULT_RNMI_EXCPVEC), + DEFINE_PROP_UINT32("num-triggers", RISCVCPU, env.num_triggers, + RV_DEFAULT_NUM_TRIGGERS), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), @@ -2764,6 +2771,10 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) { mcc->def->cfg.max_satp_mode =3D VM_1_10_SV32; } + + if (def->num_triggers) { + mcc->def->num_triggers =3D def->num_triggers; + } #endif } if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ea92e2c68c..38f02a9dc7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,7 +189,22 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implie= d_rules[]; #define RV_VLEN_MAX 1024 #define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 -#define RV_MAX_TRIGGERS 2 + +/* + * The Debug 1.0 spec allows a humongous amount of triggers. Section + * "Enumeration" says: "The above algorithm reads back tselect so that + * implementations which have 2^n triggers only need to implement n + * bits of tselect.". tselect can have up to XLEN bits, so the max + * theoretical RV_MAX_TRIGGERS value is 2^XLEN. + * + * Allowing 2^XLEN triggers per hart is silly so we'll set a max to a + * modest 1024 triggers, which is way more than what we see current + * hardware use (most chips uses 2-4 triggers per hart, RISC-V Server + * Ref requires at least 11). With a 1024 max per hart we'll be set + * for a long time ... hopefully. + */ +#define RV_MAX_TRIGGERS 1024 +#define RV_DEFAULT_NUM_TRIGGERS 2 =20 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) @@ -576,6 +591,8 @@ typedef struct RISCVCPUDef { RISCVCPUConfig cfg; bool bare; const RISCVCSR *custom_csrs; + /* This is just a setter for env->num_triggers. */ + uint32_t num_triggers; } RISCVCPUDef; =20 /** diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 9a4910c431..ba5bc6ae13 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "cpu.h" #include "target/riscv/debug.h" #include "trace.h" @@ -1049,14 +1050,13 @@ void riscv_trigger_realize(CPURISCVState *env) { int i; =20 - /* - * Alloc env->tdata1/2/3, cpu_breakpoint, cpu_watchpoint and - * itrigger_timer dynamically. This is overkill now - * given that they could be static arrays with RV_MAX_TRIGGERS - * but we'll parametrize the trigger number later, i.e. the - * array length won't be static. - */ - env->num_triggers =3D RV_MAX_TRIGGERS; + if (env->num_triggers > RV_MAX_TRIGGERS) { + error_report( + "Invalid configuration: 'num-triggers' must be less than %= u", + RV_MAX_TRIGGERS); + exit(1); + } + env->tdata1 =3D g_new0(uint64_t, env->num_triggers); env->tdata2 =3D g_new0(uint64_t, env->num_triggers); env->tdata3 =3D g_new0(uint64_t, env->num_triggers); --=20 2.43.0