On Wed, Jun 12, 2024 at 6:17 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> We define CPU options for WG CSR support in RISC-V CPUs which
> can be set by machine/device emulation. The RISC-V CSR emulation
> will also check this feature for emulating WG CSRs.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> ---
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/tcg/tcg-cpu.c | 11 +++++++++++
> 3 files changed, 22 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 69a08e8c2c..d70eedf957 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -204,6 +204,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
> ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
> + ISA_EXT_DATA_ENTRY(smwg, PRIV_VERSION_1_12_0, ext_smwg),
> + ISA_EXT_DATA_ENTRY(smwgd, PRIV_VERSION_1_12_0, ext_smwgd),
> + ISA_EXT_DATA_ENTRY(sswg, PRIV_VERSION_1_12_0, ext_sswg),
>
> DEFINE_PROP_END_OF_LIST(),
> };
> @@ -1595,6 +1598,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
> MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>
> + /* RISC-V WorldGuard v0.4 */
> + MULTI_EXT_CFG_BOOL("x-smwg", ext_smwg, false),
> + MULTI_EXT_CFG_BOOL("x-smwgd", ext_smwgd, false),
> + MULTI_EXT_CFG_BOOL("x-sswg", ext_sswg, false),
We want to add the functionality then expose the properties, as this
is user accessible and we want to maintain bistability.
I understand this doesn't break the build, but it's a bit strange to
allow users to enable something when at this point it doesn't yet work
Alistair
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e1e4f32698..23e779ae08 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -120,6 +120,9 @@ struct RISCVCPUConfig {
> bool ext_ssaia;
> bool ext_sscofpmf;
> bool ext_smepmp;
> + bool ext_smwg;
> + bool ext_smwgd;
> + bool ext_sswg;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 683f604d9f..dc86e6e1d5 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -726,6 +726,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> cpu->pmu_avail_ctrs = 0;
> }
>
> + /* RISC-V WorldGuard */
> + if (cpu->cfg.ext_sswg && !cpu->cfg.ext_smwg) {
> + error_setg(errp, "Sswg extension requires Smwg extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_smwgd != cpu->cfg.ext_sswg) {
> + error_setg(errp, "Smwgd/Sswg extensions should be enabled together");
> + return;
> + }
> +
> /*
> * Disable isa extensions based on priv spec after we
> * validated and set everything we need.
> --
> 2.17.1
>
>