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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f8393e8e53sm11363875ad.16.2024.06.12.01.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 01:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718180105; x=1718784905; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=t/AUOAInjkFfC7EhRiJBRMiTPdQ2lCm4ch6BlghBPuU=; b=aX6MP6oDirKKIplRDKeNZtxcVMIAo9p5Z1/F6DMVPKMte12z8pyX5h5YXaawEhAOnB NELYJRlkQy0sscSUAvsggWIdTD6pOANS2/+Tf6xwH3Vtu0oLmPvPieAvP0QHoDTcDMK6 kfjJcxpENdHZ9Xcw2SxjvrqIz2caErFVNyQkVVUJnx3lcQP9hooU55OGGbtGsAOJ3Of8 0SwJIrmLnByEUhCI+hqizlSemZrJLl0ZlhBSjK2Eh/KfPSLIX2AS7l2UGqgx9r8GC2LG mgRUN6k6BVWgPkpj2LXDZfOHOnYtnNCjWjXCp5Z0vdJDXkftyr9YdIBmW5FTKlx/cMhx nxtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718180105; x=1718784905; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=t/AUOAInjkFfC7EhRiJBRMiTPdQ2lCm4ch6BlghBPuU=; b=kbS0tTgadsgjiHizjkkwSyYKmcpl5zlxpStZMR1iPotILSMJV+GqNpQJyu2ZgUWvo/ jm6gVP4BZLG9bwelCkeY8SrIByEnUMmmyhIycIk7OFkYAQllahCmRJw4nEA8Mi6VZqcl GZ8YBVUErbrV3DEySbklAShXe4Fke/kQdA1orR+I0FZnYoSUZKEDJOZFxG/uXAHRLcQz 0jjKJRnrNxd7tSw+HtnmCbarFfn9yCbHDVWLh5FwVWlCeL4q4VHN/iw7a1AqZfDOz/10 CjVyTrzOohjnWM88MztfYj0ma3Bmd6kexExf3NO4hvoFnph7yop2LrPR4YwwCOdsutWa 9Lug== X-Gm-Message-State: AOJu0YwtWeQGOMKJTgTbi64GFy4Od5nD6D0h0BqTN9QHvk8QM7o1GuBk NjAzhy5HYkH9x5+qLQd2Z8SS1JIvByNnScV0PJdE06rNjLbya+Wd6FMjATDEwlivfkPS87NB+Vu hahiuwqtt6LhFZjrv2FIHNQh76dbBlig+dVhc+y/5DPRHzOQ9mCfnY4ycvPSqJGg6izErm8ZQs3 KTYL5btVNMvBxRQ6EICFdpwUNJVroqnI+ARZ/tbJsaGQ== X-Google-Smtp-Source: AGHT+IG5wJthYOfktPwpbknyCYAna1CFTxUI/ODaFFZ95fOwIwfQ0NUj0LE3JyOUAyDJz83FyZgtZw== X-Received: by 2002:a17:902:d48b:b0:1f7:345a:e23d with SMTP id d9443c01a7336-1f83b6f6b61mr11145425ad.31.1718180104409; Wed, 12 Jun 2024 01:15:04 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Peter Xu , David Hildenbrand , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension Date: Wed, 12 Jun 2024 16:14:05 +0800 Message-Id: <20240612081416.29704-6-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240612081416.29704-1-jim.shu@sifive.com> References: <20240612081416.29704-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718180233376100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We define CPU options for WG CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating WG CSRs. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/tcg/tcg-cpu.c | 11 +++++++++++ 3 files changed, 22 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69a08e8c2c..d70eedf957 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -204,6 +204,9 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), + ISA_EXT_DATA_ENTRY(smwg, PRIV_VERSION_1_12_0, ext_smwg), + ISA_EXT_DATA_ENTRY(smwgd, PRIV_VERSION_1_12_0, ext_smwgd), + ISA_EXT_DATA_ENTRY(sswg, PRIV_VERSION_1_12_0, ext_sswg), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -1595,6 +1598,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 + /* RISC-V WorldGuard v0.4 */ + MULTI_EXT_CFG_BOOL("x-smwg", ext_smwg, false), + MULTI_EXT_CFG_BOOL("x-smwgd", ext_smwgd, false), + MULTI_EXT_CFG_BOOL("x-sswg", ext_sswg, false), + DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..23e779ae08 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -120,6 +120,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_smwg; + bool ext_smwgd; + bool ext_sswg; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 683f604d9f..dc86e6e1d5 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -726,6 +726,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) cpu->pmu_avail_ctrs =3D 0; } =20 + /* RISC-V WorldGuard */ + if (cpu->cfg.ext_sswg && !cpu->cfg.ext_smwg) { + error_setg(errp, "Sswg extension requires Smwg extension"); + return; + } + + if (cpu->cfg.ext_smwgd !=3D cpu->cfg.ext_sswg) { + error_setg(errp, "Smwgd/Sswg extensions should be enabled together= "); + return; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. --=20 2.17.1