[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4

Jim Shu posted 16 patches 1 month ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240612081416.29704-1-jim.shu@sifive.com
Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Eduardo Habkost <eduardo@habkost.net>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Yanan Wang <wangyanan55@huawei.com>, Peter Xu <peterx@redhat.com>, David Hildenbrand <david@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, Michael Rolnik <mrolnik@gmail.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Song Gao <gaosong@loongson.cn>, Laurent Vivier <laurent@vivier.eu>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>, Stafford Horne <shorne@gmail.com>, Nicholas Piggin <npiggin@gmail.com>, Yoshinori Sato <ysato@users.sourceforge.jp>, Ilya Leoshkevich <iii@linux.ibm.com>, Thomas Huth <thuth@redhat.com>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Artyom Tarasenko <atar4qemu@gmail.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Max Filippov <jcmvbkbc@gmail.com>
accel/tcg/cputlb.c                   |   34 +-
docs/system/riscv/virt.rst           |   10 +
hw/misc/Kconfig                      |    3 +
hw/misc/meson.build                  |    1 +
hw/misc/riscv_wgchecker.c            | 1161 ++++++++++++++++++++++++++
hw/misc/riscv_worldguard.c           |  273 ++++++
hw/misc/trace-events                 |    9 +
hw/riscv/Kconfig                     |    1 +
hw/riscv/virt.c                      |  163 +++-
include/exec/exec-all.h              |   11 +-
include/exec/memattrs.h              |    5 +
include/hw/core/cpu.h                |    3 +
include/hw/misc/riscv_worldguard.h   |  123 +++
include/hw/riscv/virt.h              |   17 +-
system/physmem.c                     |   16 +-
target/alpha/helper.c                |    2 +-
target/arm/tcg/tlb_helper.c          |    2 +-
target/avr/helper.c                  |    2 +-
target/cris/helper.c                 |    2 +-
target/hppa/mem_helper.c             |    2 +-
target/i386/tcg/sysemu/excp_helper.c |    3 +-
target/loongarch/tcg/tlb_helper.c    |    2 +-
target/m68k/helper.c                 |   10 +-
target/microblaze/helper.c           |    8 +-
target/mips/tcg/sysemu/tlb_helper.c  |    4 +-
target/openrisc/mmu.c                |    2 +-
target/ppc/mmu_helper.c              |    2 +-
target/riscv/cpu.c                   |   16 +-
target/riscv/cpu.h                   |   12 +
target/riscv/cpu_bits.h              |    5 +
target/riscv/cpu_cfg.h               |    5 +
target/riscv/cpu_helper.c            |   69 +-
target/riscv/csr.c                   |  107 +++
target/riscv/tcg/tcg-cpu.c           |   11 +
target/rx/cpu.c                      |    3 +-
target/s390x/tcg/excp_helper.c       |    2 +-
target/sh4/helper.c                  |    2 +-
target/sparc/mmu_helper.c            |    6 +-
target/tricore/helper.c              |    2 +-
target/xtensa/helper.c               |    3 +-
40 files changed, 2054 insertions(+), 60 deletions(-)
create mode 100644 hw/misc/riscv_wgchecker.c
create mode 100644 hw/misc/riscv_worldguard.c
create mode 100644 include/hw/misc/riscv_worldguard.h
[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4
Posted by Jim Shu 1 month ago
This patchset implements Smwg/Smwgd/Sswg CPU extension and wgChecker
device defined in WorldGuard spec v0.4.

The WG v0.4 spec could be found here:
https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf

To enable WG in QEMU, pass "wg=on" as machine parameter to virt machine.
It enables both WG CPU CSRs to apply WID of CPU and wgCheckers on
the DRAM, FLASH, and UART to protect these resources.

This patchset contains 5 parts:

1. Commit  1: Bugfix of IOMMUMemoryRegion
2. Commit  2 ~ 3: Extend IOMMUMemoryRegion and MemTxAttr for WG support
3. Commit  4 ~ 11: Add WG global device and CPU extensions
4. Commit 12 ~ 15: Add WG checker device
5. Commit 16: Add WG support to the virt machine

Jim Shu (16):
  accel/tcg: Store section pointer in CPUTLBEntryFull
  accel/tcg: memory access from CPU will pass access_type to IOMMU
  exec: Add RISC-V WorldGuard WID to MemTxAttrs
  hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
  target/riscv: Add CPU options of WorldGuard CPU extension
  target/riscv: Add hard-coded CPU state of WG extension
  target/riscv: Add defines for WorldGuard CSRs
  target/riscv: Allow global WG config to set WG CPU callbacks
  target/riscv: Implement WorldGuard CSRs
  target/riscv: Add WID to MemTxAttrs of CPU memory transactions
  hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
  hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
  hw/misc: riscv_wgchecker: Implement wgchecker slot registers
  hw/misc: riscv_wgchecker: Implement correct block-access behavior
  hw/misc: riscv_wgchecker: Check the slot settings in translate
  hw/riscv: virt: Add WorldGuard support

 accel/tcg/cputlb.c                   |   34 +-
 docs/system/riscv/virt.rst           |   10 +
 hw/misc/Kconfig                      |    3 +
 hw/misc/meson.build                  |    1 +
 hw/misc/riscv_wgchecker.c            | 1161 ++++++++++++++++++++++++++
 hw/misc/riscv_worldguard.c           |  273 ++++++
 hw/misc/trace-events                 |    9 +
 hw/riscv/Kconfig                     |    1 +
 hw/riscv/virt.c                      |  163 +++-
 include/exec/exec-all.h              |   11 +-
 include/exec/memattrs.h              |    5 +
 include/hw/core/cpu.h                |    3 +
 include/hw/misc/riscv_worldguard.h   |  123 +++
 include/hw/riscv/virt.h              |   17 +-
 system/physmem.c                     |   16 +-
 target/alpha/helper.c                |    2 +-
 target/arm/tcg/tlb_helper.c          |    2 +-
 target/avr/helper.c                  |    2 +-
 target/cris/helper.c                 |    2 +-
 target/hppa/mem_helper.c             |    2 +-
 target/i386/tcg/sysemu/excp_helper.c |    3 +-
 target/loongarch/tcg/tlb_helper.c    |    2 +-
 target/m68k/helper.c                 |   10 +-
 target/microblaze/helper.c           |    8 +-
 target/mips/tcg/sysemu/tlb_helper.c  |    4 +-
 target/openrisc/mmu.c                |    2 +-
 target/ppc/mmu_helper.c              |    2 +-
 target/riscv/cpu.c                   |   16 +-
 target/riscv/cpu.h                   |   12 +
 target/riscv/cpu_bits.h              |    5 +
 target/riscv/cpu_cfg.h               |    5 +
 target/riscv/cpu_helper.c            |   69 +-
 target/riscv/csr.c                   |  107 +++
 target/riscv/tcg/tcg-cpu.c           |   11 +
 target/rx/cpu.c                      |    3 +-
 target/s390x/tcg/excp_helper.c       |    2 +-
 target/sh4/helper.c                  |    2 +-
 target/sparc/mmu_helper.c            |    6 +-
 target/tricore/helper.c              |    2 +-
 target/xtensa/helper.c               |    3 +-
 40 files changed, 2054 insertions(+), 60 deletions(-)
 create mode 100644 hw/misc/riscv_wgchecker.c
 create mode 100644 hw/misc/riscv_worldguard.c
 create mode 100644 include/hw/misc/riscv_worldguard.h

-- 
2.17.1