Switched to a new branch '20240612081416.29704-1-jim.shu@sifive.com'
Applying: accel/tcg: Store section pointer in CPUTLBEntryFull
Applying: accel/tcg: memory access from CPU will pass access_type to IOMMU
Applying: exec: Add RISC-V WorldGuard WID to MemTxAttrs
Applying: hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
Applying: target/riscv: Add CPU options of WorldGuard CPU extension
Applying: target/riscv: Add hard-coded CPU state of WG extension
Applying: target/riscv: Add defines for WorldGuard CSRs
Applying: target/riscv: Allow global WG config to set WG CPU callbacks
Applying: target/riscv: Implement WorldGuard CSRs
Applying: target/riscv: Add WID to MemTxAttrs of CPU memory transactions
Applying: hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
Applying: hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
Applying: hw/misc: riscv_wgchecker: Implement wgchecker slot registers
Applying: hw/misc: riscv_wgchecker: Implement correct block-access behavior
Applying: hw/misc: riscv_wgchecker: Check the slot settings in translate
Applying: hw/riscv: virt: Add WorldGuard support
Warning: Permanently added 'github.com' (ED25519) to the list of known hosts.
To github.com:patchew-project/qemu
 * [new tag]               patchew/20240612081416.29704-1-jim.shu@sifive.com -> patchew/20240612081416.29704-1-jim.shu@sifive.com