[v1] target/riscv: Allow software access to MIP SEIP

[PATCH 1/2] target/riscv: cpu: Fixup indentation

Posted by Alistair Francis 3 years, 11 months ago

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..a4120c7fb4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -709,11 +709,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
         case IRQ_S_EXT:
         case IRQ_VS_EXT:
         case IRQ_M_EXT:
-             if (kvm_enabled()) {
+            if (kvm_enabled()) {
                 kvm_riscv_set_irq(cpu, irq, level);
-             } else {
+            } else {
                 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
-             }
+            }
              break;
         default:
             g_assert_not_reached();
-- 
2.35.1

Re: [PATCH 1/2] target/riscv: cpu: Fixup indentation

Posted by Weiwei Li 3 years, 11 months ago

Hi Alistair,

It seems that there is other indentation problem in  cpu.c. Maybe they 
can be fixed together.

/* Do some ISA extension error checking */
if(cpu->cfg.ext_i&& cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
if(!cpu->cfg.ext_i&& !cpu->cfg.ext_e) {
error_setg(errp,
"Either I or E extension must be set");
return;
}

Regards,

Weiwei Li

在 2022/3/15 下午2:40, Alistair Francis 写道:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/cpu.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ff..a4120c7fb4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -709,11 +709,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>           case IRQ_S_EXT:
>           case IRQ_VS_EXT:
>           case IRQ_M_EXT:
> -             if (kvm_enabled()) {
> +            if (kvm_enabled()) {
>                   kvm_riscv_set_irq(cpu, irq, level);
> -             } else {
> +            } else {
>                   riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
> -             }
> +            }
>                break;
>           default:
>               g_assert_not_reached();

Re: [PATCH 1/2] target/riscv: cpu: Fixup indentation

Posted by Bin Meng 3 years, 11 months ago

On Tue, Mar 15, 2022 at 2:40 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>