[v1] target/riscv: Allow software access to MIP SEIP

[PATCH 0/2] target/riscv: Allow software access to MIP SEIP

Alistair Francis posted 2 patches 2 years, 1 month ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

There is a newer version of this series

target/riscv/cpu.h |  8 ++++++++
target/riscv/cpu.c | 16 ++++++++++++----
target/riscv/csr.c |  8 ++++++--
3 files changed, 26 insertions(+), 6 deletions(-)

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[PATCH 0/2] target/riscv: Allow software access to MIP SEIP

Posted by Alistair Francis 2 years, 1 month ago

From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V specification states that:
  "Supervisor-level external interrupts are made pending based on the
  logical-OR of the software-writable SEIP bit and the signal from the
  external interrupt controller."

We currently only allow either the interrupt controller or software to
set the bit, which is incorrect.

This patch removes the miclaim mask when writing MIP to allow M-mode
software to inject interrupts, even with an interrupt controller.

We then also need to keep track of which source is setting MIP_SEIP. The
final value is a OR of both, so we add two bools and use that to keep
track of the current state. This way either source can change without
loosing the correct value.

This fixes: https://gitlab.com/qemu-project/qemu/-/issues/904

Alistair Francis (2):
  target/riscv: cpu: Fixup indentation
  target/riscv: Allow software access to MIP SEIP

 target/riscv/cpu.h |  8 ++++++++
 target/riscv/cpu.c | 16 ++++++++++++----
 target/riscv/csr.c |  8 ++++++--
 3 files changed, 26 insertions(+), 6 deletions(-)

-- 
2.35.1