From nobody Mon Feb 9 05:55:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647328036517471.4588838309319; Tue, 15 Mar 2022 00:07:16 -0700 (PDT) Received: from localhost ([::1]:60800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1H1-00009W-Ev for importer@patchew.org; Tue, 15 Mar 2022 03:07:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU0r6-0004KL-9l for qemu-devel@nongnu.org; Tue, 15 Mar 2022 02:40:28 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:18518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU0r3-0008F1-LP for qemu-devel@nongnu.org; Tue, 15 Mar 2022 02:40:27 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Mar 2022 14:40:19 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 23:12:25 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 23:40:19 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KHkLB0hKGz1SVp1 for ; Mon, 14 Mar 2022 23:40:18 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ggPXJajEQbI6 for ; Mon, 14 Mar 2022 23:40:17 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.107]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KHkL64fdCz1SVp3; Mon, 14 Mar 2022 23:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1647326426; x=1678862426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uH+FnFzokSTg9hEnoprqBqYtSFmT3D4puqtd1m9I0kM=; b=ADxEidZ+YK1U0cY6mkyFKLErPIvFBp6h5bdKLr/goFD5MVDH60kqW2Fz EggzRzELoMxUUJE7Ncguz/Sfaxst9gVtyLdMUjC4ugN1zZmOoKe64ssgt SWEVL9cxO8x4NpyAn5yGn9YJrJcq3Uy1x8C4B4r0eKUwI9nChVggvFfXe eWDKLZo+mUkno+TuWzxpb8WFmnvJ1YJLMzTQVesww79wr2H7G9PYtguFB kvbZ7Ho5USyWkRAo3VYnrBcDOFi+5e5XBSKpdzNX1JeQaxCqbgygA/SPt COz3h/6jsyxkXTN3o6q/loQL0jYb6HeYNpjl28MCrZWDtw9PFMWqV6zS+ A==; X-IronPort-AV: E=Sophos;i="5.90,182,1643644800"; d="scan'208";a="196320401" IronPort-SDR: 3554KGE5p8Dk5oA8atz3aba98dR+hKKJkAiVqDU/tJ0sKVcTT+/NdGzUwj5b0Jer4oAhRnhRuN fVIM1ruwhX28CHcZlklTcyvRFhM8t1ysjCFwSnvEJGr5dpAFJEhNPHUatQLLbA9rD91wNpAP9Z M6npS6/gotF45LImwFLERzy49FA3ed+T2tyffa4uHIh2T3TV/ctDlWSGpTi8JlUiAIoSpDAuAP iyUdL2h9tHrkd4rPz0JvK30O+7gCpCF8wOpxgGS3uqcQhL1rIrgBZcQTZUoMgufoPLd7pO1wAU dMgFDTFtUspbYQfpZNyXMRov IronPort-SDR: s4m+n1hM2nhQjDnMnEydLPk3j5YqwebNvii1Dl+igzJ35Kl4boZ/sWSCJwJdfaCWPX19IsHIM9 w+J7SPMfEYGcWXnCbBx80kkG/xREU1vhrbDBYPTH2Tptbqn5+UBdgmCt7CIGYAWo5rE6Qvyav1 +C1KH6JYx4D3bXYPj4RWM07c72Lmb61SSzDFdpyvUAyhom91AJDMetzgTjCklNygPsR9IgyhZ9 AjfQO5vn509lHo++L0YYytQ30SopkGyPJDdiK2sAaeB1M/vOARF9ny0yGcaiC1kNqCGJpGEMmw BnA= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1647326417; x=1649918418; bh=uH+FnFzokSTg9hEnop rqBqYtSFmT3D4puqtd1m9I0kM=; b=h2k3Y9mkcSePcXpw+4F3rdE9b8XqZNEa1a AgzBdY/FDgwfTqUv9LWILrySFrv6glsHJuMFlNxM/kOfdEgPSKbOEpj+Tao3FZoG mkKIrOblMu0X14+uSkVmEgjZnBeSA8THsv7+o5WHVg5DHuub9XF+vjnJiu+FBPKN S83qB5OOV0LnqdZ/wrAg2BNmYr7U5uJiCdcjpdBMN2WVb5bGt1jm2SdRDBxvkIdz dFI8Ggt0QVwi5WNBwhbAhyMyltR+vKSvhvXFUpJat+xqcBTCs8c0H1j3Ee53mvR8 R2c1pIAemoZ7pd+rBH59H2vQCk/Jj6BG+gNtowxTySXkTkLZw30w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , alistair23@gmail.com, Bin Meng , bmeng.cn@gmail.com, Alistair Francis Subject: [PATCH 1/2] target/riscv: cpu: Fixup indentation Date: Tue, 15 Mar 2022 16:40:06 +1000 Message-Id: <20220315064007.3600746-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315064007.3600746-1-alistair.francis@opensource.wdc.com> References: <20220315064007.3600746-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=066bbe4b2=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647328037782100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..a4120c7fb4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -709,11 +709,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: - if (kvm_enabled()) { + if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); - } else { + } else { riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); - } + } break; default: g_assert_not_reached(); --=20 2.35.1 From nobody Mon Feb 9 05:55:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647328321669211.67531274858914; Tue, 15 Mar 2022 00:12:01 -0700 (PDT) Received: from localhost ([::1]:44868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU1Lc-0008Qv-Ih for importer@patchew.org; Tue, 15 Mar 2022 03:12:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU0r6-0004KM-9a for qemu-devel@nongnu.org; Tue, 15 Mar 2022 02:40:28 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:18524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU0r3-0008FH-LR for qemu-devel@nongnu.org; Tue, 15 Mar 2022 02:40:28 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Mar 2022 14:40:23 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 23:12:28 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2022 23:40:22 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KHkLF6CyMz1SVnx for ; Mon, 14 Mar 2022 23:40:21 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id CMiwBiddbsZp for ; Mon, 14 Mar 2022 23:40:21 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.107]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KHkLB2TdBz1Rvlx; Mon, 14 Mar 2022 23:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1647326426; x=1678862426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+E1qD2QSY6CJKqpndhQML7d+praVidtrikxaw0zJfUE=; b=K4J200e1Z9Ru6agwJvowNPIKDXqI/nWWDW/ggmiZAO5b9FtI4E//qsKs FGFlHHPjKgIF1bUn7iOAqMow4QVjjf9m31KIo86WMeCUd1Kg3hPnSwmXX xaqM4lL5421stgjH8+4Gf9+b4jIh/twNZFi/b8R5Ik01F6S5Rab25GqiZ C138ZwkWO5XWNpA/K49ZtyC2FNZMkwWw3ZU+QanP/UcPn81rd2PwqlMPU Oyps1ITGwHiazE0kORVsG05qXkmi8gpTaxGUh9hWQ7xPGPf9yex/8pU9J rCSVVtf1L2rp8CDbzpvwQLghEsQ23WP/S6tDNB6qFAu8KNd2fHBKcgm14 g==; X-IronPort-AV: E=Sophos;i="5.90,182,1643644800"; d="scan'208";a="196320406" IronPort-SDR: GfZRE40+Jw0f9LrfLvcbq/UiGXW1zXwxfwlaV/qglHhuLEH61IE5RK07nW37vL0mGTaTkBWEv0 LJLt1rAhsT+5TJiYnWXQv2b0BykjiUXQQClEKVaH2PQnaiT5rdV63qjXZh4Gh5bLK3ngn1146e LOceyX02KAQ+MAdayY5TkubyxYAp2OXbjDGNfVErFC86jvLWbZFBVYLuYOPUk76YRFbJMg+pEC Z4KDdpDtweVIdXLnuBBI6zj9KL7muAa0v+L2kZPg7kLQcA5a9t9eL/7w0w66K4WE0dz+HXRAjn yaMr1ydlmxvnWwc61XOvVSIX IronPort-SDR: U4SvdkmI8dmU/HJnuASkHLVVpHeKEsBkJAlHs+qj0MH6r/uTuwoY4ACHn6YWIgf+HRmjV+DiHP 08VKb9vExdCrU42lAXMMOazryynhb9ezspIDf1snX5odBssImbJw9G3cXRJ0dqVCwJbYBw0lyF EpquQAIKiemEY74IcuAL7f5O7ACjsf6FRF2JnjMNnCNPQfA0G961MhdJCaUjQvxlR+qMduOBUc eo0HE0iRgToPLHZlBsIABYGsLi9ONiaP+fiE5aod4RiiK6YSrh9F337hujjIlaspaZIlA+fNRk iCo= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1647326421; x=1649918422; bh=+E1qD2QSY6CJKqpndh QML7d+praVidtrikxaw0zJfUE=; b=iwPCo48cXJPo3XkE/SNzxsWaXaN2YGERAo 7at21QHc7bhi+0AfN1m+KpELeeVo9NJbg7WG+S2L7P214l9nfh3pMBVesxosUPcp atG72IndQk66dBSVDXp19ACTJ06FulngKbzJmSBQtaSQ0QdWm7Sza+hz0RNNlGQH 9q5Ei27CGNgDlVTKoM6v+VBrRbqWoOOqD0h+IuDLuTKHP7zICPFlGlYEyJVHbSZm Y1ppe4aouJ08Sh1vYIDnbHb79fh92lEVHmjru6DE3RVQrRki8E9OPLJ/1Hfl39xR YzIcWmT/qMHspxGw03xNgkmvQH0BplzI+og9uewEmvAb+9b44dGA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , alistair23@gmail.com, Bin Meng , bmeng.cn@gmail.com, Alistair Francis Subject: [PATCH 2/2] target/riscv: Allow software access to MIP SEIP Date: Tue, 15 Mar 2022 16:40:07 +1000 Message-Id: <20220315064007.3600746-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220315064007.3600746-1-alistair.francis@opensource.wdc.com> References: <20220315064007.3600746-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=066bbe4b2=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647328323586100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The RISC-V specification states that: "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller." We currently only allow either the interrupt controller or software to set the bit, which is incorrect. This patch removes the miclaim mask when writing MIP to allow M-mode software to inject interrupts, even with an interrupt controller. We then also need to keep track of which source is setting MIP_SEIP. The final value is a OR of both, so we add two bools and use that to keep track of the current state. This way either source can change without loosing the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu.c | 10 +++++++++- target/riscv/csr.c | 8 ++++++-- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..05d40f8dbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -173,6 +173,14 @@ struct CPUArchState { uint64_t mstatus; =20 uint64_t mip; + /* + * MIP contains the software writable version of SEIP ORed with the + * external interrupt value. The MIP register is always up-to-date. + * To keep track of the current source, we also save booleans of the v= alues + * here. + */ + bool external_seip; + bool software_seip; =20 uint64_t miclaim; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a4120c7fb4..0bd19e16a2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -706,7 +706,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, in= t level) case IRQ_VS_TIMER: case IRQ_M_TIMER: case IRQ_U_EXT: - case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: if (kvm_enabled()) { @@ -715,6 +714,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq, i= nt level) riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); } break; + case IRQ_S_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + env->external_seip =3D level; + riscv_cpu_update_mip(cpu, 1 << irq, + BOOL_TO_MASK(level | env->software_se= ip)); + } + break; default: g_assert_not_reached(); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0606cd0ea8..48e78cf91e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1403,10 +1403,14 @@ static RISCVException rmw_mip64(CPURISCVState *env,= int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu =3D env_archcpu(env); - /* Allow software control of delegable interrupts not claimed by hardw= are */ - uint64_t old_mip, mask =3D wr_mask & delegable_ints & ~env->miclaim; + uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + if (mask & MIP_SEIP) { + env->software_seip =3D new_val & MIP_SEIP; + } + new_val |=3D env->external_seip << IRQ_S_EXT; + if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { --=20 2.35.1