[v3] target/riscv: Allow software access to MIP SEIP

[PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP

Alistair Francis posted 2 patches 2 years, 1 month ago

Diff against v1 v2
Download series mbox

Test checkpatch passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220317061817.3856850-1-alistair.francis@opensource.wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

target/riscv/cpu.h |  8 ++++++++
target/riscv/cpu.c | 30 +++++++++++++++++++-----------
target/riscv/csr.c |  8 ++++++--
3 files changed, 33 insertions(+), 13 deletions(-)

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[PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP

Posted by Alistair Francis 2 years, 1 month ago

From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V specification states that:
  "Supervisor-level external interrupts are made pending based on the
  logical-OR of the software-writable SEIP bit and the signal from the
  external interrupt controller."

We currently only allow either the interrupt controller or software to
set the bit, which is incorrect.

This patch removes the miclaim mask when writing MIP to allow M-mode
software to inject interrupts, even with an interrupt controller.

We then also need to keep track of which source is setting MIP_SEIP. The
final value is a OR of both, so we add two bools and use that to keep
track of the current state. This way either source can change without
losing the correct value.

This fixes: https://gitlab.com/qemu-project/qemu/-/issues/904

Alistair Francis (2):
  target/riscv: cpu: Fixup indentation
  target/riscv: Allow software access to MIP SEIP

 target/riscv/cpu.h |  8 ++++++++
 target/riscv/cpu.c | 30 +++++++++++++++++++-----------
 target/riscv/csr.c |  8 ++++++--
 3 files changed, 33 insertions(+), 13 deletions(-)

-- 
2.35.1

Re: [PATCH v3 0/2] target/riscv: Allow software access to MIP SEIP

Posted by Alistair Francis 2 years, 1 month ago

On Thu, Mar 17, 2022 at 4:18 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The RISC-V specification states that:
>   "Supervisor-level external interrupts are made pending based on the
>   logical-OR of the software-writable SEIP bit and the signal from the
>   external interrupt controller."
>
> We currently only allow either the interrupt controller or software to
> set the bit, which is incorrect.
>
> This patch removes the miclaim mask when writing MIP to allow M-mode
> software to inject interrupts, even with an interrupt controller.
>
> We then also need to keep track of which source is setting MIP_SEIP. The
> final value is a OR of both, so we add two bools and use that to keep
> track of the current state. This way either source can change without
> losing the correct value.
>
> This fixes: https://gitlab.com/qemu-project/qemu/-/issues/904
>
> Alistair Francis (2):
>   target/riscv: cpu: Fixup indentation
>   target/riscv: Allow software access to MIP SEIP

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h |  8 ++++++++
>  target/riscv/cpu.c | 30 +++++++++++++++++++-----------
>  target/riscv/csr.c |  8 ++++++--
>  3 files changed, 33 insertions(+), 13 deletions(-)
>
> --
> 2.35.1
>