[v1] A collection of RISC-V cleanups and improvements

[PATCH 0/7] A collection of RISC-V cleanups and improvements

Alistair Francis posted 7 patches 2 years, 4 months ago

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Maintainers: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

There is a newer version of this series

hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
hw/riscv/microchip_pfsoc.c |   2 +-
hw/riscv/opentitan.c       |   2 +-
hw/riscv/sifive_e.c        |   2 +-
hw/riscv/sifive_u.c        |   2 +-
target/riscv/cpu.c         |   2 +-
6 files changed, 81 insertions(+), 183 deletions(-)

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[PATCH 0/7] A collection of RISC-V cleanups and improvements

Posted by Alistair Francis 2 years, 4 months ago

From: Alistair Francis <alistair.francis@wdc.com>

This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.

Alistair Francis (7):
  hw/intc: sifive_plic: Add a reset function
  hw/intc: sifive_plic: Cleanup the write function
  hw/intc: sifive_plic: Cleanup the read function
  hw/intc: sifive_plic: Cleanup remaining functions
  target/riscv: Mark the Hypervisor extension as non experimental
  target/riscv: Enable the Hypervisor extension by default
  hw/riscv: Use error_fatal for SoC realisation

 hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
 hw/riscv/microchip_pfsoc.c |   2 +-
 hw/riscv/opentitan.c       |   2 +-
 hw/riscv/sifive_e.c        |   2 +-
 hw/riscv/sifive_u.c        |   2 +-
 target/riscv/cpu.c         |   2 +-
 6 files changed, 81 insertions(+), 183 deletions(-)

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2.31.1