[v4] A collection of RISC-V cleanups and improvements

[PATCH v4 0/8] A collection of RISC-V cleanups and improvements

Alistair Francis posted 8 patches 2 years, 3 months ago

Diff against v1 v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/20220105213937.1113508-1-alistair.francis@opensource.wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

include/hw/riscv/virt.h    |   2 +-
hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
hw/riscv/microchip_pfsoc.c |   2 +-
hw/riscv/opentitan.c       |   2 +-
hw/riscv/sifive_e.c        |   2 +-
hw/riscv/sifive_u.c        |   2 +-
target/riscv/cpu.c         |   2 +-
7 files changed, 82 insertions(+), 184 deletions(-)

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[PATCH v4 0/8] A collection of RISC-V cleanups and improvements

Posted by Alistair Francis 2 years, 3 months ago

From: Alistair Francis <alistair.francis@wdc.com>

This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.

v4:
 - Resend
v3:
 - Drop some patches
 - Few small fixes from reviews
v2:
 - Add some more fixes
 - Address review comments

Alistair Francis (8):
  hw/intc: sifive_plic: Add a reset function
  hw/intc: sifive_plic: Cleanup the write function
  hw/intc: sifive_plic: Cleanup the read function
  hw/intc: sifive_plic: Cleanup remaining functions
  target/riscv: Mark the Hypervisor extension as non experimental
  target/riscv: Enable the Hypervisor extension by default
  hw/riscv: Use error_fatal for SoC realisation
  hw/riscv: virt: Allow support for 32 cores

 include/hw/riscv/virt.h    |   2 +-
 hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
 hw/riscv/microchip_pfsoc.c |   2 +-
 hw/riscv/opentitan.c       |   2 +-
 hw/riscv/sifive_e.c        |   2 +-
 hw/riscv/sifive_u.c        |   2 +-
 target/riscv/cpu.c         |   2 +-
 7 files changed, 82 insertions(+), 184 deletions(-)

-- 
2.31.1

Re: [PATCH v4 0/8] A collection of RISC-V cleanups and improvements

Posted by Alistair Francis 2 years, 3 months ago

On Thu, Jan 6, 2022 at 7:55 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> This is a few patches to cleanup some RISC-V hardware and mark the
> Hyperisor extension as non experimental.
>
> v4:
>  - Resend
> v3:
>  - Drop some patches
>  - Few small fixes from reviews
> v2:
>  - Add some more fixes
>  - Address review comments
>
> Alistair Francis (8):
>   hw/intc: sifive_plic: Add a reset function
>   hw/intc: sifive_plic: Cleanup the write function
>   hw/intc: sifive_plic: Cleanup the read function
>   hw/intc: sifive_plic: Cleanup remaining functions
>   target/riscv: Mark the Hypervisor extension as non experimental
>   target/riscv: Enable the Hypervisor extension by default
>   hw/riscv: Use error_fatal for SoC realisation
>   hw/riscv: virt: Allow support for 32 cores

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  include/hw/riscv/virt.h    |   2 +-
>  hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
>  hw/riscv/microchip_pfsoc.c |   2 +-
>  hw/riscv/opentitan.c       |   2 +-
>  hw/riscv/sifive_e.c        |   2 +-
>  hw/riscv/sifive_u.c        |   2 +-
>  target/riscv/cpu.c         |   2 +-
>  7 files changed, 82 insertions(+), 184 deletions(-)
>
> --
> 2.31.1
>
>