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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420698682100002 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 877e76877c..a9f7a1bfb0 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -355,6 +355,23 @@ static const MemoryRegionOps sifive_plic_ops =3D { } }; =20 +static void sifive_plic_reset(DeviceState *dev) +{ + SiFivePLICState *s =3D SIFIVE_PLIC(dev); + int i; + + memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources); + memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs); + memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words); + memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words); + memset(s->enable, 0, sizeof(uint32_t) * s->num_enables); + + for (i =3D 0; i < s->num_harts; i++) { + qemu_set_irq(s->m_external_irqs[i], 0); + qemu_set_irq(s->s_external_irqs[i], 0); + } +} + /* * parse PLIC hart/mode address offset config * @@ -501,6 +518,7 @@ static void sifive_plic_class_init(ObjectClass *klass, = void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D sifive_plic_reset; device_class_set_props(dc, sifive_plic_properties); dc->realize =3D sifive_plic_realize; dc->vmsd =3D &vmstate_sifive_plic; --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420857943100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 76 +++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index a9f7a1bfb0..698492ce77 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -33,6 +33,11 @@ =20 #define RISCV_DEBUG_PLIC 0 =20 +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) +{ + return addr >=3D base && addr - base < num; +} + static PLICMode char_to_mode(char c) { switch (c) { @@ -269,80 +274,53 @@ static void sifive_plic_write(void *opaque, hwaddr ad= dr, uint64_t value, { SiFivePLICState *plic =3D opaque; =20 - /* writes must be 4 byte words */ - if ((addr & 0x3) !=3D 0) { - goto err; - } - - if (addr >=3D plic->priority_base && /* 4 bytes per source */ - addr < plic->priority_base + (plic->num_sources << 2)) - { + if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; + plic->source_priority[irq] =3D value & 7; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: irq=3D%d priority=3D%d\n", - irq, plic->source_priority[irq]); - } sifive_plic_update(plic); - return; - } else if (addr >=3D plic->pending_base && /* 1 bit per source */ - addr < plic->pending_base + (plic->num_sources >> 3)) - { + } else if (addr_between(addr, plic->pending_base, + plic->num_sources >> 3)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pending write: 0x%" HWADDR_PRIx "", __func__, addr); - return; - } else if (addr >=3D plic->enable_base && /* 1 bit per source */ - addr < plic->enable_base + plic->num_addrs * plic->enable_stride) - { + } else if (addr_between(addr, plic->enable_base, + plic->num_addrs * plic->enable_stride)) { uint32_t addrid =3D (addr - plic->enable_base) / plic->enable_stri= de; uint32_t wordid =3D (addr & (plic->enable_stride - 1)) >> 2; + if (wordid < plic->bitfield_words) { plic->enable[addrid * plic->bitfield_words + wordid] =3D value; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write enable: hart%d-%c word=3D%d value=3D= %x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), wordid, - plic->enable[addrid * plic->bitfield_words + wordid]); - } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid enable write 0x%" HWADDR_PRIx "\n", + __func__, addr); } - } else if (addr >=3D plic->context_base && /* 4 bytes per reg */ - addr < plic->context_base + plic->num_addrs * plic->context_stride) - { + } else if (addr_between(addr, plic->context_base, + plic->num_addrs * plic->context_stride)) { uint32_t addrid =3D (addr - plic->context_base) / plic->context_st= ride; uint32_t contextid =3D (addr & (plic->context_stride - 1)); + if (contextid =3D=3D 0) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: hart%d-%c priority=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - plic->target_priority[addrid]); - } if (value <=3D plic->num_priorities) { plic->target_priority[addrid] =3D value; sifive_plic_update(plic); } - return; } else if (contextid =3D=3D 4) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write claim: hart%d-%c irq=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - (uint32_t)value); - } if (value < plic->num_sources) { sifive_plic_set_claimed(plic, value, false); sifive_plic_update(plic); } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid context write 0x%" HWADDR_PRIx "\n", + __func__, addr); } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); } - -err: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid register write 0x%" HWADDR_PRIx "\n", - __func__, addr); } =20 static const MemoryRegionOps sifive_plic_ops =3D { --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641420581619139.92445938726712; Wed, 5 Jan 2022 14:09:41 -0800 (PST) Received: from localhost ([::1]:32966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5ETU-0001lE-IW for importer@patchew.org; Wed, 05 Jan 2022 17:09:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5EQv-0007n3-ST for qemu-devel@nongnu.org; Wed, 05 Jan 2022 17:07:01 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:1937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5EQt-0007tH-OH for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1641418806; x=1644010807; bh=4IZx9WjGfYJOYFMc1N hfAQRWWd90/x/xUALrZMkCDMQ=; b=d3nbcVUsaa2fvkXwj3VdXN8TQ2JW+zO4Aa ktyuRJDAra29SwPTNo4I9cJW8luowucIzdNUN1umxwcwKWDaRQsMoIOxuCTJK1eC IwM87NaQYyHROf2lqkJak9zcyIq5bj9FipvE7Pg/UYRbIgdQhpw48x89FYppaKhC Xl99x3nFz7gxfvBwsX74xvZK0JKrXfH1FOtVF4HLTu0ZlfdqrKE+uFoFqgQC6VQo ZccFM5TY4qdoEk0qPwleGgfWvhUz6Rk7QzhaYSgioaIcWc56L7uF+aRP4CyCbWam 0e32pQe2R/NyN5cbnntpb6eR31Y+yuNGAxUKFqebBMrPXcyWAd9Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng Subject: [PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function Date: Thu, 6 Jan 2022 07:39:32 +1000 Message-Id: <20220105213937.1113508-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420583860100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 55 +++++++++---------------------------------- 1 file changed, 11 insertions(+), 44 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 698492ce77..44d24b3c59 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -199,70 +199,37 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr= addr, unsigned size) { SiFivePLICState *plic =3D opaque; =20 - /* writes must be 4 byte words */ - if ((addr & 0x3) !=3D 0) { - goto err; - } - - if (addr >=3D plic->priority_base && /* 4 bytes per source */ - addr < plic->priority_base + (plic->num_sources << 2)) - { + if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read priority: irq=3D%d priority=3D%d\n", - irq, plic->source_priority[irq]); - } + return plic->source_priority[irq]; - } else if (addr >=3D plic->pending_base && /* 1 bit per source */ - addr < plic->pending_base + (plic->num_sources >> 3)) - { + } else if (addr_between(addr, plic->pending_base, plic->num_sources >>= 3)) { uint32_t word =3D (addr - plic->pending_base) >> 2; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read pending: word=3D%d value=3D%d\n", - word, plic->pending[word]); - } + return plic->pending[word]; - } else if (addr >=3D plic->enable_base && /* 1 bit per source */ - addr < plic->enable_base + plic->num_addrs * plic->enable_str= ide) - { + } else if (addr_between(addr, plic->enable_base, + plic->num_addrs * plic->enable_stride)) { uint32_t addrid =3D (addr - plic->enable_base) / plic->enable_stri= de; uint32_t wordid =3D (addr & (plic->enable_stride - 1)) >> 2; + if (wordid < plic->bitfield_words) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read enable: hart%d-%c word=3D%d value=3D%= x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), wordid, - plic->enable[addrid * plic->bitfield_words + wordid]); - } return plic->enable[addrid * plic->bitfield_words + wordid]; } - } else if (addr >=3D plic->context_base && /* 1 bit per source */ - addr < plic->context_base + plic->num_addrs * plic->context_s= tride) - { + } else if (addr_between(addr, plic->context_base, + plic->num_addrs * plic->context_stride)) { uint32_t addrid =3D (addr - plic->context_base) / plic->context_st= ride; uint32_t contextid =3D (addr & (plic->context_stride - 1)); + if (contextid =3D=3D 0) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read priority: hart%d-%c priority=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - plic->target_priority[addrid]); - } return plic->target_priority[addrid]; } else if (contextid =3D=3D 4) { uint32_t value =3D sifive_plic_claim(plic, addrid); - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read claim: hart%d-%c irq=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - value); - } + sifive_plic_update(plic); return value; } } =20 -err: qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register read 0x%" HWADDR_PRIx "\n", __func__, addr); --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164141976083350.40249363664111; Wed, 5 Jan 2022 13:56:00 -0800 (PST) Received: from localhost ([::1]:37266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5EGF-00026D-LM for importer@patchew.org; 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s=dkim; t=1641418811; x=1644010812; bh=OKeVXM7n1kl3vOCkJ/ REqODiO5Ms05QqhnoF2DV6gIY=; b=WDsOAO5cz9wy8rliLV+z/nsJ9UojGhinHx MRqCqdz6hYhOEJYXvb6MlQCHOtDYmtKrjYL5WMkvpXmKWLBpr6AbNf0LDpnu8ZO9 eJj8qQYGb58Kp6ep19+l8eX9jNQpchDLlxZSnwzilKerXjuM7llc4d+JZZRLlL6w D/OmIAr/GGHk2BT4/rmg/NB9MSS8vYHLgWOr8W68TCElZX6LT1B18Mds/qeKUoDi Bo0m7ogqE60J0rqdxK+FcWKDuyfM36s6IT39wn09rImoK0E+ljOb0xHKdZdTgBtf 8g/xMvpvBJnql6OGkuSEYY/1WMsOOz5e9/Jad1dPMEvA4xAOvAsQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng Subject: [PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions Date: Thu, 6 Jan 2022 07:39:33 +1000 Message-Id: <20220105213937.1113508-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641419762629100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis We can remove the original sifive_plic_irqs_pending() function and instead just use the sifive_plic_claim() function (renamed to sifive_plic_claimed()) to determine if any interrupts are pending. This requires move the side effects outside of sifive_plic_claimed(), but as they are only invoked once that isn't a problem. We have also removed all of the old #ifdef debugging logs, so let's cleanup the last remaining debug function while we are here. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 109 +++++++++--------------------------------- 1 file changed, 22 insertions(+), 87 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 44d24b3c59..746c0f0343 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -31,8 +31,6 @@ #include "migration/vmstate.h" #include "hw/irq.h" =20 -#define RISCV_DEBUG_PLIC 0 - static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) { return addr >=3D base && addr - base < num; @@ -51,47 +49,6 @@ static PLICMode char_to_mode(char c) } } =20 -static char mode_to_char(PLICMode m) -{ - switch (m) { - case PLICMode_U: return 'U'; - case PLICMode_S: return 'S'; - case PLICMode_H: return 'H'; - case PLICMode_M: return 'M'; - default: return '?'; - } -} - -static void sifive_plic_print_state(SiFivePLICState *plic) -{ - int i; - int addrid; - - /* pending */ - qemu_log("pending : "); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->pending[i]); - } - qemu_log("\n"); - - /* pending */ - qemu_log("claimed : "); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->claimed[i]); - } - qemu_log("\n"); - - for (addrid =3D 0; addrid < plic->num_addrs; addrid++) { - qemu_log("hart%d-%c enable: ", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode)); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + = i]); - } - qemu_log("\n"); - } -} - static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t val= ue) { uint32_t old, new, cmp =3D qatomic_read(a); @@ -115,26 +72,34 @@ static void sifive_plic_set_claimed(SiFivePLICState *p= lic, int irq, bool level) atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); } =20 -static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid) +static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid) { + uint32_t max_irq =3D 0; + uint32_t max_prio =3D plic->target_priority[addrid]; int i, j; + for (i =3D 0; i < plic->bitfield_words; i++) { uint32_t pending_enabled_not_claimed =3D - (plic->pending[i] & ~plic->claimed[i]) & - plic->enable[addrid * plic->bitfield_words + i]; + (plic->pending[i] & ~plic->claimed[i]) & + plic->enable[addrid * plic->bitfield_words + i= ]; + if (!pending_enabled_not_claimed) { continue; } + for (j =3D 0; j < 32; j++) { int irq =3D (i << 5) + j; uint32_t prio =3D plic->source_priority[irq]; int enabled =3D pending_enabled_not_claimed & (1 << j); - if (enabled && prio > plic->target_priority[addrid]) { - return 1; + + if (enabled && prio > max_prio) { + max_irq =3D irq; + max_prio =3D prio; } } } - return 0; + + return max_irq; } =20 static void sifive_plic_update(SiFivePLICState *plic) @@ -145,7 +110,7 @@ static void sifive_plic_update(SiFivePLICState *plic) for (addrid =3D 0; addrid < plic->num_addrs; addrid++) { uint32_t hartid =3D plic->addr_config[addrid].hartid; PLICMode mode =3D plic->addr_config[addrid].mode; - int level =3D sifive_plic_irqs_pending(plic, addrid); + bool level =3D !!sifive_plic_claimed(plic, addrid); =20 switch (mode) { case PLICMode_M: @@ -158,41 +123,6 @@ static void sifive_plic_update(SiFivePLICState *plic) break; } } - - if (RISCV_DEBUG_PLIC) { - sifive_plic_print_state(plic); - } -} - -static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) -{ - int i, j; - uint32_t max_irq =3D 0; - uint32_t max_prio =3D plic->target_priority[addrid]; - - for (i =3D 0; i < plic->bitfield_words; i++) { - uint32_t pending_enabled_not_claimed =3D - (plic->pending[i] & ~plic->claimed[i]) & - plic->enable[addrid * plic->bitfield_words + i]; - if (!pending_enabled_not_claimed) { - continue; - } - for (j =3D 0; j < 32; j++) { - int irq =3D (i << 5) + j; - uint32_t prio =3D plic->source_priority[irq]; - int enabled =3D pending_enabled_not_claimed & (1 << j); - if (enabled && prio > max_prio) { - max_irq =3D irq; - max_prio =3D prio; - } - } - } - - if (max_irq) { - sifive_plic_set_pending(plic, max_irq, false); - sifive_plic_set_claimed(plic, max_irq, true); - } - return max_irq; } =20 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) @@ -223,10 +153,15 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr= addr, unsigned size) if (contextid =3D=3D 0) { return plic->target_priority[addrid]; } else if (contextid =3D=3D 4) { - uint32_t value =3D sifive_plic_claim(plic, addrid); + uint32_t max_irq =3D sifive_plic_claimed(plic, addrid); + + if (max_irq) { + sifive_plic_set_pending(plic, max_irq, false); + sifive_plic_set_claimed(plic, max_irq, true); + } =20 sifive_plic_update(plic); - return value; + return max_irq; } } =20 --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641420306376164.16944738006885; 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s=dkim; t=1641418818; x=1644010819; bh=ZGx1B3MgM+U6Kfsl3i EYfy3ZvGCUTB6i+cs1K5eEnAk=; b=HwTyC69yi/HyiZeCZdY6VHp/HP6oFlWV6a aaIHLUb9xQn3uMtbMwBI6crIA29NjdRu1W6zNUHUgY1WHcqvONoQgVrVU2dfX9hr 38zXA87Hvep0QiWg5Pg1xQddHPe1wUL1YL/CwIgwfRV51HJSTaOI+MU0KXppjiMP cfWLnE/AH6kPuGUBc7JkXAWS0bSIlQVxWvQXs1rnmjgbUXueENCWmLEVb9Iz+h1G ZYmvY/uQ99LnJ45EHADOrzFDfDUk9x0qUvylvJaaQfKDryW62Flk/MRqnBoP6ET9 JD2Se8VaNRiEzYxq+dcKFVOjrXZR3X9XypH5SQwqnFr0T/LNoMSQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng , Anup Patel Subject: [PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental Date: Thu, 6 Jan 2022 07:39:34 +1000 Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420307520100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The Hypervisor spec is now frozen, so remove the experimental tag. Signed-off-by: Alistair Francis Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..9ea67bedd3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,6 +627,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -645,7 +646,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1641418825; x=1644010826; bh=JNQZsgaGbrSE6vbRmN 678U1im9RKfaH2hWZaf2zYz3M=; b=U177trUKzcCiLaMPFOn5gMwR86atH9RAXZ w3AsZCbdZsXOKlp+igLN7tonl0MzqfDv1PUYEaTC3rb+PfnRXUcyGva1VmCvdv22 OpJseIyuxwG7MDeBET0UIKlHiv0YPYPUVxxl3aE/W2njxRmMUiIYZiOTG/sjTkPb lFp/qsfvLPiDj34O8BMWsqqcoWBkyscmD+XG1EmfIUidJKcID0nCI/c9TtYILNue ZFTvxAQd0SbqkzKNRtUaoJKYdYg0CHDq/PCQE+Jtv9Vdr32rlOUPfhrrvB3FfJ7C Y6BEb4oI4wtY1ph7fRM21xrkZLPs8QjRxK9LeUUc0zWJaB/EDIhQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng , Anup Patel Subject: [PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default Date: Thu, 6 Jan 2022 07:39:35 +1000 Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420694696100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Let's enable the Hypervisor extension by default. This doesn't affect named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the Hypervisor extensions by default for the virt machine. Signed-off-by: Alistair Francis Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9ea67bedd3..29749e834f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1641418832; x=1644010833; bh=qihKQJF a1ma+57SqXXU0PIiok5kIt8Hb57cmcXqJS7U=; b=gZR7IQCy7bP0E7+TkrEXOgm FLBkqjjpHc39mKYeEM3ySZymLVrxE8s1HL6iHTeAGpXi+JEUb8hzp6nGwgdr0tug GyQIRFs2q3IOJn6FeVPhugAybUVpGgmsmJC4wOrJjuD2Rj+jmoUN7nvblXdThbb7 1acSozjopqpy4mMLRhKthQ9c2Uh04xb/LXEX2YbBQ7rHkDbU6U6F30gZ/B6ghvz+ wl3r5PV/pgMSPMho2XHYvYu0FZRuvGr6YxFSTzjncBKWk/01oRzheICfysitdTaZ rWD5J3ygqTskkbUpiHX3zrGBbA9a387HqhtohAO42yarDlB/3RGEiCIqf/wpyqA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation Date: Thu, 6 Jan 2022 07:39:36 +1000 Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420961407100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis When realising the SoC use error_fatal instead of error_abort as the process can fail and report useful information to the user. Currently a user can see this: $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display= none -drive if=3Dpflash QEMU 6.1.93 monitor - type 'help' for more information (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_= u_otp.c:229: qemu-system-riscv64: OTP drive size < 16K Aborted (core dumped) Which this patch addresses Reported-by: Markus Armbruster Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Markus Armbruster Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index d1d065efbc..cafd1fc9ae 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -471,7 +471,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_MICROCHIP_PFSOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Split RAM into low and high regions using aliases to machine->ram */ mem_low_size =3D memmap[MICROCHIP_PFSOC_DRAM_LO].size; diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c531450b9f..0856c347e8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -80,7 +80,7 @@ static void opentitan_board_init(MachineState *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_IBEX_SOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_RAM].base, machine->ram); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 9b206407a6..dcb87b6cfd 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static void sifive_e_machine_init(MachineState *machine) =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_= SOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Data Tightly Integrated Memory */ memory_region_add_subregion(sys_mem, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index aa74e67889..7fbc7dea42 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -547,7 +547,7 @@ static void sifive_u_machine_init(MachineState *machine) &error_abort); object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, &error_abort); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* register RAM */ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].b= ase, --=20 2.31.1 From nobody Tue May 7 11:41:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1641420697891709.4714034237144; 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s=dkim; t=1641418839; x=1644010840; bh=SEiOHlJ j5xbKXbw7cUvBTuIDNdThltjWHQqPVs9QSEA=; b=YvOiuzaJZVqooc6jeIYe6Xu MsExGqhNUi8IJlfJ7hs5xem5dlzlHvYxKoKwbnDsrVV4mhpLYqhGxENaHIklVC/2 siIfvA0P7JMAW3Jj/9U0KZeA2vBAlrKTbxlPjhVX17aatOBTARk9/1cNeQY8g/uU Jz0hcKJHQhRf/ZmqxiP709DFkTTwEXhcUW/rtsEACBSC6myVUu3v9JTrySrxZaOO GZREx1YZUTKVrtwUtiKBFctqvOyDDnN1ToSCbNzdsfRzvtXE2W0vgDx5VeIl9DeE YxiZt3Z4BfinzKAiTisjF9HSRd83wc9cf0SltHMIrZTypPFsx2+BS86Zw9b1tFA= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Palmer Dabbelt , alistair23@gmail.com, Alistair Francis , Alistair Francis , Bin Meng , Anup Patel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores Date: Thu, 6 Jan 2022 07:39:37 +1000 Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> References: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=9978dc08b=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1641420698682100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so let's set that as the maximum for the virt board. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435 Signed-off-by: Alistair Francis Reviewed-by: Anup Patel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b8ef99f348..6e9f61ccd9 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "qom/object.h" =20 -#define VIRT_CPUS_MAX 8 +#define VIRT_CPUS_MAX 32 #define VIRT_SOCKETS_MAX 8 =20 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.31.1