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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946346223100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 877e76877c..35f097799a 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -355,6 +355,17 @@ static const MemoryRegionOps sifive_plic_ops =3D { } }; =20 +static void sifive_plic_reset(DeviceState *dev) +{ + SiFivePLICState *s =3D SIFIVE_PLIC(dev); + + memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources); + memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs); + memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words); + memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words); + memset(s->enable, 0, sizeof(uint32_t) * s->num_enables); +} + /* * parse PLIC hart/mode address offset config * @@ -501,6 +512,7 @@ static void sifive_plic_class_init(ObjectClass *klass, = void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D sifive_plic_reset; device_class_set_props(dc, sifive_plic_properties); dc->realize =3D sifive_plic_realize; dc->vmsd =3D &vmstate_sifive_plic; --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1638945803; x=1641537804; bh=Wm6huLeVSEvMGmiKKk K0H77PwZ+dV4Llc57yf7RGz7M=; b=K1bvYKOLYFxb4siX0fzhUsrOIKWskWvd9E GPPJnZanw/4NrO0riagJqY60pVpdc6jl+Pfm049+2C0wYsIraZJ21rcfiwKCUEqZ fq/tkUxmLdXTpPX/sz7fksqTafEqiUkPSLwUcHBRIhXjuxulbvKmjmnfqwONV2m/ aEM9hPByGsmmed/O+jBFnZnBesavvcK+FUHu+fF31BzHFMYownLzzEV6dtRHyEF1 U7zwkj9shdzSleHr9MQ+7xNWsL5adlc16WbZt47w1QknY//Ihf9qBnDCtI7AhQfC OoHuHOEJkXdzY9c9SH0f/wgKqswGHchBSMd3Q3XamON8M6uvQlYg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com Subject: [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function Date: Wed, 8 Dec 2021 16:42:47 +1000 Message-Id: <20211208064252.375360-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946922806100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 82 +++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 49 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 35f097799a..c1fa689868 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -33,6 +33,17 @@ =20 #define RISCV_DEBUG_PLIC 0 =20 +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) +{ + uint32_t end =3D base + num; + + if (addr >=3D base && addr < end) { + return true; + } + + return false; +} + static PLICMode char_to_mode(char c) { switch (c) { @@ -269,80 +280,53 @@ static void sifive_plic_write(void *opaque, hwaddr ad= dr, uint64_t value, { SiFivePLICState *plic =3D opaque; =20 - /* writes must be 4 byte words */ - if ((addr & 0x3) !=3D 0) { - goto err; - } - - if (addr >=3D plic->priority_base && /* 4 bytes per source */ - addr < plic->priority_base + (plic->num_sources << 2)) - { + if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; + plic->source_priority[irq] =3D value & 7; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: irq=3D%d priority=3D%d\n", - irq, plic->source_priority[irq]); - } sifive_plic_update(plic); - return; - } else if (addr >=3D plic->pending_base && /* 1 bit per source */ - addr < plic->pending_base + (plic->num_sources >> 3)) - { + } else if (addr_between(addr, plic->pending_base, + plic->num_sources >> 3)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pending write: 0x%" HWADDR_PRIx "", __func__, addr); - return; - } else if (addr >=3D plic->enable_base && /* 1 bit per source */ - addr < plic->enable_base + plic->num_addrs * plic->enable_stride) - { + } else if (addr_between(addr, plic->enable_base, + plic->num_addrs * plic->enable_stride)) { uint32_t addrid =3D (addr - plic->enable_base) / plic->enable_stri= de; uint32_t wordid =3D (addr & (plic->enable_stride - 1)) >> 2; + if (wordid < plic->bitfield_words) { plic->enable[addrid * plic->bitfield_words + wordid] =3D value; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write enable: hart%d-%c word=3D%d value=3D= %x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), wordid, - plic->enable[addrid * plic->bitfield_words + wordid]); - } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid enable write 0x%" HWADDR_PRIx "\n", + __func__, addr); } - } else if (addr >=3D plic->context_base && /* 4 bytes per reg */ - addr < plic->context_base + plic->num_addrs * plic->context_stride) - { + } else if (addr_between(addr, plic->context_base, + plic->num_addrs * plic->context_stride)) { uint32_t addrid =3D (addr - plic->context_base) / plic->context_st= ride; uint32_t contextid =3D (addr & (plic->context_stride - 1)); + if (contextid =3D=3D 0) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: hart%d-%c priority=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - plic->target_priority[addrid]); - } if (value <=3D plic->num_priorities) { plic->target_priority[addrid] =3D value; sifive_plic_update(plic); } - return; } else if (contextid =3D=3D 4) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write claim: hart%d-%c irq=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - (uint32_t)value); - } if (value < plic->num_sources) { sifive_plic_set_claimed(plic, value, false); sifive_plic_update(plic); } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid context write 0x%" HWADDR_PRIx "\n", + __func__, addr); } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); } - -err: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid register write 0x%" HWADDR_PRIx "\n", - __func__, addr); } =20 static const MemoryRegionOps sifive_plic_ops =3D { --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1638946655886758.3632907006328; Tue, 7 Dec 2021 22:57:35 -0800 (PST) Received: from localhost ([::1]:33350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1muqtS-0002bG-Pf for importer@patchew.org; Wed, 08 Dec 2021 01:57:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1muqfw-0002GF-MZ for qemu-devel@nongnu.org; Wed, 08 Dec 2021 01:43:37 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:42051) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1muqfu-0006B9-Eu for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1638945808; x=1641537809; bh=1nZXyKteUXqi1CCV0m CtgioLAXBXnj1AjAfzLFp/9tI=; b=pkquyoV1tHaPUW7Dkbs0qa7Qj1XpHgis9f FScDohRh+/BvtUZ4sJfXFr3y1PUbgISxAe/jO54c5vFw9A3TWY27bQiALr98sXCf UJHrkm3dCqRW+DhegUSgPXhpOEeMnVsUWADbWUDiKiOD+MBFWgGjq9ou1/+kDc6I 45N3tU4AAJ7p7adbZLkLH5CbIqUINr3pSn2+foCz2Z4BY8TW+klN4E54QU5Yd0Xh joGuGhfhzdpCe5GC8BWh5z+9Kvr2CrP5Ay2PlNsoR274ozbiWK9VoB1LEkwBUwCL JaNIaFyhPl1xqpn1XRanYCZDzgYoEsIxTGINpMAfgcCn9rneSjvQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com Subject: [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function Date: Wed, 8 Dec 2021 16:42:48 +1000 Message-Id: <20211208064252.375360-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946656905100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 55 +++++++++---------------------------------- 1 file changed, 11 insertions(+), 44 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index c1fa689868..7f9715a584 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -205,70 +205,37 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr= addr, unsigned size) { SiFivePLICState *plic =3D opaque; =20 - /* writes must be 4 byte words */ - if ((addr & 0x3) !=3D 0) { - goto err; - } - - if (addr >=3D plic->priority_base && /* 4 bytes per source */ - addr < plic->priority_base + (plic->num_sources << 2)) - { + if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read priority: irq=3D%d priority=3D%d\n", - irq, plic->source_priority[irq]); - } + return plic->source_priority[irq]; - } else if (addr >=3D plic->pending_base && /* 1 bit per source */ - addr < plic->pending_base + (plic->num_sources >> 3)) - { + } else if (addr_between(addr, plic->pending_base, plic->num_sources >>= 3)) { uint32_t word =3D (addr - plic->pending_base) >> 2; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read pending: word=3D%d value=3D%d\n", - word, plic->pending[word]); - } + return plic->pending[word]; - } else if (addr >=3D plic->enable_base && /* 1 bit per source */ - addr < plic->enable_base + plic->num_addrs * plic->enable_str= ide) - { + } else if (addr_between(addr, plic->enable_base, + plic->num_addrs * plic->enable_stride)) { uint32_t addrid =3D (addr - plic->enable_base) / plic->enable_stri= de; uint32_t wordid =3D (addr & (plic->enable_stride - 1)) >> 2; + if (wordid < plic->bitfield_words) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read enable: hart%d-%c word=3D%d value=3D%= x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), wordid, - plic->enable[addrid * plic->bitfield_words + wordid]); - } return plic->enable[addrid * plic->bitfield_words + wordid]; } - } else if (addr >=3D plic->context_base && /* 1 bit per source */ - addr < plic->context_base + plic->num_addrs * plic->context_s= tride) - { + } else if (addr_between(addr, plic->context_base, + plic->num_addrs * plic->context_stride)) { uint32_t addrid =3D (addr - plic->context_base) / plic->context_st= ride; uint32_t contextid =3D (addr & (plic->context_stride - 1)); + if (contextid =3D=3D 0) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read priority: hart%d-%c priority=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - plic->target_priority[addrid]); - } return plic->target_priority[addrid]; } else if (contextid =3D=3D 4) { uint32_t value =3D sifive_plic_claim(plic, addrid); - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: read claim: hart%d-%c irq=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - value); - } + sifive_plic_update(plic); return value; } } =20 -err: qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register read 0x%" HWADDR_PRIx "\n", __func__, addr); --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163894699487126.449992867857304; Tue, 7 Dec 2021 23:03:14 -0800 (PST) Received: from localhost ([::1]:39870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1muqyv-00077r-Pu for importer@patchew.org; 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s=dkim; t=1638945814; x=1641537815; bh=aCfA01cp4jNgHVFtBw XK+eDf0TJojAxCJS4r83LTGPU=; b=OYjV2KH9evfFlp33UoHnvrfEVlEuz28pjL /ITWEe+lkRkIh8R7o8HyH2RtXNcZKEkPL19ye94QSImfOrcvlS6Z/CctM8bf8V+n 8tu47vk9cmUjiAB+4d3PCHY0p7kjYJ4uLm88YqWYv2qh81sMhs5PS4mgDGQQLL9d bfld5CbwJ/z/yQ2Ka60nR+3l4WsHqRnD6LGIpTZt+iRuqu627zsT5AtSYiIicury qASjlYfBoVPErZXymcj4YypYEcc4WprCIZEauRp5GypFUqJQiFOWbTVptJC2Yvkn AyOVEc5RQJxTQ5kUaGbBSVRjMQJUShgZ0fL2y83+ETQ+b2syaDSg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com Subject: [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions Date: Wed, 8 Dec 2021 16:42:49 +1000 Message-Id: <20211208064252.375360-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946996427100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis We can remove the original sifive_plic_irqs_pending() function and instead just use the sifive_plic_claim() function (renamed to sifive_plic_claimed()) to determine if any interrupts are pending. This requires move the side effects outside of sifive_plic_claimed(), but as they are only invoked once that isn't a problem. We have also removed all of the old #ifdef debugging logs, so let's cleanup the last remaining debug function while we are here. Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 109 +++++++++--------------------------------- 1 file changed, 22 insertions(+), 87 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 7f9715a584..d9bf01b647 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -31,8 +31,6 @@ #include "migration/vmstate.h" #include "hw/irq.h" =20 -#define RISCV_DEBUG_PLIC 0 - static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) { uint32_t end =3D base + num; @@ -57,47 +55,6 @@ static PLICMode char_to_mode(char c) } } =20 -static char mode_to_char(PLICMode m) -{ - switch (m) { - case PLICMode_U: return 'U'; - case PLICMode_S: return 'S'; - case PLICMode_H: return 'H'; - case PLICMode_M: return 'M'; - default: return '?'; - } -} - -static void sifive_plic_print_state(SiFivePLICState *plic) -{ - int i; - int addrid; - - /* pending */ - qemu_log("pending : "); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->pending[i]); - } - qemu_log("\n"); - - /* pending */ - qemu_log("claimed : "); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->claimed[i]); - } - qemu_log("\n"); - - for (addrid =3D 0; addrid < plic->num_addrs; addrid++) { - qemu_log("hart%d-%c enable: ", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode)); - for (i =3D plic->bitfield_words - 1; i >=3D 0; i--) { - qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + = i]); - } - qemu_log("\n"); - } -} - static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t val= ue) { uint32_t old, new, cmp =3D qatomic_read(a); @@ -121,26 +78,34 @@ static void sifive_plic_set_claimed(SiFivePLICState *p= lic, int irq, bool level) atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); } =20 -static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid) +static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid) { + uint32_t max_irq =3D 0; + uint32_t max_prio =3D plic->target_priority[addrid]; int i, j; + for (i =3D 0; i < plic->bitfield_words; i++) { uint32_t pending_enabled_not_claimed =3D - (plic->pending[i] & ~plic->claimed[i]) & - plic->enable[addrid * plic->bitfield_words + i]; + (plic->pending[i] & ~plic->claimed[i]) & + plic->enable[addrid * plic->bitfield_words + i= ]; + if (!pending_enabled_not_claimed) { continue; } + for (j =3D 0; j < 32; j++) { int irq =3D (i << 5) + j; uint32_t prio =3D plic->source_priority[irq]; int enabled =3D pending_enabled_not_claimed & (1 << j); - if (enabled && prio > plic->target_priority[addrid]) { - return 1; + + if (enabled && prio > max_prio) { + max_irq =3D irq; + max_prio =3D prio; } } } - return 0; + + return max_irq; } =20 static void sifive_plic_update(SiFivePLICState *plic) @@ -151,7 +116,7 @@ static void sifive_plic_update(SiFivePLICState *plic) for (addrid =3D 0; addrid < plic->num_addrs; addrid++) { uint32_t hartid =3D plic->addr_config[addrid].hartid; PLICMode mode =3D plic->addr_config[addrid].mode; - int level =3D sifive_plic_irqs_pending(plic, addrid); + bool level =3D !!sifive_plic_claimed(plic, addrid); =20 switch (mode) { case PLICMode_M: @@ -164,41 +129,6 @@ static void sifive_plic_update(SiFivePLICState *plic) break; } } - - if (RISCV_DEBUG_PLIC) { - sifive_plic_print_state(plic); - } -} - -static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) -{ - int i, j; - uint32_t max_irq =3D 0; - uint32_t max_prio =3D plic->target_priority[addrid]; - - for (i =3D 0; i < plic->bitfield_words; i++) { - uint32_t pending_enabled_not_claimed =3D - (plic->pending[i] & ~plic->claimed[i]) & - plic->enable[addrid * plic->bitfield_words + i]; - if (!pending_enabled_not_claimed) { - continue; - } - for (j =3D 0; j < 32; j++) { - int irq =3D (i << 5) + j; - uint32_t prio =3D plic->source_priority[irq]; - int enabled =3D pending_enabled_not_claimed & (1 << j); - if (enabled && prio > max_prio) { - max_irq =3D irq; - max_prio =3D prio; - } - } - } - - if (max_irq) { - sifive_plic_set_pending(plic, max_irq, false); - sifive_plic_set_claimed(plic, max_irq, true); - } - return max_irq; } =20 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) @@ -229,10 +159,15 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr= addr, unsigned size) if (contextid =3D=3D 0) { return plic->target_priority[addrid]; } else if (contextid =3D=3D 4) { - uint32_t value =3D sifive_plic_claim(plic, addrid); + uint32_t max_irq =3D sifive_plic_claimed(plic, addrid); + + if (max_irq) { + sifive_plic_set_pending(plic, max_irq, false); + sifive_plic_set_claimed(plic, max_irq, true); + } =20 sifive_plic_update(plic); - return value; + return max_irq; } } =20 --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1638946592898940.9947054627804; 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s=dkim; t=1638945820; x=1641537821; bh=ayBTYXwSr3LpHDfXsa tQL6OmSGThM5dBa3wy7BLUtaE=; b=fIHOfkVT13kC52vFjXAtAFaiwbir4Ow5D1 3Jo885/ISxbbBMYPxwQAz7Ne1QrlPQz5TTHL5dhTE6DrjNJZagTXuAW4+BySwVvf C0z7T6x7q+fhz+75H82hdvewj/86M0/qAVV54y7DZJS7q+olhCAq9U+Mi19GZ8Gc bTV5BmQlMowOpaUCWwwu4XXxd5iMLieN1xfQhJUMyCx5PfoA1UOjntjUPP7YQSwu /Ci756ddpO8EMPZVidPYUTGQFdsdOQ8t/A1WonPG46x0/OoxqQljKyIdX8pvvA5u BvX4FCrG28JwCg6ZAFmbv1Cyhdvk4NR6SWmmEozWO59A+24DxTXA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com Subject: [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental Date: Wed, 8 Dec 2021 16:42:50 +1000 Message-Id: <20211208064252.375360-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946594283100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The Hypervisor spec is now frozen, so remove the experimental tag. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..1edb2771b4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -626,6 +626,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -639,7 +640,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1638945825; x=1641537826; bh=SPZIA74TJTVMJ/EW0C huA+m3vlMDh9qmBIfXrpPLqp8=; b=o7GHGcrB4mSA3F62M9UTEa6y6QUwTGSLkS gysZVzRNTvKlWzpgBARmZztpYLy1B5UAFeS3i9esoQ+AHzsY8a9Rrh1I0j/nbYWF CcgH8ji1aq5vjQwm79mLuWQsCjT8XxdA5on0OEae+oPM8EKrzw9YLoRC1PWfa2Ef xR4E4v9LzMlTZzXzuJ9UmBX57mi3KRW5vIUHAVLKTxhgotHLtafpijVep8JHJMqv osDjva35/wzTROwooWuzn6zm9g01fBjJ4DNTsGWZKupdG7KtjEaIbmX1s5o7RSsx os9ADw3YOtMlX6vd+DEa5KemZENHGDBUmihM2Xt3pqlLoZjW08IQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com Subject: [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default Date: Wed, 8 Dec 2021 16:42:51 +1000 Message-Id: <20211208064252.375360-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638946932830100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Let's enable the Hypervisor extension by default. This doesn't affect named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the Hypervisor extensions by default for the virt machine. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1edb2771b4..013a8760b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -626,7 +626,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), --=20 2.31.1 From nobody Sat May 18 10:07:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1638945831; x=1641537832; bh=VoW/APYv+/Addxn8Vl 3X/2aFIt0i7U7pteAN7/AtERQ=; b=LPyKdl/thFiYYsrqa2HsmVjGcKx8ztmdna hMgFKyibdWZp9rlfdBm82dO3PUsuGd42E+R+89lDPuloO4SCklwC0puW//rrW1Ec uCLA/H57YXK/U+8JpHwe2r1RGDgcypIlyBj1yfObHncTiYRL1G4PjFonHd7MHsI8 Zi7cAD+OqlR3dc3wBUx27r5QeJqzkZ3iUD0jMyNU0dsEyKdCfCtRS46w912mbUo0 uuylJFvKDKXz5PrpWgc73L5YOlVp5KWs2HmJoLfF8Drmb75gNY707WCcFm7rJteZ zxVTe1aJswpWMkiYzuVokPEBZ/FCCD1iC66jUISOfgNzVIHj/AfA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , alistair23@gmail.com, Alistair Francis , bmeng.cn@gmail.com, Markus Armbruster Subject: [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation Date: Wed, 8 Dec 2021 16:42:52 +1000 Message-Id: <20211208064252.375360-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> References: <20211208064252.375360-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=96943765b=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1638947374975100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis When realising the SoC use error_fatal instead of error_abort as the process can fail and report useful information to the user. Currently a user can see this: $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display= none -drive if=3Dpflash QEMU 6.1.93 monitor - type 'help' for more information (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_= u_otp.c:229: qemu-system-riscv64: OTP drive size < 16K Aborted (core dumped) Which this patch addresses Signed-off-by: Alistair Francis Reported-by: Markus Armbruster Reviewed-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 57d779fb55..f16e4d10eb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -471,7 +471,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_MICROCHIP_PFSOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Split RAM into low and high regions using aliases to machine->ram */ mem_low_size =3D memmap[MICROCHIP_PFSOC_DRAM_LO].size; diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c531450b9f..0856c347e8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -80,7 +80,7 @@ static void opentitan_board_init(MachineState *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_IBEX_SOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_RAM].base, machine->ram); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 9b206407a6..dcb87b6cfd 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static void sifive_e_machine_init(MachineState *machine) =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_= SOC); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Data Tightly Integrated Memory */ memory_region_add_subregion(sys_mem, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 589ae72a59..d576484851 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -545,7 +545,7 @@ static void sifive_u_machine_init(MachineState *machine) &error_abort); object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, &error_abort); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* register RAM */ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].b= ase, --=20 2.31.1