[v1] target/ppc: Correct some errors with real mode handling

[RFC 0/4] target/ppc: Correct some errors with real mode handling

David Gibson posted 4 patches 5 years, 10 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20200103063911.180977-1-david@gibson.dropbear.id.au

Maintainers: David Gibson <david@gibson.dropbear.id.au>

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target/ppc/cpu.h                |   7 --
target/ppc/mmu-hash64.c         | 125 ++++++++++++++------------------
target/ppc/translate_init.inc.c |  17 ++---
3 files changed, 59 insertions(+), 90 deletions(-)

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[RFC 0/4] target/ppc: Correct some errors with real mode handling

Posted by David Gibson 5 years, 10 months ago

POWER "book S" (server class) cpus have a concept of "real mode" where
MMU translation is disabled... sort of.  In fact this can mean a bunch
of slightly different things when hypervisor mode and other
considerations are present.

We had some errors in edge cases here, so clean some things up and
correct them.

David Gibson (4):
  ppc: Drop PPC_EMULATE_32BITS_HYPV stub
  ppc: Remove stub of PPC970 HID4 implementation
  target/ppc: Correct handling of real mode accesses with vhyp on hash
    MMU
  target/ppc: Introduce ppc_hash64_use_vrma() helper

 target/ppc/cpu.h                |   7 --
 target/ppc/mmu-hash64.c         | 125 ++++++++++++++------------------
 target/ppc/translate_init.inc.c |  17 ++---
 3 files changed, 59 insertions(+), 90 deletions(-)

-- 
2.24.1