From nobody Thu Nov 13 04:43:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578033820; cv=none; d=zohomail.com; s=zohoarc; b=WvlnU4D/KqtqCbzBwBFAxeASB1/8Q/+Oc9spw5m37hrfSOwL8/gU1K8naiWd2qQKOf4n46G/nSkSEE554sM6aHP7XGr0nCtaet+IFv545th5Z1Z9Gxu/h22r6xQWJJLYP9IOJec11oO/LZZFOszIhaMuj98Lj4NThYF/os8OYfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578033820; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zA6oZwUIqIDP2GocnBLBNb/kVyVYI/2L/amSkSuwd+Q=; b=EGq6n8o9zIIuVvzFJp2RfCzW1kZFIWY/5Bd3DJ3cDmU3TPW6YTYOpO15+2WD4T+xW3kRg2qcdsGiPxmXK1MpFyHVUZNL+B1wQJc7qK5ml4qybwPSsvlsG+Hl5aH+Nydt/mSjcoIOwRW2vgBcDEB/RB3aaIcFqRDc2+n8JE0jXPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1578033820778391.10708083088; Thu, 2 Jan 2020 22:43:40 -0800 (PST) Received: from localhost ([::1]:49240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGgN-0001se-JD for importer@patchew.org; Fri, 03 Jan 2020 01:43:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35835) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGcH-00056t-Dw for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inGcF-0000Jy-PO for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:25 -0500 Received: from ozlabs.org ([203.11.71.1]:34595) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inGcD-00007V-9A; Fri, 03 Jan 2020 01:39:22 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47pwH84R09z9sRd; Fri, 3 Jan 2020 17:39:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578033556; bh=TfQTmXYbC8QhW9e6z4YK15NqUFRWl/4wKLoSPI7wBfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gKvGS9D4uwFyYl8LhsOg4LtTs6g/gVQBewYe78Kzxrwwx43FhUOAOtHEo3WO6BFuk ws2ruTCYe7r2IXIH0Zj5NClZojKa1z0IL9R3/lIk22ShuaI2IgUbDA4/m7Lj4oUL/Z dW/e+76/Yoe2vMbW0rq56pVHcBlsN2mkgQ+bNY4E= From: David Gibson To: qemu-devel@nongnu.org, philmd@redhat.com, clg@kaod.org, groug@kaod.org Subject: [RFC 1/4] ppc: Drop PPC_EMULATE_32BITS_HYPV stub Date: Fri, 3 Jan 2020 17:39:08 +1100 Message-Id: <20200103063911.180977-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200103063911.180977-1-david@gibson.dropbear.id.au> References: <20200103063911.180977-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, qemu-ppc@nongnu.org, Mark Cave-Ayland , paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The only effect of the PPC_EMULATE_32BITS_HYPV define is to change how MSR_HVB is defined. This appears to be something to handle hypervisor mode for 32-bit CPUs, but there's really no other code to handle this. The MSR_THV bit, which it uses is implemented for no cpus we model. It's unlikely anyone is going to implement this any time soon, so just drop it. Signed-off-by: David Gibson --- target/ppc/cpu.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 103bfe9dc2..2de9e2fa2b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -26,8 +26,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 -/* #define PPC_EMULATE_32BITS_HYPV */ - #define TCG_GUEST_DEFAULT_MO 0 =20 #define TARGET_PAGE_BITS_64K 16 @@ -450,14 +448,9 @@ typedef struct ppc_v3_pate_t { #define MSR_HVB (1ULL << MSR_SHV) #define msr_hv msr_shv #else -#if defined(PPC_EMULATE_32BITS_HYPV) -#define MSR_HVB (1ULL << MSR_THV) -#define msr_hv msr_thv -#else #define MSR_HVB (0ULL) #define msr_hv (0) #endif -#endif =20 /* DSISR */ #define DSISR_NOPTE 0x40000000 --=20 2.24.1 From nobody Thu Nov 13 04:43:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578033702; cv=none; d=zohomail.com; s=zohoarc; b=kP7AZcZFPtwwcuFXT5wB4xbOBzQmPz2mr/D0QeWirrsEqXeonbA2p52JmHR9/T+LeJ5fFhgPSWLBo4I/UAcd1TW5XgN6j/RqMMjA6GtcqDBAdZDexWEbcrPM+Sm2gLD/ghMvuvGiVRsSOoGEQwdRwJySQY/H0jMRvO9yi1MyecU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578033702; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LYQiH0CmPicmDIuXIr/0QTS4j0m9e9vMf+6RFSbN8gs=; b=F01Q8Umpq7Ut9fJnbTpJXKDmsqsZqsI+WzjPLYKGhGAGfH///FpKc5t/qsBJb4nv1idRGqxMcXXFbueeGu1Ry2XHSOjdQCIhTPD+WXoKzmUUb3m4RfcKVqIS6h/8hyoJC6K0SleDq3uMIHe21h2+sZNFPXJbCTU/h7XBaKiOs7c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1578033701924264.3657111124178; Thu, 2 Jan 2020 22:41:41 -0800 (PST) Received: from localhost ([::1]:49214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGeS-0006vD-7R for importer@patchew.org; Fri, 03 Jan 2020 01:41:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35795) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGcH-00056r-GZ for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inGcE-0000Ih-O7 for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:24 -0500 Received: from ozlabs.org ([203.11.71.1]:60353) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inGcD-00007Y-Bm; Fri, 03 Jan 2020 01:39:22 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47pwH83FV7z9sNH; Fri, 3 Jan 2020 17:39:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578033556; bh=hKHBL40fvquvop2W00XL2m4WOhOqI+ZG7iI5VyXxM7g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cd6MaTDzfHZesWdkrzZUIw12RjTy99Kgx2OvBorgf1Snqm6ZX8UJk37oHs5Easgdg xwdkUNDdGPJVUV6zH6LTts6ZDAuaqqJEnscgAso1ut8vfgnrL9x5WobSfIz/2ynMcI mZa5bz1PqgYTAPOz6pT1QBczUxokvU03OB6imh14= From: David Gibson To: qemu-devel@nongnu.org, philmd@redhat.com, clg@kaod.org, groug@kaod.org Subject: [RFC 2/4] ppc: Remove stub of PPC970 HID4 implementation Date: Fri, 3 Jan 2020 17:39:09 +1100 Message-Id: <20200103063911.180977-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200103063911.180977-1-david@gibson.dropbear.id.au> References: <20200103063911.180977-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, qemu-ppc@nongnu.org, Mark Cave-Ayland , paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability. However, it can be (and often was) strapped into "Apple mode", where the hypervisor capabilities were disabled (essentially putting it always in hypervisor mode). That's actually the only mode of the 970 we support in qemu, and we're unlikely to change that any time soon. However, we do have a partial implementation of the 970's HID4 register which affects things only relevant for hypervisor mode. That stub is also really ugly, since it attempts to duplicate the effects of HID4 by re-encoding it into the LPCR register used in newer CPUs, but in a really confusing way. Just get rid of it. Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 28 +--------------------------- target/ppc/translate_init.inc.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 38 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da8966ccf5..a881876647 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong va= l) =20 /* Filter out bits */ switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ - if (val & 0x40) { - lpcr |=3D LPCR_LPES0; - } - if (val & 0x8000000000000000ull) { - lpcr |=3D LPCR_LPES1; - } - if (val & 0x20) { - lpcr |=3D (0x4ull << LPCR_RMLS_SHIFT); - } - if (val & 0x4000000000000000ull) { - lpcr |=3D (0x2ull << LPCR_RMLS_SHIFT); - } - if (val & 0x2000000000000000ull) { - lpcr |=3D (0x1ull << LPCR_RMLS_SHIFT); - } - env->spr[SPR_RMOR] =3D ((lpcr >> 41) & 0xffffull) << 26; - - /* - * XXX We could also write LPID from HID4 here - * but since we don't tag any translation on it - * it doesn't actually matter - * - * XXX For proper emulation of 970 we also need - * to dig HRMOR out of HID5 - */ - break; case POWERPC_MMU_2_03: /* P5p */ lpcr =3D val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | @@ -1154,6 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) } break; default: + g_assert_not_reached(); ; } env->spr[SPR_LPCR] =3D lpcr; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index d33d65dff7..436d0d5a51 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7884,25 +7884,20 @@ static void spr_write_lpcr(DisasContext *ctx, int s= prn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); } - -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn) -{ -#if defined(TARGET_PPC64) - spr_write_generic(ctx, sprn, gprn); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -#endif -} - #endif /* !defined(CONFIG_USER_ONLY) */ =20 static void gen_spr_970_lpar(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) /* Logical partitionning */ - /* PPC970: HID4 is effectively the LPCR */ + /* PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it */ spr_register(env, SPR_970_HID4, "HID4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_970_hid4, + &spr_read_generic, &spr_write_generic, 0x00000000); #endif } --=20 2.24.1 From nobody Thu Nov 13 04:43:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578033701; cv=none; d=zohomail.com; s=zohoarc; b=MvO7cy2JZqCACy4JD/3P2lmpvL14vwf5Ajlrd5H38bWeW3je/rnkgafFkX1iheTJ7aeBlgVen8UeYNr3V6NaLlTA2VQuirfYsHEpqd/tQKumshvvMKt+Y6lxIdA6lGNguYc8o7ziX8n/Vb7EFlmmQxdrNZl1lA18FWRny8P//1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578033701; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VoYelv9cJ8c0dK6dkxE5TW5n4KFpCA/vpy+OGKQPees=; b=hPtxm7TLNOHXmOXBqZYPI0Dp38OLwhfh3k80ThOV6emwRfm16OtnLxUyU5LOXBxN3SaGMjCpurGXN6Lj1tKZ6UfmZ2bUgB0qVPsjtBCk7vhLuE55cOtHmkCh5N/QC5pN9OZmNyBQeXL4zbDTp7Aeh+djDIj+ay8zh6itqCPwR9o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1578033701433277.8916123354129; Thu, 2 Jan 2020 22:41:41 -0800 (PST) Received: from localhost ([::1]:49212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGeR-0006un-IX for importer@patchew.org; Fri, 03 Jan 2020 01:41:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35948) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGcI-00056v-7S for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inGcF-0000KI-Qh for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:26 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:37863) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inGcE-00007h-9T; Fri, 03 Jan 2020 01:39:22 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47pwH85CbGz9sRW; Fri, 3 Jan 2020 17:39:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578033556; bh=UomTOzzCLUxQKFOwa15TEphgpgzlVFcF75Lx2wGRjBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ndC9MntmUy26SjABG+KbbRQ8UF4l6/C4P+jVrPRmpM2kp2LKW3Qpt9yaQAdNIUNVq D6B0/MUnkWfOYnaSqsQK99b1HLhb9Zp+nvrm+Qm8O5t52Wlz4w++6fNbO1dAoqVyNI tfJ+dq4BqRYwWdakqINwGC+kP9ZJ6feUQ5o0EzXY= From: David Gibson To: qemu-devel@nongnu.org, philmd@redhat.com, clg@kaod.org, groug@kaod.org Subject: [RFC 3/4] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU Date: Fri, 3 Jan 2020 17:39:10 +1100 Message-Id: <20200103063911.180977-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200103063911.180977-1-david@gibson.dropbear.id.au> References: <20200103063911.180977-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, qemu-ppc@nongnu.org, Mark Cave-Ayland , paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we only model the non-hypervisor-privileged parts of the cpu. Essentially we model the hypervisor's behaviour from the point of view of a guest OS, but we don't model the hypervisor's execution. In particular, in this mode, qemu's notion of target physical address is a guest physical address from the vcpu's point of view. So accesses in guest real mode don't require translation. If we were modelling the hypervisor mode, we'd need to translate the guest physical address into a host physical address. Currently, we handle this sloppily: we rely on setting up the virtual LPCR and RMOR registers so that GPAs are simply HPAs plus an offset, which we set to zero. This is already conceptually dubious, since the LPCR and RMOR registers don't exist in the non-hypervisor portion of the CPU. It gets worse with POWER9, where RMOR and LPCR[VPM0] no longer exist at all. Clean this up by explicitly handling the vhyp case. While we're there, remove some unnecessary nesting of if statements that made the logic to select the correct real mode behaviour a bit less clear than it could be. Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 60 ++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a881876647..5fabd93c92 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -789,27 +789,30 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, */ raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; =20 - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA =3D=3D GPA =3D=3D qemu guest address + */ + } else if (msr_hv || !env->has_hv_mode) { + /* In HV mode, add HRMOR if top EA bit is clear */ if (!(eaddr >> 63)) { raddr |=3D env->spr[SPR_HRMOR]; } - } else { - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { - slb =3D &env->vrma_slb; - if (slb->sps) { - goto skip_slb_search; - } - /* Not much else to do here */ + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ + slb =3D &env->vrma_slb; + if (!slb->sps) { + /* Invalid VRMA setup, machine check */ cs->exception_index =3D POWERPC_EXCP_MCHECK; env->error_code =3D 0; return 1; - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - raddr |=3D env->spr[SPR_RMOR]; - } else { - /* The access failed, generate the approriate interrupt */ + } + + goto skip_slb_search; + } else { + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >=3D env->rmls) { if (rwx =3D=3D 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -821,6 +824,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, } return 1; } + + raddr |=3D env->spr[SPR_RMOR]; } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, @@ -953,22 +958,27 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu= , target_ulong addr) /* In real mode the top 4 effective address bits are ignored */ raddr =3D addr & 0x0FFFFFFFFFFFFFFFULL; =20 - /* In HV mode, add HRMOR if top EA bit is clear */ - if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA =3D=3D GPA =3D=3D qemu guest address + */ + return raddr; + } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } - - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { return -1; } - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - return raddr | env->spr[SPR_RMOR]; } else { - return -1; + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >=3D env->rmls) { + return -1; + } + return raddr | env->spr[SPR_RMOR]; } } else { slb =3D slb_lookup(cpu, addr); --=20 2.24.1 From nobody Thu Nov 13 04:43:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578033819; cv=none; d=zohomail.com; s=zohoarc; b=CZpk56Xcvy3ioGKdb/C/rO8RSF7QgVLViGw6fNTYXEjstO+e6fY/DKecY11ecvc6iRUlutDzTlY4KOeKmKDeKTR2K4MyuA/wvMguTa/CUSIcku4n3SPaRZEhBs2oW1f1PuaMg7lyS5w1QBj11N5p86bzWTrGxj4j8xRaPNGBtk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578033819; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8k1rECMxGsyBt6WyyNXHE0lIlBNbKod7u9yaNgu4N9Q=; b=BXuZJ6EI1f90jwjoOBwk62K0IYymM1jrz1j/bGWqxPqCy6+JHUTk73au/flaazAD+t7g5pDwWZfdngMSiRufflpKQ74X/yCf1gNGKbMLzVknW/EbXiSgVsX1TXr8KL5+tTgbfWxvl4ss791AnWd/QtmEYHa7jEjTATz2oKycjmM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157803381940497.6925526788217; Thu, 2 Jan 2020 22:43:39 -0800 (PST) Received: from localhost ([::1]:49238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGgM-0001r6-Ba for importer@patchew.org; Fri, 03 Jan 2020 01:43:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35794) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inGcH-00056q-Gm for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inGcE-0000Ip-Ik for qemu-devel@nongnu.org; Fri, 03 Jan 2020 01:39:24 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:39985 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inGcD-00007y-BY; Fri, 03 Jan 2020 01:39:22 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47pwH862qkz9sRm; Fri, 3 Jan 2020 17:39:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578033556; bh=BUqhshOcWk+Swa3UXK3WA+Ekx9g6BOIPl7hkmltSymM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gnlB4P4/Qv193W8I9udTXsAVO/zpS1tvqUckof1jSvsquolEQBnIfO0J+UaIOGi4m CrXKCOD/OU6A0gfcdHB/4nyby+jS5Os/mwklIAiqDMhbLHmFaZ1L7Py0Ci93xlzGtt tJ/T7dz6jsDdtT9XKt9roeWQ5zp2y/EaCQ6BhgJ4= From: David Gibson To: qemu-devel@nongnu.org, philmd@redhat.com, clg@kaod.org, groug@kaod.org Subject: [RFC 4/4] target/ppc: Introduce ppc_hash64_use_vrma() helper Date: Fri, 3 Jan 2020 17:39:11 +1100 Message-Id: <20200103063911.180977-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200103063911.180977-1-david@gibson.dropbear.id.au> References: <20200103063911.180977-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, qemu-ppc@nongnu.org, Mark Cave-Ayland , paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When running guests under a hypervisor, the hypervisor obviously needs to be protected from guest accesses even if those are in what the guest considers real mode (translation off). The POWER hardware provides two ways of doing that: The old way has guest real mode accesses simply offset and bounds checked into host addresses. It works, but requires that a significant chunk of the guest's memory - the RMA - be physically contiguous in the host, which is pretty inconvenient. The new way, known as VRMA, has guest real mode accesses translated in roughly the normal way but with some special parameters. In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, but in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We handle that difference in behaviour in ppc_hash64_set_isi().. but not in other places that we blindly check LPCR[VPM0]. Correct those instances with a new helper to tell if we should be in VRMA mode. Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 5fabd93c92..d878180df5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -668,6 +668,19 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *= cpu, return 0; } =20 +static bool ppc_hash64_use_vrma(CPUPPCState *env) +{ + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR + * register no longer exist */ + return true; + + default: + return !!(env->spr[SPR_LPCR] & LPCR_VPM0); + } +} + static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) { CPUPPCState *env =3D &POWERPC_CPU(cs)->env; @@ -676,15 +689,7 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_t = error_code) if (msr_ir) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ - vpm =3D true; - break; - default: - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm =3D ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HISI; @@ -702,15 +707,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_t = dar, uint64_t dsisr) if (msr_dr) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ - vpm =3D true; - break; - default: - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm =3D ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HDSI; @@ -799,7 +796,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, if (!(eaddr >> 63)) { raddr |=3D env->spr[SPR_HRMOR]; } - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { @@ -967,7 +964,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, = target_ulong addr) } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { @@ -1056,8 +1053,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) slb->sps =3D NULL; =20 /* Is VRMA enabled ? */ - lpcr =3D env->spr[SPR_LPCR]; - if (!(lpcr & LPCR_VPM0)) { + if (ppc_hash64_use_vrma(env)) { return; } =20 @@ -1065,6 +1061,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) * Make one up. Mostly ignore the ESID which will not be needed * for translation */ + lpcr =3D env->spr[SPR_LPCR]; vsid =3D SLB_VSID_VRMA; vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; vsid |=3D (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); --=20 2.24.1