[Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes

Richard Henderson posted 13 patches 5 years, 1 month ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20190317090834.5552-1-richard.henderson@linaro.org
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Claudio Fontana <claudio.fontana@huawei.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, Andrzej Zaborowski <balrogg@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>, Aleksandar Rikalo <arikalo@wavecomp.com>, Stefan Weil <sw@weilnetz.de>, Richard Henderson <rth@twiddle.net>
There is a newer version of this series
tcg/aarch64/tcg-target.h     |    1 +
tcg/i386/tcg-target.h        |    1 +
tcg/ppc/tcg-target.h         |   34 +-
tcg/ppc/tcg-target.opc.h     |   11 +
tcg/tcg-op.h                 |    1 +
tcg/tcg-opc.h                |    1 +
tcg/tcg.h                    |    1 +
target/arm/translate.c       |    4 +
tcg/aarch64/tcg-target.inc.c |    5 +-
tcg/arm/tcg-target.inc.c     |    7 +-
tcg/i386/tcg-target.inc.c    |    5 +-
tcg/mips/tcg-target.inc.c    |    3 +-
tcg/ppc/tcg-target.inc.c     | 1039 ++++++++++++++++++++++++++++++++--
tcg/riscv/tcg-target.inc.c   |    5 +-
tcg/s390/tcg-target.inc.c    |    3 +-
tcg/sparc/tcg-target.inc.c   |    3 +-
tcg/tcg-op-gvec.c            |   88 +--
tcg/tcg-op-vec.c             |   60 +-
tcg/tcg.c                    |  120 ++--
tcg/tci/tcg-target.inc.c     |    3 +-
20 files changed, 1212 insertions(+), 183 deletions(-)
create mode 100644 tcg/ppc/tcg-target.opc.h
[Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes
Posted by Richard Henderson 5 years, 1 month ago
Version 2 does not require VSX, and works with just Altivec.
But the last 3 patches incrementally add Power7/8/9 instructions.

I've tested this vs aa64 risu on power7 big-endian and power9
little-endian, so all of the easy bugs are out.  ;-)


r~


Richard Henderson (13):
  tcg: Assert fixed_reg is read-only
  tcg: Return bool success from tcg_out_mov
  tcg: Support cross-class moves without instruction support
  tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
  target/arm: Fill in .opc for cmtst_op
  tcg/ppc: Initial backend support for Altivec
  tcg: Add INDEX_op_dup_mem_vec
  tcg/ppc: Implement INDEX_op_dupm_vec
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Support vector multiply
  tcg/ppc: Update vector support to v2.06
  tcg/ppc: Update vector support to v2.07
  tcg/ppc: Update vector support to v3.00

 tcg/aarch64/tcg-target.h     |    1 +
 tcg/i386/tcg-target.h        |    1 +
 tcg/ppc/tcg-target.h         |   34 +-
 tcg/ppc/tcg-target.opc.h     |   11 +
 tcg/tcg-op.h                 |    1 +
 tcg/tcg-opc.h                |    1 +
 tcg/tcg.h                    |    1 +
 target/arm/translate.c       |    4 +
 tcg/aarch64/tcg-target.inc.c |    5 +-
 tcg/arm/tcg-target.inc.c     |    7 +-
 tcg/i386/tcg-target.inc.c    |    5 +-
 tcg/mips/tcg-target.inc.c    |    3 +-
 tcg/ppc/tcg-target.inc.c     | 1039 ++++++++++++++++++++++++++++++++--
 tcg/riscv/tcg-target.inc.c   |    5 +-
 tcg/s390/tcg-target.inc.c    |    3 +-
 tcg/sparc/tcg-target.inc.c   |    3 +-
 tcg/tcg-op-gvec.c            |   88 +--
 tcg/tcg-op-vec.c             |   60 +-
 tcg/tcg.c                    |  120 ++--
 tcg/tci/tcg-target.inc.c     |    3 +-
 20 files changed, 1212 insertions(+), 183 deletions(-)
 create mode 100644 tcg/ppc/tcg-target.opc.h

-- 
2.17.2


Re: [Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes
Posted by no-reply@patchew.org 5 years, 1 month ago
Patchew URL: https://patchew.org/QEMU/20190317090834.5552-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes
Type: series
Message-id: 20190317090834.5552-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20190317090834.5552-1-richard.henderson@linaro.org -> patchew/20190317090834.5552-1-richard.henderson@linaro.org
Switched to a new branch 'test'
9e9ef28e00 tcg/ppc: Update vector support to v3.00
e805447820 tcg/ppc: Update vector support to v2.07
29a048fa5c tcg/ppc: Update vector support to v2.06
702b53e3fe tcg/ppc: Support vector multiply
2ba329a816 tcg/ppc: Support vector shift by immediate
5e65162310 tcg/ppc: Implement INDEX_op_dupm_vec
3446564d5b tcg: Add INDEX_op_dup_mem_vec
f7bd30e149 tcg/ppc: Initial backend support for Altivec
593da57da7 target/arm: Fill in .opc for cmtst_op
18026c831d tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
378fdc5169 tcg: Support cross-class moves without instruction support
b7b9445e8a tcg: Return bool success from tcg_out_mov
4a8963a14a tcg: Assert fixed_reg is read-only

=== OUTPUT BEGIN ===
1/13 Checking commit 4a8963a14ab4 (tcg: Assert fixed_reg is read-only)
WARNING: Block comments use a leading /* on a separate line
#102: FILE: tcg/tcg.c:3529:
+            /* temp value is modified, so the value kept in memory is

WARNING: Block comments use * on subsequent lines
#103: FILE: tcg/tcg.c:3530:
+            /* temp value is modified, so the value kept in memory is
+               potentially not the same */

WARNING: Block comments use a trailing */ on a separate line
#103: FILE: tcg/tcg.c:3530:
+               potentially not the same */

total: 0 errors, 3 warnings, 140 lines checked

Patch 1/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/13 Checking commit b7b9445e8a4f (tcg: Return bool success from tcg_out_mov)
3/13 Checking commit 378fdc51691e (tcg: Support cross-class moves without instruction support)
WARNING: Block comments use a leading /* on a separate line
#23: FILE: tcg/tcg.c:3372:
+                /* Cross register class move not supported.

WARNING: Block comments use * on subsequent lines
#24: FILE: tcg/tcg.c:3373:
+                /* Cross register class move not supported.
+                   Store the source register into the destination slot

WARNING: Block comments use a trailing */ on a separate line
#25: FILE: tcg/tcg.c:3374:
+                   and leave the destination temp as TEMP_VAL_MEM.  */

WARNING: Block comments use a leading /* on a separate line
#43: FILE: tcg/tcg.c:3485:
+                /* Cross register class move not supported.  Sync the

WARNING: Block comments use * on subsequent lines
#44: FILE: tcg/tcg.c:3486:
+                /* Cross register class move not supported.  Sync the
+                   temp back to its slot and load from there.  */

WARNING: Block comments use a trailing */ on a separate line
#44: FILE: tcg/tcg.c:3486:
+                   temp back to its slot and load from there.  */

WARNING: Block comments use a leading /* on a separate line
#56: FILE: tcg/tcg.c:3648:
+                        /* Cross register class move not supported.  Sync the

WARNING: Block comments use * on subsequent lines
#57: FILE: tcg/tcg.c:3649:
+                        /* Cross register class move not supported.  Sync the
+                           temp back to its slot and load from there.  */

WARNING: Block comments use a trailing */ on a separate line
#57: FILE: tcg/tcg.c:3649:
+                           temp back to its slot and load from there.  */

total: 0 errors, 9 warnings, 43 lines checked

Patch 3/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/13 Checking commit 18026c831d0e (tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded)
5/13 Checking commit 593da57da76b (target/arm: Fill in .opc for cmtst_op)
6/13 Checking commit f7bd30e149b0 (tcg/ppc: Initial backend support for Altivec)
ERROR: spaces required around that '|' (ctx:VxV)
#187: FILE: tcg/ppc/tcg-target.inc.c:327:
+#define VX4(opc)  (OPCD(4)|(opc))
                           ^

ERROR: trailing whitespace
#541: FILE: tcg/ppc/tcg-target.inc.c:2871:
+        umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 }, $

ERROR: trailing whitespace
#542: FILE: tcg/ppc/tcg-target.inc.c:2872:
+        smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 }, $

ERROR: trailing whitespace
#543: FILE: tcg/ppc/tcg-target.inc.c:2873:
+        umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 }, $

WARNING: Block comments use a leading /* on a separate line
#606: FILE: tcg/ppc/tcg-target.inc.c:2936:
+        /* Recall we use VSX integer loads, so the integer is right

WARNING: Block comments use * on subsequent lines
#607: FILE: tcg/ppc/tcg-target.inc.c:2937:
+        /* Recall we use VSX integer loads, so the integer is right
+           justified within the left (zero-index) double-word.  */

WARNING: Block comments use a trailing */ on a separate line
#607: FILE: tcg/ppc/tcg-target.inc.c:2937:
+           justified within the left (zero-index) double-word.  */

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#830: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#835: FILE: tcg/ppc/tcg-target.opc.h:1:
+/* Target-specific opcodes for host vector expansion.  These will be

WARNING: Block comments use * on subsequent lines
#836: FILE: tcg/ppc/tcg-target.opc.h:2:
+/* Target-specific opcodes for host vector expansion.  These will be
+   emitted by tcg_expand_vec_op.  For those familiar with GCC internals,

WARNING: Block comments use a trailing */ on a separate line
#837: FILE: tcg/ppc/tcg-target.opc.h:3:
+   consider these to be UNSPEC with names.  */

total: 4 errors, 7 warnings, 788 lines checked

Patch 6/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/13 Checking commit 3446564d5b9b (tcg: Add INDEX_op_dup_mem_vec)
WARNING: Block comments use a leading /* on a separate line
#65: FILE: tcg/tcg-op-gvec.c:400:
+        /* Recall that ARM SVE allows vector sizes that are not a

total: 0 errors, 1 warnings, 175 lines checked

Patch 7/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/13 Checking commit 5e6516231011 (tcg/ppc: Implement INDEX_op_dupm_vec)
9/13 Checking commit 2ba329a816a5 (tcg/ppc: Support vector shift by immediate)
10/13 Checking commit 702b53e3fee7 (tcg/ppc: Support vector multiply)
ERROR: code indent should never use tabs
#119: FILE: tcg/ppc/tcg-target.inc.c:3198:
+^Ibreak;$

total: 1 errors, 0 warnings, 177 lines checked

Patch 10/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/13 Checking commit 29a048fa5c3a (tcg/ppc: Update vector support to v2.06)
12/13 Checking commit e80544782070 (tcg/ppc: Update vector support to v2.07)
ERROR: trailing whitespace
#261: FILE: tcg/ppc/tcg-target.inc.c:3042:
+        umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, $

ERROR: trailing whitespace
#262: FILE: tcg/ppc/tcg-target.inc.c:3043:
+        smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, $

ERROR: trailing whitespace
#263: FILE: tcg/ppc/tcg-target.inc.c:3044:
+        umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, $

total: 3 errors, 0 warnings, 354 lines checked

Patch 12/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

13/13 Checking commit 9e9ef28e00ce (tcg/ppc: Update vector support to v3.00)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190317090834.5552-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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