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[PATCH v7 00/22] tcg/ppc: Add vector opcodes

Richard Henderson posted 22 patches 4 years, 6 months ago
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20190930202125.21064-1-richard.henderson@linaro.org
Maintainers: Richard Henderson <rth@twiddle.net>
tcg/ppc/tcg-target.h     |   51 +-
tcg/ppc/tcg-target.opc.h |   13 +
tcg/ppc/tcg-target.inc.c | 1118 +++++++++++++++++++++++++++++++++++---
3 files changed, 1101 insertions(+), 81 deletions(-)
create mode 100644 tcg/ppc/tcg-target.opc.h
[PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by Richard Henderson 4 years, 6 months ago 
Changes since v6:
  * The have_foo tests have been split so that VSX is not
    combined with ISA revision.
  * The power{7,8,9} patches have been split by isa extension.
  * Force the [TABC]X bits on within the VSX instruction defines,
    making the usage of the VSX insns clearer, since we have no
    additional or'ing of seemingly random bits.

Changes since v5:
  * Disable runtime altivec detection until all of the required
    opcodes are implemented.
    Because dup2 was last, that really means all of the pure altivec
    bits, so the initial patches are not bisectable in any meaningful
    sense.  I thought about reshuffling dup2 earlier, but that created
    too many conflicts and I was too lazy.
  * Rearranged the patches a little bit to make sure that each
    one actually builds, which was not the case before.
  * Folded in the fix to tcg_out_mem_long, as discussed in the
    followup within the v4 thread.

Changes since v4:
  * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into
    ten smaller patches.
  * The net result (code-wise) is not changed between former patch 1
    and ten new patches.
  * Remaining (2-7) patches from v4 are applied verbatim.
  * This means that code-wise v5 and v4 do not differ.
  * v5 is devised to help debugging, and to better organize the code.

Changes since v3:
  * Add support for bitsel, with the vsx xxsel insn.
  * Rely on the new relocation overflow handling, so
    we don't require 3 insns for a vector load.

Changes since v2:
  * Several generic tcg patches to improve dup vs dupi vs dupm.
    In particular, if a global temp (like guest r10) is not in
    a host register, we should duplicate from memory instead of
    loading to an integer register, spilling to stack, loading
    to a vector register, and then duplicating.
  * I have more confidence that 32-bit ppc host should work
    this time around.  No testing on that front yet, but I've
    unified some code sequences with 64-bit ppc host.
  * Base altivec now supports V128 only.  Moved V64 support to
    Power7 (v2.06), which has 64-bit load/store.
  * Dropped support for 64-bit vector multiply using Power8.
    The expansion was too large compared to using integer regs.

Richard Henderson (22):
  tcg/ppc: Introduce Altivec registers
  tcg/ppc: Introduce macro VX4()
  tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
  tcg/ppc: Create TCGPowerISA and have_isa
  tcg/ppc: Replace HAVE_ISA_2_06
  tcg/ppc: Replace HAVE_ISEL macro with a variable
  tcg/ppc: Enable tcg backend vector compilation
  tcg/ppc: Add support for load/store/logic/comparison
  tcg/ppc: Add support for vector maximum/minimum
  tcg/ppc: Add support for vector add/subtract
  tcg/ppc: Add support for vector saturated add/subtract
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Support vector multiply
  tcg/ppc: Support vector dup2
  tcg/ppc: Enable Altivec detection
  tcg/ppc: Update vector support for VSX
  tcg/ppc: Update vector support for v2.07 Altivec
  tcg/ppc: Update vector support for v2.07 VSX
  tcg/ppc: Update vector support for v2.07 FP
  tcg/ppc: Update vector support for v3.00 Altivec
  tcg/ppc: Update vector support for v3.00 load/store
  tcg/ppc: Update vector support for v3.00 dup/dupi

 tcg/ppc/tcg-target.h     |   51 +-
 tcg/ppc/tcg-target.opc.h |   13 +
 tcg/ppc/tcg-target.inc.c | 1118 +++++++++++++++++++++++++++++++++++---
 3 files changed, 1101 insertions(+), 81 deletions(-)
 create mode 100644 tcg/ppc/tcg-target.opc.h

-- 
2.17.1
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by no-reply@patchew.org 4 years, 6 months ago 
Patchew URL: https://patchew.org/QEMU/20190930202125.21064-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190930202125.21064-1-richard.henderson@linaro.org
Subject: [PATCH v7 00/22] tcg/ppc: Add vector opcodes

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20190930213820.29777-1-mlevitsk@redhat.com -> patchew/20190930213820.29777-1-mlevitsk@redhat.com
Switched to a new branch 'test'
478e76c tcg/ppc: Update vector support for v3.00 dup/dupi
b89afa6 tcg/ppc: Update vector support for v3.00 load/store
bce09e8 tcg/ppc: Update vector support for v3.00 Altivec
d5f2f79 tcg/ppc: Update vector support for v2.07 FP
e0fc728 tcg/ppc: Update vector support for v2.07 VSX
b1be698 tcg/ppc: Update vector support for v2.07 Altivec
5fc86b4 tcg/ppc: Update vector support for VSX
89107c6 tcg/ppc: Enable Altivec detection
b3d5636 tcg/ppc: Support vector dup2
47e0e2b tcg/ppc: Support vector multiply
1993d36 tcg/ppc: Support vector shift by immediate
cbeffa5 tcg/ppc: Add support for vector saturated add/subtract
1241ea6 tcg/ppc: Add support for vector add/subtract
f9972ad tcg/ppc: Add support for vector maximum/minimum
13da469 tcg/ppc: Add support for load/store/logic/comparison
5ff43ce tcg/ppc: Enable tcg backend vector compilation
96e0364 tcg/ppc: Replace HAVE_ISEL macro with a variable
9c0980c tcg/ppc: Replace HAVE_ISA_2_06
e3266d3 tcg/ppc: Create TCGPowerISA and have_isa
998bca4 tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
6272fbe tcg/ppc: Introduce macro VX4()
0035792 tcg/ppc: Introduce Altivec registers

=== OUTPUT BEGIN ===
1/22 Checking commit 00357923b0b1 (tcg/ppc: Introduce Altivec registers)
2/22 Checking commit 6272fbed21ab (tcg/ppc: Introduce macro VX4())
ERROR: spaces required around that '|' (ctx:VxV)
#21: FILE: tcg/ppc/tcg-target.inc.c:322:
+#define VX4(opc)  (OPCD(4)|(opc))
                           ^

total: 1 errors, 0 warnings, 7 lines checked

Patch 2/22 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/22 Checking commit 998bca481a97 (tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC())
4/22 Checking commit e3266d393526 (tcg/ppc: Create TCGPowerISA and have_isa)
5/22 Checking commit 9c0980c45e5d (tcg/ppc: Replace HAVE_ISA_2_06)
6/22 Checking commit 96e03641f26f (tcg/ppc: Replace HAVE_ISEL macro with a variable)
7/22 Checking commit 5ff43ce33249 (tcg/ppc: Enable tcg backend vector compilation)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#163: 
new file mode 100644

total: 0 errors, 1 warnings, 129 lines checked

Patch 7/22 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/22 Checking commit 13da469a4ee1 (tcg/ppc: Add support for load/store/logic/comparison)
9/22 Checking commit f9972ad57906 (tcg/ppc: Add support for vector maximum/minimum)
10/22 Checking commit 1241ea67c7b2 (tcg/ppc: Add support for vector add/subtract)
11/22 Checking commit cbeffa5f1b81 (tcg/ppc: Add support for vector saturated add/subtract)
12/22 Checking commit 1993d365c640 (tcg/ppc: Support vector shift by immediate)
13/22 Checking commit 47e0e2b46bbd (tcg/ppc: Support vector multiply)
ERROR: code indent should never use tabs
#133: FILE: tcg/ppc/tcg-target.inc.c:3217:
+^Ibreak;$

total: 1 errors, 0 warnings, 192 lines checked

Patch 13/22 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

14/22 Checking commit b3d5636c8887 (tcg/ppc: Support vector dup2)
15/22 Checking commit 89107c63bb12 (tcg/ppc: Enable Altivec detection)
16/22 Checking commit 5fc86b499068 (tcg/ppc: Update vector support for VSX)
17/22 Checking commit b1be69897458 (tcg/ppc: Update vector support for v2.07 Altivec)
18/22 Checking commit e0fc72804bd0 (tcg/ppc: Update vector support for v2.07 VSX)
19/22 Checking commit d5f2f795d0d8 (tcg/ppc: Update vector support for v2.07 FP)
20/22 Checking commit bce09e83ceff (tcg/ppc: Update vector support for v3.00 Altivec)
21/22 Checking commit b89afa6b8a8d (tcg/ppc: Update vector support for v3.00 load/store)
22/22 Checking commit 478e76cf962b (tcg/ppc: Update vector support for v3.00 dup/dupi)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190930202125.21064-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by David Gibson 4 years, 6 months ago 
Uh.. do you want me to merge this?  Probably best to CC me if you
do.. otherwise I'm likely to miss it.

On Mon, Sep 30, 2019 at 01:21:03PM -0700, Richard Henderson wrote:
> Changes since v6:
>   * The have_foo tests have been split so that VSX is not
>     combined with ISA revision.
>   * The power{7,8,9} patches have been split by isa extension.
>   * Force the [TABC]X bits on within the VSX instruction defines,
>     making the usage of the VSX insns clearer, since we have no
>     additional or'ing of seemingly random bits.
> 
> Changes since v5:
>   * Disable runtime altivec detection until all of the required
>     opcodes are implemented.
>     Because dup2 was last, that really means all of the pure altivec
>     bits, so the initial patches are not bisectable in any meaningful
>     sense.  I thought about reshuffling dup2 earlier, but that created
>     too many conflicts and I was too lazy.
>   * Rearranged the patches a little bit to make sure that each
>     one actually builds, which was not the case before.
>   * Folded in the fix to tcg_out_mem_long, as discussed in the
>     followup within the v4 thread.
> 
> Changes since v4:
>   * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into
>     ten smaller patches.
>   * The net result (code-wise) is not changed between former patch 1
>     and ten new patches.
>   * Remaining (2-7) patches from v4 are applied verbatim.
>   * This means that code-wise v5 and v4 do not differ.
>   * v5 is devised to help debugging, and to better organize the code.
> 
> Changes since v3:
>   * Add support for bitsel, with the vsx xxsel insn.
>   * Rely on the new relocation overflow handling, so
>     we don't require 3 insns for a vector load.
> 
> Changes since v2:
>   * Several generic tcg patches to improve dup vs dupi vs dupm.
>     In particular, if a global temp (like guest r10) is not in
>     a host register, we should duplicate from memory instead of
>     loading to an integer register, spilling to stack, loading
>     to a vector register, and then duplicating.
>   * I have more confidence that 32-bit ppc host should work
>     this time around.  No testing on that front yet, but I've
>     unified some code sequences with 64-bit ppc host.
>   * Base altivec now supports V128 only.  Moved V64 support to
>     Power7 (v2.06), which has 64-bit load/store.
>   * Dropped support for 64-bit vector multiply using Power8.
>     The expansion was too large compared to using integer regs.
> 
> Richard Henderson (22):
>   tcg/ppc: Introduce Altivec registers
>   tcg/ppc: Introduce macro VX4()
>   tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
>   tcg/ppc: Create TCGPowerISA and have_isa
>   tcg/ppc: Replace HAVE_ISA_2_06
>   tcg/ppc: Replace HAVE_ISEL macro with a variable
>   tcg/ppc: Enable tcg backend vector compilation
>   tcg/ppc: Add support for load/store/logic/comparison
>   tcg/ppc: Add support for vector maximum/minimum
>   tcg/ppc: Add support for vector add/subtract
>   tcg/ppc: Add support for vector saturated add/subtract
>   tcg/ppc: Support vector shift by immediate
>   tcg/ppc: Support vector multiply
>   tcg/ppc: Support vector dup2
>   tcg/ppc: Enable Altivec detection
>   tcg/ppc: Update vector support for VSX
>   tcg/ppc: Update vector support for v2.07 Altivec
>   tcg/ppc: Update vector support for v2.07 VSX
>   tcg/ppc: Update vector support for v2.07 FP
>   tcg/ppc: Update vector support for v3.00 Altivec
>   tcg/ppc: Update vector support for v3.00 load/store
>   tcg/ppc: Update vector support for v3.00 dup/dupi
> 
>  tcg/ppc/tcg-target.h     |   51 +-
>  tcg/ppc/tcg-target.opc.h |   13 +
>  tcg/ppc/tcg-target.inc.c | 1118 +++++++++++++++++++++++++++++++++++---
>  3 files changed, 1101 insertions(+), 81 deletions(-)
>  create mode 100644 tcg/ppc/tcg-target.opc.h
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by Richard Henderson 4 years, 6 months ago 
On 10/13/19 5:25 PM, David Gibson wrote:
> 
> Uh.. do you want me to merge this?  Probably best to CC me if you
> do.. otherwise I'm likely to miss it.

No thanks, it's now in a tcg pull request.


r~
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by David Gibson 4 years, 6 months ago 
On Sun, Oct 13, 2019 at 08:31:59PM -0700, Richard Henderson wrote:
> On 10/13/19 5:25 PM, David Gibson wrote:
> > 
> > Uh.. do you want me to merge this?  Probably best to CC me if you
> > do.. otherwise I'm likely to miss it.
> 
> No thanks, it's now in a tcg pull request.

Ok, cool.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by Mark Cave-Ayland 4 years, 6 months ago 
On 30/09/2019 21:21, Richard Henderson wrote:

> Changes since v6:
>   * The have_foo tests have been split so that VSX is not
>     combined with ISA revision.
>   * The power{7,8,9} patches have been split by isa extension.
>   * Force the [TABC]X bits on within the VSX instruction defines,
>     making the usage of the VSX insns clearer, since we have no
>     additional or'ing of seemingly random bits.
> 
> Changes since v5:
>   * Disable runtime altivec detection until all of the required
>     opcodes are implemented.
>     Because dup2 was last, that really means all of the pure altivec
>     bits, so the initial patches are not bisectable in any meaningful
>     sense.  I thought about reshuffling dup2 earlier, but that created
>     too many conflicts and I was too lazy.
>   * Rearranged the patches a little bit to make sure that each
>     one actually builds, which was not the case before.
>   * Folded in the fix to tcg_out_mem_long, as discussed in the
>     followup within the v4 thread.
> 
> Changes since v4:
>   * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into
>     ten smaller patches.
>   * The net result (code-wise) is not changed between former patch 1
>     and ten new patches.
>   * Remaining (2-7) patches from v4 are applied verbatim.
>   * This means that code-wise v5 and v4 do not differ.
>   * v5 is devised to help debugging, and to better organize the code.
> 
> Changes since v3:
>   * Add support for bitsel, with the vsx xxsel insn.
>   * Rely on the new relocation overflow handling, so
>     we don't require 3 insns for a vector load.
> 
> Changes since v2:
>   * Several generic tcg patches to improve dup vs dupi vs dupm.
>     In particular, if a global temp (like guest r10) is not in
>     a host register, we should duplicate from memory instead of
>     loading to an integer register, spilling to stack, loading
>     to a vector register, and then duplicating.
>   * I have more confidence that 32-bit ppc host should work
>     this time around.  No testing on that front yet, but I've
>     unified some code sequences with 64-bit ppc host.
>   * Base altivec now supports V128 only.  Moved V64 support to
>     Power7 (v2.06), which has 64-bit load/store.
>   * Dropped support for 64-bit vector multiply using Power8.
>     The expansion was too large compared to using integer regs.
> 
> Richard Henderson (22):
>   tcg/ppc: Introduce Altivec registers
>   tcg/ppc: Introduce macro VX4()
>   tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
>   tcg/ppc: Create TCGPowerISA and have_isa
>   tcg/ppc: Replace HAVE_ISA_2_06
>   tcg/ppc: Replace HAVE_ISEL macro with a variable
>   tcg/ppc: Enable tcg backend vector compilation
>   tcg/ppc: Add support for load/store/logic/comparison
>   tcg/ppc: Add support for vector maximum/minimum
>   tcg/ppc: Add support for vector add/subtract
>   tcg/ppc: Add support for vector saturated add/subtract
>   tcg/ppc: Support vector shift by immediate
>   tcg/ppc: Support vector multiply
>   tcg/ppc: Support vector dup2
>   tcg/ppc: Enable Altivec detection
>   tcg/ppc: Update vector support for VSX
>   tcg/ppc: Update vector support for v2.07 Altivec
>   tcg/ppc: Update vector support for v2.07 VSX
>   tcg/ppc: Update vector support for v2.07 FP
>   tcg/ppc: Update vector support for v3.00 Altivec
>   tcg/ppc: Update vector support for v3.00 load/store
>   tcg/ppc: Update vector support for v3.00 dup/dupi
> 
>  tcg/ppc/tcg-target.h     |   51 +-
>  tcg/ppc/tcg-target.opc.h |   13 +
>  tcg/ppc/tcg-target.inc.c | 1118 +++++++++++++++++++++++++++++++++++---
>  3 files changed, 1101 insertions(+), 81 deletions(-)
>  create mode 100644 tcg/ppc/tcg-target.opc.h

I've just tried this version with my OS X/MacOS 9 CDROM boot tests and it looks good
here: no crashes or visible artefacts AFAICT:

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (PPC32)


ATB,

Mark.
Re: [PATCH v7 00/22] tcg/ppc: Add vector opcodes
Posted by Aleksandar Markovic 4 years, 6 months ago 
01.10.2019. 23.21, "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk> је
написао/ла:
>
> On 30/09/2019 21:21, Richard Henderson wrote:
>
> > Changes since v6:
> >   * The have_foo tests have been split so that VSX is not
> >     combined with ISA revision.
> >   * The power{7,8,9} patches have been split by isa extension.
> >   * Force the [TABC]X bits on within the VSX instruction defines,
> >     making the usage of the VSX insns clearer, since we have no
> >     additional or'ing of seemingly random bits.
> >
> > Changes since v5:
> >   * Disable runtime altivec detection until all of the required
> >     opcodes are implemented.
> >     Because dup2 was last, that really means all of the pure altivec
> >     bits, so the initial patches are not bisectable in any meaningful
> >     sense.  I thought about reshuffling dup2 earlier, but that created
> >     too many conflicts and I was too lazy.
> >   * Rearranged the patches a little bit to make sure that each
> >     one actually builds, which was not the case before.
> >   * Folded in the fix to tcg_out_mem_long, as discussed in the
> >     followup within the v4 thread.
> >
> > Changes since v4:
> >   * Patch 1, "tcg/ppc: Introduce Altivec registers", is divided into
> >     ten smaller patches.
> >   * The net result (code-wise) is not changed between former patch 1
> >     and ten new patches.
> >   * Remaining (2-7) patches from v4 are applied verbatim.
> >   * This means that code-wise v5 and v4 do not differ.
> >   * v5 is devised to help debugging, and to better organize the code.
> >
> > Changes since v3:
> >   * Add support for bitsel, with the vsx xxsel insn.
> >   * Rely on the new relocation overflow handling, so
> >     we don't require 3 insns for a vector load.
> >
> > Changes since v2:
> >   * Several generic tcg patches to improve dup vs dupi vs dupm.
> >     In particular, if a global temp (like guest r10) is not in
> >     a host register, we should duplicate from memory instead of
> >     loading to an integer register, spilling to stack, loading
> >     to a vector register, and then duplicating.
> >   * I have more confidence that 32-bit ppc host should work
> >     this time around.  No testing on that front yet, but I've
> >     unified some code sequences with 64-bit ppc host.
> >   * Base altivec now supports V128 only.  Moved V64 support to
> >     Power7 (v2.06), which has 64-bit load/store.
> >   * Dropped support for 64-bit vector multiply using Power8.
> >     The expansion was too large compared to using integer regs.
> >
> > Richard Henderson (22):
> >   tcg/ppc: Introduce Altivec registers
> >   tcg/ppc: Introduce macro VX4()
> >   tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
> >   tcg/ppc: Create TCGPowerISA and have_isa
> >   tcg/ppc: Replace HAVE_ISA_2_06
> >   tcg/ppc: Replace HAVE_ISEL macro with a variable
> >   tcg/ppc: Enable tcg backend vector compilation
> >   tcg/ppc: Add support for load/store/logic/comparison
> >   tcg/ppc: Add support for vector maximum/minimum
> >   tcg/ppc: Add support for vector add/subtract
> >   tcg/ppc: Add support for vector saturated add/subtract
> >   tcg/ppc: Support vector shift by immediate
> >   tcg/ppc: Support vector multiply
> >   tcg/ppc: Support vector dup2
> >   tcg/ppc: Enable Altivec detection
> >   tcg/ppc: Update vector support for VSX
> >   tcg/ppc: Update vector support for v2.07 Altivec
> >   tcg/ppc: Update vector support for v2.07 VSX
> >   tcg/ppc: Update vector support for v2.07 FP
> >   tcg/ppc: Update vector support for v3.00 Altivec
> >   tcg/ppc: Update vector support for v3.00 load/store
> >   tcg/ppc: Update vector support for v3.00 dup/dupi
> >
> >  tcg/ppc/tcg-target.h     |   51 +-
> >  tcg/ppc/tcg-target.opc.h |   13 +
> >  tcg/ppc/tcg-target.inc.c | 1118 +++++++++++++++++++++++++++++++++++---
> >  3 files changed, 1101 insertions(+), 81 deletions(-)
> >  create mode 100644 tcg/ppc/tcg-target.opc.h
>
> I've just tried this version with my OS X/MacOS 9 CDROM boot tests and it
looks good
> here: no crashes or visible artefacts AFAICT:
>
> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (PPC32)
>
>
>

For all patches in this series:

Reviewed-by: Aleksandar Markovic
<amarkovic@wavecomp.com>

Patchew 2.1-devel-0870f84

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