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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fFksXPcg68larzzGnM7YN3sIm2Zb50QlLmNUoBTpHpM=; b=EJQs8GvHZeXOa7fKejsFy8q3k8WVUUi7ShXqpg69P0+4Wl0ap/0wMkBcUIt8T/KiKH cVUqCytYqLBiyVm4S034txVSitzaF/2xkp+vuKgC2olbmexcm5J1HA5Dw8zpFutMl462 XNl97eF6Lg0eGoUXFzS2oNJI8xZX5aA+Ec8ScBJOWOgWIyu/TJN2shQtDeSeSCtmFuVT DfX6RQdo4EFtzVEm8tqOPQgQEDtQF6xSLFxiOQ/fhMzHXTxJiQmOZOlVFbMsar6nPp0G /wpnyL0bLFRQm/wnk/4BHCq407cHh5DVDaMv2XLg9A8gLznEF/hNHlZJIhZH5ZGFP1Ej seIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fFksXPcg68larzzGnM7YN3sIm2Zb50QlLmNUoBTpHpM=; b=VsKvM3NHrC/JopzMRTFbUsEsb8BoDLFS88I4ZageDnUp08BcF6awBdKDKgsetg1Ziu ASecYZX88klyw+Cuxl0rNhkpkKSNmV34YEn4gqZRdcJBn8Nlg/sEalsPzWB2eUO2tO/H oHZuKhuHIhPNNUTkMDfnouXrdZexTuf/ZhSOYg+zBg52t6u5KnlK0L/XFY5H+f6IiBn8 1n42iyGZ8tWwqLObtFnfiopMzzc0r9Lp5kv7zIr5R4mpD9PEVYE72vBFw6oPV+X+JwMy DtUiJK8wjutZht1YD6iwyfPchxG6AspzJg3KWYz/I86l3nMYe7IJEHti0tCrTgkp/9oq F4DA== X-Gm-Message-State: APjAAAW2TFO7ax/zfFWz1KZZJ7pCzFa30g99T03afZcvHzdY/Wlojp2G pUSFwDdEbUjtRmjxbIbtho8jV+A73Tk= X-Google-Smtp-Source: APXvYqxDlwQK7J7t8S4Hzj5XgrkSVxRD5sUwnmpdOiCwX48vCT0VOz5XJ6K1hKmXzwfZJBVZjsbssg== X-Received: by 2002:a17:90a:8087:: with SMTP id c7mr1203547pjn.56.1569874888258; Mon, 30 Sep 2019 13:21:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 01/22] tcg/ppc: Introduce Altivec registers Date: Mon, 30 Sep 2019 13:21:04 -0700 Message-Id: <20190930202125.21064-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Altivec supports 32 128-bit vector registers, whose names are by convention v0 through v31. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 11 ++++- tcg/ppc/tcg-target.inc.c | 88 +++++++++++++++++++++++++--------------- 2 files changed, 65 insertions(+), 34 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 7627fb62d3..690fa744e1 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -31,7 +31,7 @@ # define TCG_TARGET_REG_BITS 32 #endif =20 -#define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 =20 @@ -45,6 +45,15 @@ typedef enum { TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27, TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31, =20 + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + TCG_REG_CALL_STACK =3D TCG_REG_R1, TCG_AREG0 =3D TCG_REG_R27 } TCGReg; diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 815edac077..9d678c3bf1 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -42,6 +42,9 @@ # define TCG_REG_TMP1 TCG_REG_R12 #endif =20 +#define TCG_VEC_TMP1 TCG_REG_V0 +#define TCG_VEC_TMP2 TCG_REG_V1 + #define TCG_REG_TB TCG_REG_R31 #define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64) =20 @@ -72,39 +75,15 @@ bool have_isa_3_00; #endif =20 #ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "r0", - "r1", - "r2", - "r3", - "r4", - "r5", - "r6", - "r7", - "r8", - "r9", - "r10", - "r11", - "r12", - "r13", - "r14", - "r15", - "r16", - "r17", - "r18", - "r19", - "r20", - "r21", - "r22", - "r23", - "r24", - "r25", - "r26", - "r27", - "r28", - "r29", - "r30", - "r31" +static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", }; #endif =20 @@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R5, TCG_REG_R4, TCG_REG_R3, + + /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ + TCG_REG_V2, /* call clobbered, vectors */ + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V8, + TCG_REG_V9, + TCG_REG_V10, + TCG_REG_V11, + TCG_REG_V12, + TCG_REG_V13, + TCG_REG_V14, + TCG_REG_V15, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, }; =20 static const int tcg_target_call_iarg_regs[] =3D { @@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); =20 + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ @@ -2818,6 +2838,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ } --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Sg+1BNlUkd68yFef7dmXTKIYOAnPSKke44HmN/xx+JE=; b=A7wTKz4tl834f4hFOk1ubqMUF86wjT2ZJQ0ZYUpwo83HXup3na1a16G4SqKHdMdnGr EvaCl+o3KCGuKSnJlq7RNuipIbxNcgyoFL2iUPi1PWGjY6xcZlQfttOQTfi7LA0TqyU5 qiI90S7yNpLgBsgJtjIMz+pU6IR777kCC5PRvItN2Wg1Hih3aVv4778Y4cKGiihwwvj/ Q9+B1wNCXFd9N1RVXDvXiVzuLETQl8aq6BxfHn6f9bxk5q3FA5KVKMEL3e4WNfdV002c OwxA/ibcgvOiSTHGXXihrEvHRG8SQ6+5BWWMYhf150Jn/HuCIHGakNL+ZID0nCzcfnTg MqxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Sg+1BNlUkd68yFef7dmXTKIYOAnPSKke44HmN/xx+JE=; b=E1cyz9NUKA1KSSCW5yjbdvq1Li0uzRwT1e7cMjMtuogaGvsz7418mOzLXaBjCzQmJG 9YtyYtNsPuWOv3vZbdJ7i+xtKFXouBPmMyxVK42SJch0V3pyxWUbOVNpSN9Vr4N5lpNk 4JLKZ8se+Oa0DXCAp+OCgh9pF/Ck7lxh4Qc+VBIdbmGSzjsQuwZJ/xdRjDsOPRadiPw2 4KlbKKU8F60IQejbRUU8dijiTJKjOnJyuURcTfTjbRKWT6b+ktWL6e4c4IwpjGhFh3DS eXvvnyWphgDJtcvKDsEzLXcikHDbA1WFnYLMye9VT8ffX510J7lZ8ytHoxPXYgwlU1TH /3ew== X-Gm-Message-State: APjAAAW/ilrUYSbqQaE6vu2GN4cGrvrTOG/CGaUSCJoDdJnst49XgFpj Dz4+/MA9NfF7xQNlfxUCwDbWlqUjdR4= X-Google-Smtp-Source: APXvYqx1gmmv76p0r+gt3gWTbqiZTplCVCKMKRIf7HmYMlkGgIsoNPLP0/1iamTK8XCP03lSIGil2Q== X-Received: by 2002:a62:870a:: with SMTP id i10mr23240492pfe.259.1569874889503; Mon, 30 Sep 2019 13:21:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 02/22] tcg/ppc: Introduce macro VX4() Date: Mon, 30 Sep 2019 13:21:05 -0700 Message-Id: <20190930202125.21064-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce macro VX4() used for encoding Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 9d678c3bf1..8dc5455600 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -319,6 +319,7 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) +#define VX4(opc) (OPCD(4)|(opc)) =20 #define B OPCD( 18) #define BC OPCD( 16) --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875209; cv=none; d=zoho.com; s=zohoarc; b=bN9P3VTiuTMnFNToIxr2Ay+KyY07MMRCc/2WcKsRSDvWOKw0XLh2s7raxfM3JJVVLq2bI5mkBt+uVsToCPHe5qOXRusKUUQwO3qFX/WoLmuf4KQJzA0cfkaPIIJfU3FIF7IjAGO1jM+UzetqfygORgfCnaspSwkP7I1S8MvJtOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875209; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sv1evknX8Peb+IcRUAjULJcxFSuTafe0C9v6FcPm5oM=; b=EnW1fEBs646WW1F5EBxtGtteq4Hpkh0ZcEaBeFIKoMUGlYaeE7WDblW05adTxR/V+/I9QPr1uTDNp60W3Fz3BJt4vI56HmQeDxWkZbZaWTlDE+4uersGapXuCQ5u5lwrsfydscZJJFxRJFnKZrhIrs8fO7VBAKHeJQac+rqUmGE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875209611970.769017122681; Mon, 30 Sep 2019 13:26:49 -0700 (PDT) Received: from localhost ([::1]:56870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Fs-0001a8-20 for importer@patchew.org; Mon, 30 Sep 2019 16:26:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2An-0004T6-4S for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Am-0005X8-5M for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:33 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:41262) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Am-0005Wm-0O for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:32 -0400 Received: by mail-pg1-x52d.google.com with SMTP id s1so7980907pgv.8 for ; Mon, 30 Sep 2019 13:21:31 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::52d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce macros VRT(), VRA(), VRB(), VRC() used for encoding elements of Altivec instructions. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8dc5455600..4aad5d2b36 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -473,6 +473,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define MB64(b) ((b)<<5) #define FXM(b) (1 << (19 - (b))) =20 +#define VRT(r) (((r) & 31) << 21) +#define VRA(r) (((r) & 31) << 16) +#define VRB(r) (((r) & 31) << 11) +#define VRC(r) (((r) & 31) << 6) + #define LK 1 =20 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875301; cv=none; d=zoho.com; s=zohoarc; b=lvo9ODFz3vGNRG4CIzALZXX849FWa26yB5qU+HOLS2lhcaON9U9lpLAQfNCu6QuMdL1Tsq+wfVbcOT3SUnTyCi0cHk3Pb/Bk8u4Uod9NASYSTm8zid8iAHVv9Cp+IMA1iKCf2GRR2mgwb5Rw6kEUIJb7+E4LRPjVNaZ3uuroy0c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875301; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=SzVKSOWxR21GxNNFEkqthMF5+mItMVvGCPcgyomd1W8=; b=BH9fVVu02oZBq8nqEd5MRtSoF83JFfPq+iNCBqcdaVGn10iyynio/z4Q9/pLuzhs1Y/YWWEKg3jkwUzLgqxEtNs8wI6GZ36S9hCCs4HjkiN7BcgrcUytxOe2dJ4dd6wWyQgVRcgdvpZwUxjmXgSRk/CFReUIVvXhu9VEKWryhNY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875301368124.3518840746923; Mon, 30 Sep 2019 13:28:21 -0700 (PDT) Received: from localhost ([::1]:56878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2HH-0002oW-KF for importer@patchew.org; Mon, 30 Sep 2019 16:28:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44799) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Ao-0004Tl-FP for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2An-0005Xl-Cw for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:34 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45822) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2An-0005XQ-7y for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:33 -0400 Received: by mail-pf1-x443.google.com with SMTP id y72so6213688pfb.12 for ; Mon, 30 Sep 2019 13:21:33 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SzVKSOWxR21GxNNFEkqthMF5+mItMVvGCPcgyomd1W8=; b=n66VoN6cw0yROmNJ5enKQ27M2KM/lOpS6VNk+kp0zTmsO+0HsSmpYTqdJreYWJouaY 062M5CIwN+wO484xLl7kFoqSqlBy4FvwepbAPQEkluxmTtWiSPz03jliNTmtEoRx9dSL VfeiqdahDCUscFjediuiisD2dPH/iOx6Ep8fc6tMUfArvQw46T+WObFKabg4ektSftBf pKv2pg13HrpJeI/Pq9lzlVaYklx0wyq2WufKRFLkZMOlmwPnz0skpzAWG0Fm+hZKfDGC zh5r/KwKqbWO8zved0EDwwPhiDnhCvJAXafvzZw5EHgNlO/TEhN3aXW8AZ5ePOQgadxf ArWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SzVKSOWxR21GxNNFEkqthMF5+mItMVvGCPcgyomd1W8=; b=fmXFhJ0LIwEcf4Cx4T8m4DrbINETEA1iNLVkr292EhLxAOHUtbyUOovaf19Cgc76ex jg2TVECYbiHJT704vbqHI9Iod9mRlx2rX39f4fIQU5mf19iqYQeawnffjpb+oF8nM7Wz VnWPE5sH1P8NpsRvm9gHY4RkRYHJfqer+n8G2z6PHcLth7on/ERmyvXIaYTbk/Xw1pEQ iEuLf4TCTkDFrqYMtIA5tYAu/MasqrdV5d8S0GziU0NPU5VFfZd+kiRtoSjf7lsH0reN MPpKFiRxBwyqpvouTcrQxk/VQO1K20FdjLBL6dU2hexHxSbsjCiAV16nugB/oNbDM6tt ncVQ== X-Gm-Message-State: APjAAAXEJxaf+mWL2DgBBMjV54gOJg1AeqsKvhN/O3pfr6TRsxNWY4bC 0rVJ+lI4kS2IUie2xUldWZy0K/N/hwM= X-Google-Smtp-Source: APXvYqxeuf1a26uPfaxcr82rLtiLAyhcaCPrP7nYJp/IU0EmRail94sa+CSX4RqqqDp+EpEdkayh9Q== X-Received: by 2002:a63:f74c:: with SMTP id f12mr23969606pgk.316.1569874891912; Mon, 30 Sep 2019 13:21:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 04/22] tcg/ppc: Create TCGPowerISA and have_isa Date: Mon, 30 Sep 2019 13:21:07 -0700 Message-Id: <20190930202125.21064-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce an enum to hold base < 2.06 < 3.00. Use macros to preserve the existing have_isa_2_06 and have_isa_3_00 predicates. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 12 ++++++++++-- tcg/ppc/tcg-target.inc.c | 8 ++++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 690fa744e1..35ba8693fa 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -58,8 +58,16 @@ typedef enum { TCG_AREG0 =3D TCG_REG_R27 } TCGReg; =20 -extern bool have_isa_2_06; -extern bool have_isa_3_00; +typedef enum { + tcg_isa_base, + tcg_isa_2_06, + tcg_isa_3_00, +} TCGPowerISA; + +extern TCGPowerISA have_isa; + +#define have_isa_2_06 (have_isa >=3D tcg_isa_2_06) +#define have_isa_3_00 (have_isa >=3D tcg_isa_3_00) =20 /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 4aad5d2b36..0bfaef9418 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -64,8 +64,7 @@ =20 static tcg_insn_unit *tb_ret_addr; =20 -bool have_isa_2_06; -bool have_isa_3_00; +TCGPowerISA have_isa; =20 #define HAVE_ISA_2_06 have_isa_2_06 #define HAVE_ISEL have_isa_2_06 @@ -2787,12 +2786,13 @@ static void tcg_target_init(TCGContext *s) unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); unsigned long hwcap2 =3D qemu_getauxval(AT_HWCAP2); =20 + have_isa =3D tcg_isa_base; if (hwcap & PPC_FEATURE_ARCH_2_06) { - have_isa_2_06 =3D true; + have_isa =3D tcg_isa_2_06; } #ifdef PPC_FEATURE2_ARCH_3_00 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { - have_isa_3_00 =3D true; + have_isa =3D tcg_isa_3_00; } #endif =20 --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875570; cv=none; d=zoho.com; s=zohoarc; b=ht1ujwRwaVpacyU8Zp6NlpfQ3fALfkCZXlwB0wu3ahK8W1HKYRSIuEyd8Jhl0uVoLFyNwaI2nvj+fu2lctMhSy3AnROdcBw0LzqvdjZqYTTCRjQf4KlB84kIZ9LA3FPL7XS5TFh0FkLtheezzpfaCtE4yAhVxBm1djqQgUw7mjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875570; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ayS7etBvRQ1aOAX0++NO+mX/JVf00a4W7Sr0mxG2vlw=; b=VkLIzqkFqmbnh64XnPZh4iP3QWIP6/L4iNhrRx7ISHjTQThBU86Viq/biykKnf5x1AN4VWgkB2n5Nnik7VTnyO1bAjwsoASw23CuFdEf0KSM+btDDwRZCRhVx8dN8yaDjOcQpITluECDqYzDhT5quZOAoCnfK73lPajN8N2B2J8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875570965132.5413799798945; Mon, 30 Sep 2019 13:32:50 -0700 (PDT) Received: from localhost ([::1]:56940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Lh-0006Oi-5N for importer@patchew.org; Mon, 30 Sep 2019 16:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44814) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Ap-0004Vn-Un for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Ao-0005YM-QJ for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:35 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38698) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Ao-0005Y6-LE for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:34 -0400 Received: by mail-pl1-x643.google.com with SMTP id w8so3870101plq.5 for ; Mon, 30 Sep 2019 13:21:34 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ayS7etBvRQ1aOAX0++NO+mX/JVf00a4W7Sr0mxG2vlw=; b=bGT4ryWcaWfGY2IQ6U/ewaIJWUPKhuhcOKMeIZNaY89lg2pkXvbSVCf2keGE1sXut5 QrPUceuXVnN+SrwDFOeBKwcfRLY+XJ5WAp+UZjYvX9qtPaGb7xKhy9GXslZa647f7EOp W3DyZS0lmpDyYPtewbfkW872SEQNtPbOzdjSQjPHYZt+sNcx+zYSqQXKO4lY49QV1VHF CEW60AwcpwzH0AQP5efMUXo+AfkGxWE+lnyCgFu7jK5l0icmtfE6EVpysdk68chQgQPK E5Rkvv/BZ2A25LjvNmm+0vlBvrpXB9czM4RB3O/9D3MstVc5IoFhY9jDFgJyYDu9zoVK Yeow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ayS7etBvRQ1aOAX0++NO+mX/JVf00a4W7Sr0mxG2vlw=; b=cnPU0qCNGGWveqrH6r8EHGLWJI3dIPItRMUQm1TB7P81JToRrRxliF00Xr5kCj+GiZ bMNIjqvXIZg/DZGtF+1QXX0nUDg4Y0TkgpKFaxVWCP2vlp3FEiohCSrNzeH7cp8ipnIm yXMmvs6o//FjXpCA+AjmGUznZj61OV9iQa8HcpkSyezz6velMvZ0Z8fFgRz7PyAtbetz troXjmZg5jUDEHRoIUmxH9YjyIFWx9BulAFnI0qMSJAYAnaA1MmXsSgUhiUfoRQ3HcjH PP5yaEZmxdzp5Y8JIYjIYwsNC/mi0CacNGY3OOtjjnAeozITXCWqihh4QbVzxbHJcH5c ijUw== X-Gm-Message-State: APjAAAUCWi4YfthM+n+dAHZHmqXQTgrN0sgig+PP0nRZGOR0LWuylQNz EcwKDRq/8e+pV4rRJWi2VHexolyTJIc= X-Google-Smtp-Source: APXvYqwQ5gLpswUC7AuLLWIa1odwhbZJzrevEyEN35ZeZwQtgCrIyFzrnb3W/icPkomvD5Hx6A+p5Q== X-Received: by 2002:a17:902:fe16:: with SMTP id g22mr21874668plj.246.1569874893137; Mon, 30 Sep 2019 13:21:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 05/22] tcg/ppc: Replace HAVE_ISA_2_06 Date: Mon, 30 Sep 2019 13:21:08 -0700 Message-Id: <20190930202125.21064-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is identical to have_isa_2_06, so replace it. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 0bfaef9418..7cb0002c14 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -66,7 +66,6 @@ static tcg_insn_unit *tb_ret_addr; =20 TCGPowerISA have_isa; =20 -#define HAVE_ISA_2_06 have_isa_2_06 #define HAVE_ISEL have_isa_2_06 =20 #ifndef CONFIG_SOFTMMU @@ -1797,7 +1796,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) } } else { uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; - if (!HAVE_ISA_2_06 && insn =3D=3D LDBRX) { + if (!have_isa_2_06 && insn =3D=3D LDBRX) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); @@ -1869,7 +1868,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) } } else { uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; - if (!HAVE_ISA_2_06 && insn =3D=3D STDBRX) { + if (!have_isa_2_06 && insn =3D=3D STDBRX) { tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); tcg_out_shri64(s, TCG_REG_R0, datalo, 32); --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875047; cv=none; d=zoho.com; s=zohoarc; b=jugZaI9vX2v8egbb9a2tkSs6o88hCqz/qwkdKfc8FiUk8KY4dheRglnhAX7xC0LtZe3rHWbzVS+4dRNGJ7Z7T++xPMnlZrMMgISLG0U3XQ09/OrU2YWD5N1xKQZOqcD1ZKTBHEHgmdJy4K5eE3WYn1cgCgqKAMgcB80k5NpNCIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875047; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jt4e+35BxFKMSgr66A8AIeO8Hu+tEBevMhkRfs63fGs=; b=O/H1S7fGmiYH8WsT7C+1/CCFc1HG7M9vuTn9kOS6xcIIMZ4Wy3jRmgTNi5QMqayhpIdy2R/wcfNbxOM83eY7QxifXc8rU7S5X/hM0oXew2ZtF83X3QSh+dIJg8BO6U459UaahUjYnwuPBLcMiERh4tnpX9E7JJdAOfLCgZesKFA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875047579394.6739322984412; Mon, 30 Sep 2019 13:24:07 -0700 (PDT) Received: from localhost ([::1]:56820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2DF-0006Y5-AV for importer@patchew.org; Mon, 30 Sep 2019 16:24:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44825) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Aq-0004XN-UE for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Ap-0005Yt-R4 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:36 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:33409) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Ap-0005Ya-LJ for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:35 -0400 Received: by mail-pf1-x443.google.com with SMTP id q10so6246138pfl.0 for ; Mon, 30 Sep 2019 13:21:35 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jt4e+35BxFKMSgr66A8AIeO8Hu+tEBevMhkRfs63fGs=; b=V5IRgzIzQiJ+TOivhjXM/0za0vmdkwluRjlCZS+5xKof3oAfj8jxuug4ARSi7KOFFB m9nDrQJeceH5WRmqAbCgWzmSF5VvKpQd9m4u7/d8uRmruuNMCFlV6J/jAX6pyGyTnqPw aN2y5n4oHdJokCwWh4TUBMjcqChEsxTb6zoiyzhzUqFwUMVTB++/SDNlTzKYxK9Z2fAd 38aji2WhXdoMvF5NOPH5kO0JF+KkJ4JwlgHQZgxDFsMPjn0VKq3Pxpe6rmm88InZMI7/ hjuVOICzBrV3bH6T8WIevKSM6koKLupQ5ZWaELOduzoR2Csq0bbwaKkVxs37+/0NE5ay PtMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jt4e+35BxFKMSgr66A8AIeO8Hu+tEBevMhkRfs63fGs=; b=BIeYCPVcTKPtU21VI3SEeBQDZ7kI1RIHIpTSca8In6qCdBgw9VppcIO9bRVMb2enfI y+7Jw6O8Z8n3TRDFGD19iQ/8FFiiVCgO+dl4kEX/CGJRmyK5bTkWRaVzI9DaDiDZww7S /PeANbakTwfNzd9hAUTxnwA7QqS+HsASdIwhYxca/HxgzUzjkMCUIshvg/GJiM5y5U7B T+oAqD305FpBJMrOqOUWVOSp/hYgXRzJl+fmVVxEuuqbBGzY9xxRgxRL+wDlAEvpu+TD MK8BgCkpTZDaDPCrcvn5MTsqBd1vXMlAGsM3LE2Ix0ePmBHhIiTSsFiVjHsxUwNbNTlY T2Uw== X-Gm-Message-State: APjAAAU52y1hOwDuXJ1QXLjozugnJuZAnKpO196o2ZJ6mHxwp7ap4W+t vanlqO8yKfYaE06HfPoiGR8LIf67rYc= X-Google-Smtp-Source: APXvYqzY6Lr0cxKejNrYddVagjQe7B3OO5veAdr/F5kCxfa59pWAJcF+iI/8QMiLVSFJMtzYmYdOgg== X-Received: by 2002:a63:9d04:: with SMTP id i4mr13621881pgd.254.1569874894373; Mon, 30 Sep 2019 13:21:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 06/22] tcg/ppc: Replace HAVE_ISEL macro with a variable Date: Mon, 30 Sep 2019 13:21:09 -0700 Message-Id: <20190930202125.21064-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previously we've been hard-coding knowledge that Power7 has ISEL, but it was an optional instruction before that. Use the AT_HWCAP2 bit, when present, to properly determine support. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 7cb0002c14..db28ae7eb1 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -65,8 +65,7 @@ static tcg_insn_unit *tb_ret_addr; =20 TCGPowerISA have_isa; - -#define HAVE_ISEL have_isa_2_06 +static bool have_isel; =20 #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG 30 @@ -1100,7 +1099,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, /* If we have ISEL, we can implement everything with 3 or 4 insns. All other cases below are also at least 3 insns, so speed up the code generator by not considering them and always using ISEL. */ - if (HAVE_ISEL) { + if (have_isel) { int isel, tab; =20 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); @@ -1203,7 +1202,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType ty= pe, TCGCond cond, =20 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); =20 - if (HAVE_ISEL) { + if (have_isel) { int isel =3D tcg_to_isel[cond]; =20 /* Swap the V operands if the operation indicates inversion. */ @@ -1247,7 +1246,7 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type= , uint32_t opc, } else { tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); /* Note that the only other valid constant for a2 is 0. */ - if (HAVE_ISEL) { + if (have_isel) { tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0= )); } else if (!const_a2 && a0 =3D=3D a2) { @@ -2795,6 +2794,14 @@ static void tcg_target_init(TCGContext *s) } #endif =20 +#ifdef PPC_FEATURE2_HAS_ISEL + /* Prefer explicit instruction from the kernel. */ + have_isel =3D (hwcap2 & PPC_FEATURE2_HAS_ISEL) !=3D 0; +#else + /* Fall back to knowing Power7 (2.06) has ISEL. */ + have_isel =3D have_isa_2_06; +#endif + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875826; cv=none; d=zoho.com; s=zohoarc; b=Phizq+HBe66PP912VfKYeE8YnNNJkgMKqRY1/unddI/RhvrHtRI2sTB9Zw0FWsot/gWjJO7aYVgpUGXIe8jxTNihxLeGgkB1YYpwOLPfb7rUBRhAdbaXLBYKnn9q3Fq4xbtLJImvF+/IHEULppVN1n783S/qrfEcFg/dynXTWKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875826; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=cUZEWTE4U4KpIW+xnrtwY7u98g/gstklJJokJGVCFWE=; b=BxWqUPu1J1xSGvWPNbEvoBiKhAULIklMK5JoF50lcdQTkuhZUt1p67lNzG5aP8/BIJilfHaWICScGkcwU6J9VmsBvAhUDA6R9ueVoynx2diItzwweWDXFl1ZeypbJYP3hIyn6k6QPcS+CJEJ6CSLPD3lvuVTlX6QZrqzAG/SqtY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875826084137.66981655155996; Mon, 30 Sep 2019 13:37:06 -0700 (PDT) Received: from localhost ([::1]:56994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Po-0001qg-Km for importer@patchew.org; Mon, 30 Sep 2019 16:37:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44845) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2At-0004aR-4h for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Ar-0005Zj-DX for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:38 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:46528) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Ar-0005ZG-7w for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:37 -0400 Received: by mail-pl1-x644.google.com with SMTP id q24so4320964plr.13 for ; Mon, 30 Sep 2019 13:21:37 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cUZEWTE4U4KpIW+xnrtwY7u98g/gstklJJokJGVCFWE=; b=b15LL7FF4SglNB9JVskcgU6cvyNZTeUy7Z9CenEI9mvKmafJDD+lXVIyOKK47ZpnQn F1wpMpxloizfwzBLkmoZvqwxjTtwtIvvjJkyJzvVeVciV8m7iQOE95ssX7T5tyjXCR0s QSF8vBz186haENi4vJI7K3QT+wOkJ2GTusztnxxEIAfMjxmtqRIgQnBk8OGTf7ZPP5Ta 4HiAeqvkyyCawTZ6V0JIPFFlthVQbsOvnSJPUkaB9WPd/eKCKa/tZJPRrudXKkaDhwl9 Zg6l8gTZac/aShqW4uDQsgwxnfTF7+p64scJWme8I8cKvtuqWWEMXAfZxsCEUOuw8htt +i+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cUZEWTE4U4KpIW+xnrtwY7u98g/gstklJJokJGVCFWE=; b=lqkfT1xT1rpFa/hlj3+i1+ms3+QDNYySRPYXftXbqBMLsNwy3dUyXepnNeFJwGz6mO UM347/SUeVOUBd6yTByrEDhB2/DGqvh7G1FOBwykww9PLDHEMzkaYlOTT64AXlO1P6Lm RGp72RRvJUrqK/4COHZ85sCHXtRtiQLbFnEVDSNxu7fRTZK4bzAEI6w95BJb/tzs8bHC 0GgOj5dYOBWQCljLGYtHElJmzS1bGedTaRGFa9Y6rkEJ5TZ4R9V4HRrl46nCYpH8YuA8 R0G55ECrARFzs6ysrPqsfjiTbyfSnK6QP1g1MszAgcbtYyLJULuLWzLZwqcPri4OIyWG QlKg== X-Gm-Message-State: APjAAAW8g2nVrWtlPHipF4gfhXPQyfNCVxgJ7p/tPF/wSQq2UQ6sIwoc iPgbA1KgPC0MO0QQnhzBUdElwkpTMY0= X-Google-Smtp-Source: APXvYqyXtRv4vcscwWQe54l12s68ViPIEtlm67H+J4+q8aOOm9x294hgTTe3LJsJYVJmnalNhUFWLw== X-Received: by 2002:a17:902:b092:: with SMTP id p18mr8539437plr.224.1569874895828; Mon, 30 Sep 2019 13:21:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 07/22] tcg/ppc: Enable tcg backend vector compilation Date: Mon, 30 Sep 2019 13:21:10 -0700 Message-Id: <20190930202125.21064-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce all of the flags required to enable tcg backend vector support, and a runtime flag to indicate the host supports Altivec instructions. For now, do not actually set have_isa_altivec to true, because we have not yet added all of the code to actually generate all of the required insns. However, we must define these flags in order to disable ifndefs that create stub versions of the functions added here. The change to tcg_out_movi works around a buglet in tcg.c wherein if we do not define tcg_out_dupi_vec we get a declared but not defined Werror, but if we only declare it we get a defined but not used Werror. We need to this change to tcg_out_movi eventually anyway, so it's no biggie. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 25 ++++++++++++++++ tcg/ppc/tcg-target.opc.h | 5 ++++ tcg/ppc/tcg-target.inc.c | 62 ++++++++++++++++++++++++++++++++++++++-- 3 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 tcg/ppc/tcg-target.opc.h diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 35ba8693fa..498e950f0c 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -65,6 +65,7 @@ typedef enum { } TCGPowerISA; =20 extern TCGPowerISA have_isa; +extern bool have_altivec; =20 #define have_isa_2_06 (have_isa >=3D tcg_isa_2_06) #define have_isa_3_00 (have_isa >=3D tcg_isa_3_00) @@ -143,6 +144,30 @@ extern TCGPowerISA have_isa; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +/* + * While technically Altivec could support V64, it has no 64-bit store + * instruction and substituting two 32-bit stores makes the generated + * code quite large. + */ +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v128 have_altivec +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_cmp_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h new file mode 100644 index 0000000000..fa680dd6a0 --- /dev/null +++ b/tcg/ppc/tcg-target.opc.h @@ -0,0 +1,5 @@ +/* + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index db28ae7eb1..c7ce0f923c 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -66,6 +66,7 @@ static tcg_insn_unit *tb_ret_addr; =20 TCGPowerISA have_isa; static bool have_isel; +bool have_altivec; =20 #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG 30 @@ -714,10 +715,31 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, } } =20 -static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long val) { - tcg_out_movi_int(s, type, ret, arg, false); + g_assert_not_reached(); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(ret < TCG_REG_V0); + tcg_out_movi_int(s, type, ret, arg, false); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D TCG_REG_V0); + tcg_out_dupi_vec(s, type, ret, arg); + break; + + default: + g_assert_not_reached(); + } } =20 static bool mask_operand(uint32_t c, int *mb, int *me) @@ -2602,6 +2624,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,= const TCGArg *args, } } =20 +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg out, TCGReg base, intptr_t offset) +{ + g_assert_not_reached(); +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + g_assert_not_reached(); +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; @@ -2804,6 +2856,10 @@ static void tcg_target_init(TCGContext *s) =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; + if (have_altivec) { + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xffffffff00000000ull; + } =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/PLU6T5my1e1kiKHn0wtK0KhqIRR0BaWzUa/dW2GFko=; b=b4dA416s2VOwi+kS9o6O0XrUekjBCRyaNzf4uXbQDfzgeyJDDYzETikiVDujPeAFcG kK/C2kmNVqbZTkcirFPTYgR8KNojQ3Hh6dZ6NDzNoTyR/ENaO81qHNgN5dgOyCcJXJhe bE3QaJPmEhBnwPxrvsD/YBQCmlwTXafiJO28gICqdWbIByu48+tUWRB0mrvGLVGCosMO OnLJwE4vEd0yS6kOaCr8FdASQIQ1lamfDN8orLyhR43udQMVkZS57JWxnlqGojVCOERc Ym0Mu1d8Q1IhgFwORSJvAkVcf//D833v1DgPOH9sIFtWQa1axRZtuqUVtlvf30X5y3Es LJdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/PLU6T5my1e1kiKHn0wtK0KhqIRR0BaWzUa/dW2GFko=; b=ebktyb+uMU8fjte0gQANLBiSnm2oxCN9QONteja2eFyAfZ7Q7jMbHBUhvz/yjhQpc3 VN6ie9xXBkB/X68VBK4cSEMw3ZzxpQ/VIW12D2aCEjUhMqJVSU8dN/GI86ZWZMIgeau8 In2p86PJHHwURqRhUCESFeq9uH9vNwKRINP0iN+DfV+503g+2nZg0OAEt0ucKYsGRFJ3 3V+c705ddtBeZjdbmdngNkEoqu/TAInMIufrSdd/tQ6M5f9FogrNJG6VWem7SyS6SEKy fwvSW4fd6iufC7bqXfO+0t8BNQ2aoSzkX/VkBmsjPBaFxJCwVRhWPBa3tJEFaB+jHdgP pQ0g== X-Gm-Message-State: APjAAAWpCX+maY1kg96kMeTtIry1isAVjb6LJU95/wJeCCjHVoenwUe9 tE10gsM62otcHQ+rJsVzSlYsVROSXak= X-Google-Smtp-Source: APXvYqw750LpQWH3vpLLy6atjZo0TB3FVC2We7f90TXFAQ5/1UfUnYMQTp1VUOnnF4h0bbsfreVvGQ== X-Received: by 2002:a63:6bc5:: with SMTP id g188mr7726156pgc.315.1569874897117; Mon, 30 Sep 2019 13:21:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 08/22] tcg/ppc: Add support for load/store/logic/comparison Date: Mon, 30 Sep 2019 13:21:11 -0700 Message-Id: <20190930202125.21064-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add various bits and peaces related mostly to load and store operations. In that context, logic, compare, and splat Altivec instructions are used, and, therefore, the support for emitting them is included in this patch too. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 6 +- tcg/ppc/tcg-target.inc.c | 472 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 442 insertions(+), 36 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 498e950f0c..a0e59a5074 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -153,15 +153,15 @@ extern bool have_altivec; #define TCG_TARGET_HAS_v128 have_altivec #define TCG_TARGET_HAS_v256 0 =20 -#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 #define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_cmp_vec 0 +#define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c7ce0f923c..1a8d7dc925 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -230,6 +230,10 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffff; break; + case 'v': + ct->ct |=3D TCG_CT_REG; + ct->u.regs =3D 0xffffffff00000000ull; + break; case 'L': /* qemu_ld constraint */ ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffff; @@ -459,6 +463,39 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, =20 #define NOP ORI /* ori 0,0,0 */ =20 +#define LVX XO31(103) +#define LVEBX XO31(7) +#define LVEHX XO31(39) +#define LVEWX XO31(71) + +#define STVX XO31(231) +#define STVEWX XO31(199) + +#define VCMPEQUB VX4(6) +#define VCMPEQUH VX4(70) +#define VCMPEQUW VX4(134) +#define VCMPGTSB VX4(774) +#define VCMPGTSH VX4(838) +#define VCMPGTSW VX4(902) +#define VCMPGTUB VX4(518) +#define VCMPGTUH VX4(582) +#define VCMPGTUW VX4(646) + +#define VAND VX4(1028) +#define VANDC VX4(1092) +#define VNOR VX4(1284) +#define VOR VX4(1156) +#define VXOR VX4(1220) + +#define VSPLTB VX4(524) +#define VSPLTH VX4(588) +#define VSPLTW VX4(652) +#define VSPLTISB VX4(780) +#define VSPLTISH VX4(844) +#define VSPLTISW VX4(908) + +#define VSLDOI VX4(44) + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -532,6 +569,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, intptr_t value, intptr_t addend) { tcg_insn_unit *target; + int16_t lo; + int32_t hi; =20 value +=3D addend; target =3D (tcg_insn_unit *)value; @@ -553,6 +592,20 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, } *code_ptr =3D (*code_ptr & ~0xfffc) | (value & 0xfffc); break; + case R_PPC_ADDR32: + /* + * We are abusing this relocation type. Again, this points to + * a pair of insns, lis + load. This is an absolute address + * relocation for PPC32 so the lis cannot be removed. + */ + lo =3D value; + hi =3D value - lo; + if (hi + lo !=3D value) { + return false; + } + code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + break; default: g_assert_not_reached(); } @@ -564,9 +617,29 @@ static void tcg_out_mem_long(TCGContext *s, int opi, i= nt opx, TCGReg rt, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (ret !=3D arg) { - tcg_out32(s, OR | SAB(arg, ret, arg)); + if (ret =3D=3D arg) { + return true; + } + switch (type) { + case TCG_TYPE_I64: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + /* fallthru */ + case TCG_TYPE_I32: + if (ret < TCG_REG_V0 && arg < TCG_REG_V0) { + tcg_out32(s, OR | SAB(arg, ret, arg)); + break; + } else if (ret < TCG_REG_V0 || arg < TCG_REG_V0) { + /* Altivec does not support vector/integer moves. */ + return false; + } + /* fallthru */ + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D TCG_REG_V0 && arg >=3D TCG_REG_V0); + tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); + break; + default: + g_assert_not_reached(); } return true; } @@ -718,7 +791,52 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long val) { - g_assert_not_reached(); + uint32_t load_insn; + int rel, low; + intptr_t add; + + low =3D (int8_t)val; + if (low >=3D -16 && low < 16) { + if (val =3D=3D (tcg_target_long)dup_const(MO_8, low)) { + tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val =3D=3D (tcg_target_long)dup_const(MO_16, low)) { + tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val =3D=3D (tcg_target_long)dup_const(MO_32, low)) { + tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); + return; + } + } + + /* + * Otherwise we must load the value from the constant pool. + */ + if (USE_REG_TB) { + rel =3D R_PPC_ADDR16; + add =3D -(intptr_t)s->code_gen_ptr; + } else { + rel =3D R_PPC_ADDR32; + add =3D 0; + } + + load_insn =3D LVX | VRT(ret) | RB(TCG_REG_TMP1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + new_pool_l2(s, rel, s->code_ptr, add, val, val); + } else { + new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + } + + if (USE_REG_TB) { + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); + load_insn |=3D RA(TCG_REG_TB); + } else { + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); + } + tcg_out32(s, load_insn); } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, @@ -878,7 +996,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, in= t opx, TCGReg rt, align =3D 3; /* FALLTHRU */ default: - if (rt !=3D TCG_REG_R0) { + if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { rs =3D rt; break; } @@ -892,13 +1010,13 @@ static void tcg_out_mem_long(TCGContext *s, int opi,= int opx, TCGReg rt, } =20 /* For unaligned, or very large offsets, use the indexed form. */ - if (offset & align || offset !=3D (int32_t)offset) { + if (offset & align || offset !=3D (int32_t)offset || opi =3D=3D 0) { if (rs =3D=3D base) { rs =3D TCG_REG_R0; } tcg_debug_assert(!is_store || rs !=3D rt); tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); - tcg_out32(s, opx | TAB(rt, base, rs)); + tcg_out32(s, opx | TAB(rt & 31, base, rs)); return; } =20 @@ -919,36 +1037,102 @@ static void tcg_out_mem_long(TCGContext *s, int opi= , int opx, TCGReg rt, base =3D rs; } if (opi !=3D ADDI || base !=3D rt || l0 !=3D 0) { - tcg_out32(s, opi | TAI(rt, base, l0)); + tcg_out32(s, opi | TAI(rt & 31, base, l0)); } } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, + TCGReg va, TCGReg vb, int shb) { - int opi, opx; - - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (type =3D=3D TCG_TYPE_I32) { - opi =3D LWZ, opx =3D LWZX; - } else { - opi =3D LD, opx =3D LDX; - } - tcg_out_mem_long(s, opi, opx, ret, arg1, arg2); + tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg base, intptr_t offset) { - int opi, opx; + int shift; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (type =3D=3D TCG_TYPE_I32) { - opi =3D STW, opx =3D STWX; - } else { - opi =3D STD, opx =3D STDX; + switch (type) { + case TCG_TYPE_I32: + if (ret < TCG_REG_V0) { + tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); + break; + } + tcg_debug_assert((offset & 3) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); + shift =3D (offset - 4) & 0xc; + if (shift) { + tcg_out_vsldoi(s, ret, ret, ret, shift); + } + break; + case TCG_TYPE_I64: + if (ret < TCG_REG_V0) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_mem_long(s, LD, LDX, ret, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(ret >=3D TCG_REG_V0); + tcg_debug_assert((offset & 7) =3D=3D 0); + tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); + if (offset & 8) { + tcg_out_vsldoi(s, ret, ret, ret, 8); + } + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D TCG_REG_V0); + tcg_debug_assert((offset & 15) =3D=3D 0); + tcg_out_mem_long(s, 0, LVX, ret, base, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg base, intptr_t offset) +{ + int shift; + + switch (type) { + case TCG_TYPE_I32: + if (arg < TCG_REG_V0) { + tcg_out_mem_long(s, STW, STWX, arg, base, offset); + break; + } + tcg_debug_assert((offset & 3) =3D=3D 0); + shift =3D (offset - 4) & 0xc; + if (shift) { + tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); + arg =3D TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); + break; + case TCG_TYPE_I64: + if (arg < TCG_REG_V0) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_mem_long(s, STD, STDX, arg, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(arg >=3D TCG_REG_V0); + tcg_debug_assert((offset & 7) =3D=3D 0); + if (offset & 8) { + tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); + arg =3D TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); + break; + case TCG_TYPE_V128: + tcg_debug_assert(arg >=3D TCG_REG_V0); + tcg_out_mem_long(s, 0, STVX, arg, base, offset); + break; + default: + g_assert_not_reached(); } - tcg_out_mem_long(s, opi, opx, arg, arg1, arg2); } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -2626,32 +2810,236 @@ static void tcg_out_op(TCGContext *s, TCGOpcode op= c, const TCGArg *args, =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { - g_assert_not_reached(); + switch (opc) { + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_not_vec: + return 1; + case INDEX_op_cmp_vec: + return vece <=3D MO_32 ? -1 : 0; + default: + return 0; + } } =20 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - g_assert_not_reached(); + tcg_debug_assert(dst >=3D TCG_REG_V0); + tcg_debug_assert(src >=3D TCG_REG_V0); + + /* + * Recall we use (or emulate) VSX integer loads, so the integer is + * right justified within the left (zero-index) double-word. + */ + switch (vece) { + case MO_8: + tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); + break; + case MO_16: + tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); + break; + case MO_32: + tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); + break; + case MO_64: + tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); + tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); + break; + default: + g_assert_not_reached(); + } + return true; } =20 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg out, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + int elt; + + tcg_debug_assert(out >=3D TCG_REG_V0); + switch (vece) { + case MO_8: + tcg_out_mem_long(s, 0, LVEBX, out, base, offset); + elt =3D extract32(offset, 0, 4); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 15; +#endif + tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_16: + tcg_debug_assert((offset & 1) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEHX, out, base, offset); + elt =3D extract32(offset, 1, 3); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 7; +#endif + tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_32: + tcg_debug_assert((offset & 3) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEWX, out, base, offset); + elt =3D extract32(offset, 2, 2); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 3; +#endif + tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_64: + tcg_debug_assert((offset & 7) =3D=3D 0); + tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); + tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); + elt =3D extract32(offset, 3, 1); +#ifndef HOST_WORDS_BIGENDIAN + elt =3D !elt; +#endif + if (elt) { + tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); + } else { + tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); + } + break; + default: + g_assert_not_reached(); + } + return true; } =20 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - g_assert_not_reached(); + static const uint32_t + eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, + gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }; + + TCGType type =3D vecl + TCG_TYPE_V64; + TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + uint32_t insn; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + return; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + return; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + return; + + case INDEX_op_and_vec: + insn =3D VAND; + break; + case INDEX_op_or_vec: + insn =3D VOR; + break; + case INDEX_op_xor_vec: + insn =3D VXOR; + break; + case INDEX_op_andc_vec: + insn =3D VANDC; + break; + case INDEX_op_not_vec: + insn =3D VNOR; + a2 =3D a1; + break; + + case INDEX_op_cmp_vec: + switch (args[3]) { + case TCG_COND_EQ: + insn =3D eq_op[vece]; + break; + case TCG_COND_GT: + insn =3D gts_op[vece]; + break; + case TCG_COND_GTU: + insn =3D gtu_op[vece]; + break; + default: + g_assert_not_reached(); + } + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } + + tcg_debug_assert(insn !=3D 0); + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap =3D false, need_inv =3D false; + + tcg_debug_assert(vece <=3D MO_32); + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv =3D true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap =3D true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap =3D need_inv =3D true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond =3D tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 =3D v1, v1 =3D v2, v2 =3D t1; + cond =3D tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + if (need_inv) { + tcg_gen_not_vec(vece, v0, v0); + } } =20 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { - g_assert_not_reached(); + va_list va; + TCGv_vec v0, v1, v2; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_cmp_vec: + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + default: + g_assert_not_reached(); + } + va_end(va); } =20 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) @@ -2691,6 +3079,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; + static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; + static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; + static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2826,6 +3217,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); =20 + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_orc_vec: + case INDEX_op_cmp_vec: + return &v_v_v; + case INDEX_op_not_vec: + case INDEX_op_dup_vec: + return &v_v; + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + case INDEX_op_dupm_vec: + return &v_r; + default: return NULL; } --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ZDmbwz7v2egeojt/Bhecjq76qk07ezt/13exaG5QJI=; b=tlrtg0ot3m6rRgpp3jDQDonLvaUnDhBRpCZTYAnOkvuE9j973Ra5upu6f0OStiZRRu LBt+0D5p9RNL2ZMbRioHi58ax8dkNdFrxfPvYTA2WCklFpl1+pvQb7a89FUgW4CVXedP KEqTH1OZueQ/KhKrS6B4iMpcFFLuCAtIFjBxVtFu//GpClcQonBz+LadaBam7SxS/Rnl xT0g5KHk+YQOVHxOqqst8U3STSqHYOypx8AKslMkn9LF4vkp9VM24s1wpCaGq54V//Ec 6xwU4tg1pGz7VRR9Mz4houyuQmMxMh9SRloUhXwkd+DTESJq+hCYCLAQMiNFQUc7jWhk fKdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ZDmbwz7v2egeojt/Bhecjq76qk07ezt/13exaG5QJI=; b=eErqtpDFNPPvp2ffOlfmSj/P0X5MpOuvDIrFI5ZqzmPaFm/44aJMZeCclP9zOJ2lku RTwSVUGtVQZlWHmlRGrzcL6yg1zWVbfRJPAamyIlwU+OAJ8wHn9Yc/zUq3Vfq5QGvs+4 PacQFO5ukbNzJtKfmzT78k/6CzbeR3xp/xHYHXpZxVJEEhp5IMrTVVnUPTeFSviBKZXP 9Sbj+NZ8IMP0uylj43TvGPXVY7WpQJTTrp2PsFGnDvEiR+vCjXsAD3DIlpLGiAEFV782 EDtp3J4YV2vFPloFrbkcdUiTbPFOS7sRtkvVxayMiKqtN0f3DSK1WNvsclzqQctCATbr TRkA== X-Gm-Message-State: APjAAAUmbKYKuejhB1i7OKmMO8qDRdGDdQAg6lEls9jFTY0LgPCvttC9 qG7s/xzUOlrRG4I+fL/WN9gW/mkzUjQ= X-Google-Smtp-Source: APXvYqzItHUPkRdf5afy43c40g8uNlqtHIXmTmykkan0WDWSR+mXwGG4eL+2+M5vXdsc/iuzVhvQcA== X-Received: by 2002:a63:205:: with SMTP id 5mr25662922pgc.77.1569874898562; Mon, 30 Sep 2019 13:21:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 09/22] tcg/ppc: Add support for vector maximum/minimum Date: Mon, 30 Sep 2019 13:21:12 -0700 Message-Id: <20190930202125.21064-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for vector maximum/minimum using Altivec instructions VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a0e59a5074..13699f1b63 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -164,7 +164,7 @@ extern bool have_altivec; #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 1a8d7dc925..6879be6f80 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -471,6 +471,19 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define STVX XO31(231) #define STVEWX XO31(199) =20 +#define VMAXSB VX4(258) +#define VMAXSH VX4(322) +#define VMAXSW VX4(386) +#define VMAXUB VX4(2) +#define VMAXUH VX4(66) +#define VMAXUW VX4(130) +#define VMINSB VX4(770) +#define VMINSH VX4(834) +#define VMINSW VX4(898) +#define VMINUB VX4(514) +#define VMINUH VX4(578) +#define VMINUW VX4(642) + #define VCMPEQUB VX4(6) #define VCMPEQUH VX4(70) #define VCMPEQUW VX4(134) @@ -2817,6 +2830,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_andc_vec: case INDEX_op_not_vec: return 1; + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + return vece <=3D MO_32; case INDEX_op_cmp_vec: return vece <=3D MO_32 ? -1 : 0; default: @@ -2914,7 +2932,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static const uint32_t eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, - gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }; + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, + smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, + umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -2931,6 +2953,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); return; =20 + case INDEX_op_smin_vec: + insn =3D smin_op[vece]; + break; + case INDEX_op_umin_vec: + insn =3D umin_op[vece]; + break; + case INDEX_op_smax_vec: + insn =3D smax_op[vece]; + break; + case INDEX_op_umax_vec: + insn =3D umax_op[vece]; + break; case INDEX_op_and_vec: insn =3D VAND; break; @@ -3223,6 +3257,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_cmp_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875456; cv=none; d=zoho.com; s=zohoarc; b=juru+oEB2THWd+kU2WBnHFnLXsqFeu4Zb+LJDfw3syANN0cjU2pwjDjeFkGXG7jvQNrL5HqdWEefXHJRipJrI1up4t5mdWpkY0QEbQ9UwYbJNkUPy06+AbvY3DNrknnv8wLssxJFvZqLTlqX17i4C8ysYQ52NS+64wgvKicQNrc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875456; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=oQgyY0q4tGN1HeWPOTFfa3ocMl6lXl7njB6OKQDxYM4=; b=IbOFxgDFyurZIe6kUCFoSP0zzRGkGEjSXTiobJontxVuCryguWDOdi7DImBgTFmwjenXJ4J/+hC5rtSHoqyi2/0U5ICM8uGg/9asVspfcKS1eXY/rEeksZyq4yj7eLyitEy1TX0yrcevB1jBcOgw0FEpDanBFTvWpXLiF7YdMLY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875456071630.1950871990463; Mon, 30 Sep 2019 13:30:56 -0700 (PDT) Received: from localhost ([::1]:56920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Jb-000573-S3 for importer@patchew.org; Mon, 30 Sep 2019 16:30:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44871) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Aw-0004eZ-EC for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Av-0005bA-Ah for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:42 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:46084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Av-0005as-5Z for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:41 -0400 Received: by mail-pf1-x443.google.com with SMTP id q5so6209746pfg.13 for ; Mon, 30 Sep 2019 13:21:41 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oQgyY0q4tGN1HeWPOTFfa3ocMl6lXl7njB6OKQDxYM4=; b=jpCoM8ihiHgJwEIxHdvVj4lVK4Y3iRb0lOVcH4KfTe8mqhgnHcEWHnGucJRn+9NbpY iJ2+eLXx5Op15ZL4nmtPa36ZGdmABupAxEvejvBbM9GJj1SHdPZDMGRtwwjoHOM5Zd8K +MbUMY2MRLmx+U6ng8ErSEhMmvLSQTpxTgMVDpfX6XjGq3xM0tk3WEG0cQZBYRfOchsi ztkPEZ0jdwj7DwSIeOrSeaDciz/PCZeJH4nu+B0qK1PkDf4tSGZKjBosXaJga2i6ku/G GL53wGzGUfNFfQSyFB7mvAL5UxuWrWj9cKwh6nb8WEf9Ff/tw2VdMQM4vFNE8+CYi9Lx Pv1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oQgyY0q4tGN1HeWPOTFfa3ocMl6lXl7njB6OKQDxYM4=; b=dGqP9QzXs9FEuVCHwI03+XAWyeZPtpL3SLW22k6nnx9qlbYUph1WtcWWwPADBL2cZW fBa45nRVQ+H8Qs8//FWDMPRU8xk9B89SNNrsMF7EH5+UYOU5MY5Ud3BIhudHn6xr8OUc MyVE+6iWazxOBjvFkd/idmcrC77N6S0rVuxZ6yNsX8XVHbjppcsCG/1e8kng+z7wPlAX YVj8OvFkgwnZqWx+eiceNf7R1aE3NpPzNZSBZ1f7VHg89knHcSZ/5lgER1kfFeNeD1m8 VMtJrrZNXhi95/P/o3rLeTarEP8j9+Knryo+YerXHSKL8Q+gPoZ7mScNsi4zoMhKoI6B NRTQ== X-Gm-Message-State: APjAAAVEemVjbMAxNxi+LMCJEbPInqSVX03ADEKAILHITF50Kw7fpRps Ip3/UkBm3xjUhm3mzcPlE2wQAsshSuw= X-Google-Smtp-Source: APXvYqxHePHrVJkLtCD4OHeUNYxgBVpbWsnFWZynCJ9DvmT/IkjGJV/2YliiQIZ+R+ncR+eWh8+vtw== X-Received: by 2002:a63:3709:: with SMTP id e9mr26198565pga.53.1569874899822; Mon, 30 Sep 2019 13:21:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 10/22] tcg/ppc: Add support for vector add/subtract Date: Mon, 30 Sep 2019 13:21:13 -0700 Message-Id: <20190930202125.21064-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for vector add/subtract using Altivec instructions: VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6879be6f80..6cfc78bb59 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -471,6 +471,14 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define STVX XO31(231) #define STVEWX XO31(199) =20 +#define VADDUBM VX4(0) +#define VADDUHM VX4(64) +#define VADDUWM VX4(128) + +#define VSUBUBM VX4(1024) +#define VSUBUHM VX4(1088) +#define VSUBUWM VX4(1152) + #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) @@ -2830,6 +2838,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_andc_vec: case INDEX_op_not_vec: return 1; + case INDEX_op_add_vec: + case INDEX_op_sub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: @@ -2930,6 +2940,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, const TCGArg *args, const int *const_args) { static const uint32_t + add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, 0 }, + sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, 0 }, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, @@ -2953,6 +2965,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); return; =20 + case INDEX_op_add_vec: + insn =3D add_op[vece]; + break; + case INDEX_op_sub_vec: + insn =3D sub_op[vece]; + break; case INDEX_op_smin_vec: insn =3D smin_op[vece]; break; @@ -3251,6 +3269,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); =20 + case INDEX_op_add_vec: + case INDEX_op_sub_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875746; cv=none; d=zoho.com; s=zohoarc; b=QnYHzwi2U2E0w0hA0g7ZFf/eDetxriLLatblmxZftiYA9ZixWNZiHtVltheLMlU30qfHtzzWDKkAdbBZdrj5eXHVHTafvRIXpReqAUdnJ6mw617rBp63iN/CV/EIZPgXT38bXs9xsod1gaRB8K7hlfAcZsojm2vFeHa3oWD85i4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875746; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sTJW6UTbb1j2FRe7m1NuaoxYc6z6Y7/0xQA7i53LXsg=; b=QV0Q3gdV/PanVsCRE3y6Ojacgv9z33dtJr/VzuE2IRm1uOQG8zxtV6wC9GoBgt/Z1TyzZyB0xUBhUq4waNr+XduQONPeQic99oS6BPEAGkQnC/WR/7nAksTowzm3WJT3K6OpfRMfyx8V/Uyrc3IJUK+7VkV7QE4ClkwDab21gO0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15698757465931003.4913070592502; Mon, 30 Sep 2019 13:35:46 -0700 (PDT) Received: from localhost ([::1]:56984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2OW-0000Uk-MF for importer@patchew.org; Mon, 30 Sep 2019 16:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44891) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Ay-0004gs-96 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Aw-0005dB-Ls for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:43 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:39826) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Aw-0005bS-Es for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:42 -0400 Received: by mail-pf1-x42f.google.com with SMTP id v4so6228740pff.6 for ; Mon, 30 Sep 2019 13:21:42 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sTJW6UTbb1j2FRe7m1NuaoxYc6z6Y7/0xQA7i53LXsg=; b=aOIK62qK9c1M/UcPsUhTjYsCx5SYE+x0szwbGvFfj5EZUHkAAz0HvXO44qXEabSNQ8 Em5sYdQDoscnsp0Fp9XOFh62tEuwGYJH5w6B/5q2L8T/T9K+azWVPVnV/n20b+G8EJZK jR2YlMvGWLhUL0mu83UOIsR1a4vVMkGiMzK/QfDQnIrSDwCtKQq/4yaLj0jEXIuCKLKB CoiC81z1CbSQWhANrpar0xxKLGaDRhAX/w+VMldDFmr4+40R0XRbfhYnxAcA2ZZ4RGcJ WgKi5hcx0lXRJomLh/uJ+65D7/NjpeogPx0zcr8hoSlkzUeBbR09e3dYOncqvKBqx2uS gJyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sTJW6UTbb1j2FRe7m1NuaoxYc6z6Y7/0xQA7i53LXsg=; b=PvxrIwvI5LqnsqD9RZzN0A6vQY5I/VCGCSSNgWvVcj9+7TCbFnYlZCxhW/wbjffgvJ iMmxGGgTwpWi5d2EQRqyI3itxzgPHVqDibWN8AM8S20BBIBsAxSH2D/+e6Yi4OafebJT cgHAU1YUR4DvNNqQt77TpEp7VAGhAC2F95kROPP8pKFc2+o47/+TbCWVAD7njANjrgYs 5R8m4pRGSjlfFdsc5Eq4sdSuRWZzQfnLo7Z7gMtSQH/OyEYO36xtHWZdAbvK1VKi4Rbq p4flRXhFBJVbfwsD3Sls6NZxVai1jq9dhIv3GKNYHjY3JynH83HZyk73kX1kui/kzkTT +qBw== X-Gm-Message-State: APjAAAUAa7rrHBiqPLLO6z1fDowY6tqYaTLQcRmXcZ4KnMA/0AELei8z mO7N9nqti7EsuTqKjar7OWNdWZtSDZQ= X-Google-Smtp-Source: APXvYqw6rY5S1kW2J1YHkSQgnjmsSWQl9G2v/BqZtX2ywB9YDIU4s6tRsAsRiLAJcG2IxX9tfUioFw== X-Received: by 2002:a17:90a:ad48:: with SMTP id w8mr1170947pjv.43.1569874901125; Mon, 30 Sep 2019 13:21:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract Date: Mon, 30 Sep 2019 13:21:14 -0700 Message-Id: <20190930202125.21064-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for vector saturated add/subtract using Altivec instructions: VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 13699f1b63..3ebbbfa77e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -163,7 +163,7 @@ extern bool have_altivec; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6cfc78bb59..a1165209fc 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -471,12 +471,24 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define STVX XO31(231) #define STVEWX XO31(199) =20 +#define VADDSBS VX4(768) +#define VADDUBS VX4(512) #define VADDUBM VX4(0) +#define VADDSHS VX4(832) +#define VADDUHS VX4(576) #define VADDUHM VX4(64) +#define VADDSWS VX4(896) +#define VADDUWS VX4(640) #define VADDUWM VX4(128) =20 +#define VSUBSBS VX4(1792) +#define VSUBUBS VX4(1536) #define VSUBUBM VX4(1024) +#define VSUBSHS VX4(1856) +#define VSUBUHS VX4(1600) #define VSUBUHM VX4(1088) +#define VSUBSWS VX4(1920) +#define VSUBUWS VX4(1664) #define VSUBUWM VX4(1152) =20 #define VMAXSB VX4(258) @@ -2844,6 +2856,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: return vece <=3D MO_32 ? -1 : 0; @@ -2945,6 +2961,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, + usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, + sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, + ussub_op[4] =3D { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, @@ -2971,6 +2991,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_ssadd_vec: + insn =3D ssadd_op[vece]; + break; + case INDEX_op_sssub_vec: + insn =3D sssub_op[vece]; + break; + case INDEX_op_usadd_vec: + insn =3D usadd_op[vece]; + break; + case INDEX_op_ussub_vec: + insn =3D ussub_op[vece]; + break; case INDEX_op_smin_vec: insn =3D smin_op[vece]; break; @@ -3277,6 +3309,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_cmp_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875776; cv=none; d=zoho.com; s=zohoarc; b=T1Fz/JW5EK4K/zbD+TCYbs7ZzUov1Z6DfhpdMjs23xxNDpQsmYMBwzUvXxRZNoQB4HR75CxIg6GLE67bXJ7btw2XQND1bPLpTuitrz93W7bQVjpP0Phhgi9An22IPz/chL9xS24P1K2pIsq8H4LtT1uURjcJUhgUF++Ybip7czM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875776; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2nm6apASWDrwzmzKxYCzPimVGo2WIvIIu5cuSVCbrLo=; b=ihK8vSFbIniJpwV8+8w9KGHk19ZKMzlkttXd/bqAXFOiFyvJEP8QTKmN2jIGSVxJzspvoyYtgexlFmjtd5ROR3O1Hq6D+p4lbCHOwm6mfenl646Hr36pKoT3ycXb/pRbXxWh2aZ4jBaBndVahewpYymBi2Sp95M1Qd/ceJdv9Fc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875776213215.06878907172677; Mon, 30 Sep 2019 13:36:16 -0700 (PDT) Received: from localhost ([::1]:56988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Ov-00018h-EJ for importer@patchew.org; Mon, 30 Sep 2019 16:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44906) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B0-0004kI-9K for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2Ax-0005eK-Uv for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:46 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:44438) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2Ax-0005ds-PU for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:43 -0400 Received: by mail-pl1-x641.google.com with SMTP id q15so4317639pll.11 for ; Mon, 30 Sep 2019 13:21:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2nm6apASWDrwzmzKxYCzPimVGo2WIvIIu5cuSVCbrLo=; b=tQTDhDoh8kzHSPKPKXfSpUDFpWeHa3dU9cPHI5mAZAx8VBlSEJLKYfZMxtRt9JvRYs JisL3c1qtx3qjfVsIJjny9zuvlvkc1LJY64Q6frQ2EAZDxTQV58NTkWAnjnrTXf42yEs HVZdbsl+Q//YQIg2jlSRunQgs3oSuO3Qgpusxb0s5aEkagasEyYcFKH/imK9yW5m/JVn s3exIrFjb9Z6zKbpKr/vCE5jnyCPvJ/gF5j+3Frpqt3wtZTuzLn+ddIN9SJTG/LUV9vJ kKEBeeIz/7jNPJQTQ3109ap4mRry5sGia/30+03A4L2cfcDtmhk0mdAHko1X2y7gF3Ws 1RAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2nm6apASWDrwzmzKxYCzPimVGo2WIvIIu5cuSVCbrLo=; b=TbMGhZPgbCoprrYXm8b12rWETy78D7tlAJwuIyOqIZjSwmze19ME5ojWHO1RrBjZW0 TgKppP1B8rz9lyfjPQy/A49iTY5DdadCJ4mTwrYvha8J+LmcMPCSDl6KXY8J/22zwjq1 SJmby+EYSx18z1VNuMbAGUumkdNiuIYMaMKrVnKhcExwUZMTIiUkNrOC92YgTEu1QIxD YkdRp0qXoKM+Fi6Ih4dcYR0L5l5l9xum/FEvIq+efvNDUsD126IpepnMLbloUG32uFg8 1pyxrZjRGCL1VHvS4UVXFlZ75S2icoQ1Hs3y5B3JPPZcUoMzMWchntdsLgcb+310G9xl asWQ== X-Gm-Message-State: APjAAAXzyoJNdGaTkQUkTeaw4qI98ydeBB7bNKPBGJJcvKN5Q7kYE2+b MUchiYeMKBjkjzFjEGsDkcFlkDobihE= X-Google-Smtp-Source: APXvYqxXqb7wn47QULafVerVWYgjp/lBtqeBNDJDh8qz7CEi3eo4BKWjneWCiEBQwQMtk1O1Q0wRVw== X-Received: by 2002:a17:902:b701:: with SMTP id d1mr20476004pls.209.1569874902388; Mon, 30 Sep 2019 13:21:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 12/22] tcg/ppc: Support vector shift by immediate Date: Mon, 30 Sep 2019 13:21:15 -0700 Message-Id: <20190930202125.21064-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Altivec, this is done via vector shift by vector, and loading the immediate into a register. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 3ebbbfa77e..ffb226946b 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -160,7 +160,7 @@ extern bool have_altivec; #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index a1165209fc..a9264eccbe 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -514,6 +514,16 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) =20 +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) + #define VAND VX4(1028) #define VANDC VX4(1092) #define VNOR VX4(1284) @@ -2860,8 +2870,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return vece <=3D MO_32 ? -1 : 0; default: return 0; @@ -2968,7 +2984,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, - smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }; + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, + shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, + shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3015,6 +3034,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umax_vec: insn =3D umax_op[vece]; break; + case INDEX_op_shlv_vec: + insn =3D shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn =3D shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn =3D sarv_op[vece]; + break; case INDEX_op_and_vec: insn =3D VAND; break; @@ -3059,6 +3087,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); } =20 +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { @@ -3110,14 +3150,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, { va_list va; TCGv_vec v0, v1, v2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); =20 switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; case INDEX_op_cmp_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; default: @@ -3317,6 +3368,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/W5+06zWjEsCCO8DDCnAnC5YfhRA72tGQm0aAGdzZVE=; b=oy8ECzrlPd9KlhFXDXmfv1GyfUpLI+kx024vQgtzaKW5aDC+u9oU/0vcYaEDbMSOvg 9S430iPtZd+BlU4haux5iMJNmpWnFhvkxlkPQ929Uei3AR0naFkcxSlMtseBJQe0r/q/ Pux/WfhEpFPn/iqHOcWqu7Llh4QJQVVV/ag1zAh6CVGOO+kaQ9FBOd5FZRhrcNWdrQsq jJ24bcAzbDE2nwE2+86ZULkWEp+6gQgL8gGER5tzuu1yHnGyES2SHgiWVeg1Q26CzT8y zPsEjwau8q+a7hCrSoUnwzXHyREPfRngtk1dUwmv1uQTHb1e98qNwMk0Uaj26Y5lTB8A Qigw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/W5+06zWjEsCCO8DDCnAnC5YfhRA72tGQm0aAGdzZVE=; b=YOhCx76Oz3N7UC7ILjEG2BEnWLFozrAyuLxNfcpM17PNCfD5cbQJnyg3aGCKSWLNVk fE4euzomk+tbAxNjJUnYHI6esap/kU36+neJ8qgj0OP6rQA8qTP2U2KFo4k1QYIq/RHO a/K7tVho9M8qETFRmCdz8QX3+83IsLhAlvoSnDc3dFnkQg++nWnqkh5F7AJcoi4WTJ1v ztc5FKteO+78746sRkfODzeZx1utrZL/n2Rj7O6V12t0uZPewKpss1cFD5dbBjoAWIPQ 3LWDuMOjgUiWqGf05etQLl9Sy+PcehQjFIf50QGV/8rqI6kFU3SVyAdCGyULptQUK8CP FsvQ== X-Gm-Message-State: APjAAAXSNZp+Msh+WPZ4/E33Xj4+rSnJH0ja/1pLJ3p78KMJvFzlA6rJ sSneWOlOnelW/lL2qBeV1swnBH7tFaI= X-Google-Smtp-Source: APXvYqy9X3RnCTT6/g5U/YRUcQQmD4HW5RQJIUkeGKx4PvT2IG0CINCg0WJXrwKF1TGPPHKszBQonA== X-Received: by 2002:a17:902:a70f:: with SMTP id w15mr22664141plq.132.1569874903802; Mon, 30 Sep 2019 13:21:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 13/22] tcg/ppc: Support vector multiply Date: Mon, 30 Sep 2019 13:21:16 -0700 Message-Id: <20190930202125.21064-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::634 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Altivec, this is always an expansion. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.opc.h | 8 +++ tcg/ppc/tcg-target.inc.c | 113 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 121 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index ffb226946b..f50b7f4bac 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -162,7 +162,7 @@ extern bool have_altivec; #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h index fa680dd6a0..db24a11987 100644 --- a/tcg/ppc/tcg-target.opc.h +++ b/tcg/ppc/tcg-target.opc.h @@ -3,3 +3,11 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ + +DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) +DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index a9264eccbe..d4b3354626 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -523,6 +523,25 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VSRAB VX4(772) #define VSRAH VX4(836) #define VSRAW VX4(900) +#define VRLB VX4(4) +#define VRLH VX4(68) +#define VRLW VX4(132) + +#define VMULEUB VX4(520) +#define VMULEUH VX4(584) +#define VMULOUB VX4(8) +#define VMULOUH VX4(72) +#define VMSUMUHM VX4(38) + +#define VMRGHB VX4(12) +#define VMRGHH VX4(76) +#define VMRGHW VX4(140) +#define VMRGLB VX4(268) +#define VMRGLH VX4(332) +#define VMRGLW VX4(396) + +#define VPKUHUM VX4(14) +#define VPKUWUM VX4(78) =20 #define VAND VX4(1028) #define VANDC VX4(1092) @@ -2875,6 +2894,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: @@ -2987,7 +3007,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, - sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }, + mrgh_op[4] =3D { VMRGHB, VMRGHH, VMRGHW, 0 }, + mrgl_op[4] =3D { VMRGLB, VMRGLH, VMRGLW, 0 }, + muleu_op[4] =3D { VMULEUB, VMULEUH, 0, 0 }, + mulou_op[4] =3D { VMULOUB, VMULOUH, 0, 0 }, + pkum_op[4] =3D { VPKUHUM, VPKUWUM, 0, 0 }, + rotl_op[4] =3D { VRLB, VRLH, VRLW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3076,6 +3102,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_ppc_mrgh_vec: + insn =3D mrgh_op[vece]; + break; + case INDEX_op_ppc_mrgl_vec: + insn =3D mrgl_op[vece]; + break; + case INDEX_op_ppc_muleu_vec: + insn =3D muleu_op[vece]; + break; + case INDEX_op_ppc_mulou_vec: + insn =3D mulou_op[vece]; + break; + case INDEX_op_ppc_pkum_vec: + insn =3D pkum_op[vece]; + break; + case INDEX_op_ppc_rotl_vec: + insn =3D rotl_op[vece]; + break; + case INDEX_op_ppc_msum_vec: + tcg_debug_assert(vece =3D=3D MO_16); + tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])= ); + return; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ @@ -3145,6 +3194,53 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, } } =20 +static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + TCGv_vec t2 =3D tcg_temp_new_vec(type); + TCGv_vec t3, t4; + + switch (vece) { + case MO_8: + case MO_16: + vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v0), tcgv_vec_arg(t1)); + break; + + case MO_32: + t3 =3D tcg_temp_new_vec(type); + t4 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(MO_8, t4, -16); + vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_dupi_vec(MO_8, t3, 0); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), + tcgv_vec_arg(t3), tcgv_vec_arg(t4)); + tcg_gen_add_vec(MO_32, v0, t2, t3); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -3171,6 +3267,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_mul_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; default: g_assert_not_reached(); } @@ -3217,6 +3317,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; + static const TCGTargetOpDef v_v_v_v + =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -3354,6 +3456,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: + case INDEX_op_mul_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: @@ -3371,6 +3474,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_ppc_mrgh_vec: + case INDEX_op_ppc_mrgl_vec: + case INDEX_op_ppc_muleu_vec: + case INDEX_op_ppc_mulou_vec: + case INDEX_op_ppc_pkum_vec: + case INDEX_op_ppc_rotl_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: @@ -3379,6 +3488,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_vec: case INDEX_op_dupm_vec: return &v_r; + case INDEX_op_ppc_msum_vec: + return &v_v_v_v; =20 default: return NULL; --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eU6/QJc2xrfxfZzNiKt2RQhZfpRk2OkG4frCv/G8gNE=; b=yEycODM/0oxECnH4Tbbm22S75MbJYCQHK818mSScyjNAe0kBVVtaKvn8hAy8RtMb2O tMKpNjObClShVvO+22v7qWPd58eaMGqnCsFsILy+KipEzGOWKbXIAlqGfQ218THyBUUE Th5nb11vsmjcnwjCPEDVK2bC7tpOSX+Bux/w+cSgI1KBnHHQ8209QKnTUvyQNEjj3Jlq pj1ETMQHHC+JKIHlPinLrOudCJOiyDNHllYv2x4LkvddIO/ogi4fa8V0pzMv4qz+rNtV aInxKETCApN89cM4xTccWMgLwrMHS13UVIBGd3XH+tZ4/+HuPec8bjeVWC/fK7usVnOv 29iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eU6/QJc2xrfxfZzNiKt2RQhZfpRk2OkG4frCv/G8gNE=; b=OqEl+R2TmN7ELBbxvkZXtvZobK4Ui5x7D5mVz0mY0L5OoIcHA0TeWz5Vd3rf4nz7Nu zZ5CaLmhh2kAlIJrFW5VAN37qqx6fq4Oghf+k6DxezFcfFmUPO50GoFq9eeVQkXuzycI G4sQ1qOgDRhyHnm7OeWUeKSO/p3jrpAO0fKS193tYh/K80WxOcB7yzQdRgeRWNikMHQL wgB6UvI1Sc5TdNZI62D/yB2ti5+w/dbHf9k5klxoQ1gbcDbghdQLoJ9EWoDTjBIVEpps kYFoS/GlOYWXSyHF4P7vlFZ9tJi69zi7x9OhPzleYLyuYPjvm5K1KoO6RMxJJZodakhr VNbw== X-Gm-Message-State: APjAAAUTKVoGkbz4zWYu4ibfBSzgpkYsWdGApeJSaLZOanE+UMvi4Tee Hsrce4Dn0XRwmonvkWW7Eyyf+4jmS0o= X-Google-Smtp-Source: APXvYqwNyai+oNom2mA/ZtunPzB4O1K7qgGIgIEItxSt2AzsLrskJmJZomy4GCyALJ5364kTEFQh/Q== X-Received: by 2002:a17:902:fe81:: with SMTP id x1mr21917300plm.66.1569874905017; Mon, 30 Sep 2019 13:21:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 14/22] tcg/ppc: Support vector dup2 Date: Mon, 30 Sep 2019 13:21:17 -0700 Message-Id: <20190930202125.21064-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is only used for 32-bit hosts. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d4b3354626..8a508136ce 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3102,6 +3102,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_dup2_vec: + assert(TCG_TARGET_REG_BITS =3D=3D 32); + /* With inputs a1 =3D xLxx, a2 =3D xHxx */ + tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 =3D xx= HL */ + tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp =3D HL= xx */ + tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 =3D HL= HL */ + return; + case INDEX_op_ppc_mrgh_vec: insn =3D mrgh_op[vece]; break; @@ -3480,6 +3488,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_ppc_rotl_vec: + case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569876201; cv=none; d=zoho.com; s=zohoarc; b=A4HhySNKkF0CqpSK/arJXdXigG1WncuGr0e7R2r//FEVO7E97piB/jbmauAY8M+fRo3clwyzKm7S+iSFJt4XasIkxSdZ/KydsDMDmj6nqPhFS4i/xXaQwXu4ARGHWdk5ddYp/dloJS+JcHnXLYmWleJxxxWG01K7p4A+HO3znsc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569876201; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0eIQzpvgKZ/1Z44eyY68s5331mz4V928vlgpASMp7Pk=; b=Wi76eMvBylJHQSzMxR6+j0YOtHWq7BWxr6Jjt/RIMaE0BPll8X3znVtZ8WaFhxc1s7PFR/92GSUtUk5nE0fzj7eNYeYJN914xRRKFr6HqiLN5/0DipJW0EqscJC1rg+eR67UHpiO3f5DbbG+GTvBYBq2p7Ftb0dDKWDVN7PgMro= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569876201410615.6248776396856; Mon, 30 Sep 2019 13:43:21 -0700 (PDT) Received: from localhost ([::1]:57080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Vk-00009A-LL for importer@patchew.org; Mon, 30 Sep 2019 16:43:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44947) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B2-0004oL-VK for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B1-0005iu-T4 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:48 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:39078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B1-0005hx-N7 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:47 -0400 Received: by mail-pl1-x644.google.com with SMTP id s17so4329615plp.6 for ; Mon, 30 Sep 2019 13:21:47 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0eIQzpvgKZ/1Z44eyY68s5331mz4V928vlgpASMp7Pk=; b=u8SqBZHcdak4pksG6lmbHjMDYyCYXa02XHd/hvU7IGun0TuXp6MJ6UMBqy5QmZIrMi jcy0MqGuiLqRnfNyhs/Tu+CkpQy/T6JlRq6Lfhj9pkbKSq5Qxzo8bYDgs3e7PKOQj3j/ seRSYZHgdFTFo+F/Zo8Ka7qPo7bUguxXeS0Boi6Jd0LR6UYQ0Bj91uu1+qM8bme7oz+v yIEtuRTD8xg5r/ZALgs1SKIaZJmBfACcJEF/Mls8t7nZEeGBJIG/3O+WCr4jZRUPNxWN zzB0LfN1Vj/vuGog21nIsKyKz5eTbNDQMmGSLu0XxwaC68nWpGUx2i+q9XTatd6utPgC 3Lbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0eIQzpvgKZ/1Z44eyY68s5331mz4V928vlgpASMp7Pk=; b=a2hq/cjvNIlIFelnsJ0wkq7qgT1ZflwU94nFabVKB9uoGwb6Lk1rqNBnOeyt9E/JLW S6zHFCNM/JNoEhmCuavOMvAd51OG6fCg+CnMHTJoNvkEXN5aBtfDJ9sBN7X0gzgdqll4 zdx2q9TNV+PFbBzDm7yh5c5JgHDOm/CdjuEja/6u7stzufcptenTIBznMz/3KyYym0fO 0Z1bo0YVWaATVctOmSvu4/uv0QLkgg/wgCE/k/wZ1NIoUH7e8k+7LNepDQgrojnvOtZq TIL8h9BOmMLos0jRJYYAaMZepBp2xrq6E5esQZ3ZfgIt4W5yzn3qSMkRave+YOA45WNh J0kQ== X-Gm-Message-State: APjAAAUJcw/gDlbA1NBV7+gGoXp9/30rCF5uc8Aq4U+7SvwrDv00fH+G k2yOzGH19VBALV/VnakV6sFbB93gPZc= X-Google-Smtp-Source: APXvYqzAJtoyQfhO+jTPRBpMqsqfJuHAywBEeNEfRUAbMY8TZkVOGYmz7/JBD5xvTMRd/2iWqzQP8g== X-Received: by 2002:a17:902:6bc5:: with SMTP id m5mr19093111plt.282.1569874906458; Mon, 30 Sep 2019 13:21:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 15/22] tcg/ppc: Enable Altivec detection Date: Mon, 30 Sep 2019 13:21:18 -0700 Message-Id: <20190930202125.21064-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have implemented the required tcg operations, we can enable detection of host vector support. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8a508136ce..d739f4b605 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3528,6 +3528,10 @@ static void tcg_target_init(TCGContext *s) have_isel =3D have_isa_2_06; #endif =20 + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { + have_altivec =3D true; + } + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; if (have_altivec) { --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569876423; cv=none; d=zoho.com; s=zohoarc; b=hy7vNLRaxKdI11JEREGmUhHgxucQHCSAuZAKjXGO4Ix5eV6XdpQzQ//zAE2z9+wNYOLAfyzgnjZfYv0j8RuxCG3XH6ZLhhVISxQo4QEM51HA6wAwywZlo8TcwiQNfPiCnHKhR6krKDXqPbXP/eW8Yl1HAqItjHTks6PqCnDwq+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569876423; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=mF2dwYJWcVeNG6LNSvu0FtPI46NJT+aJNqlh22HKVwc=; b=boElUfvQbkP99fXIdvFEpRLENkPt4PvEjN8f1VreW77UdTMpvIuuE1kEF3MFGIygqmyJX0l8fkLGUNdinW2CRdcXYZ1KU6TGhC4a3QX5c97pGvlAl3hdfVvvCtwU0fFb3zZwfUO5M9NIvNCYNze1jNyMrAtpUCRGu9DjQ36d2G4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569876423057229.3772335182424; Mon, 30 Sep 2019 13:47:03 -0700 (PDT) Received: from localhost ([::1]:57124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2ZR-0002pG-1d for importer@patchew.org; Mon, 30 Sep 2019 16:47:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44989) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B7-0004tO-Ap for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B3-0005jw-NE for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:53 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:42435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B3-0005jY-FV for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:49 -0400 Received: by mail-pf1-x42c.google.com with SMTP id q12so6221002pff.9 for ; Mon, 30 Sep 2019 13:21:49 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mF2dwYJWcVeNG6LNSvu0FtPI46NJT+aJNqlh22HKVwc=; b=U4gQ6IwUT23InWA7cEkUV5NB2VXgScWEeFdPu0kmbdtT8rYuXAgBJ2wo8RmuJSTayb A+Y3OKkNPwl6Pdbfo1GqMGvJNAmFTzhy5MLQ0PkEhPz15bF67xFvIANRCq0JgFCxPX+I ZC3RtxGVIpFsv4okD4mBsQpCMWDOyV4l/CESfGTasO9DLrZI8FEdpKIl9Xx4MYjVrBQF MBG4TnVXyQHdOBQIfM4QcPSbNryTcLrJ5fK2t2L8zBFfKDqqnCDE2huV5RdmBn3ix6Cy R4oiBsnWOT+YiwL3gN0R9MXtVvK24rpLkhOj7pP7OigldrMtROLQqQ6RJNn3FoEJjeSm 5Oug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mF2dwYJWcVeNG6LNSvu0FtPI46NJT+aJNqlh22HKVwc=; b=ANcIkez/w8ihlJX6kAk9p0ZyjZu+WtDNjb2nQGxSl7pTNVo7VtMiWtA53pfl3gtriy 9VWpxlh3RVQC+GBDaol1e+ajTTf6l2YN8bXqw762gadVZhh+7H+xkCos0nUIy/yoiHpr pKU/1IR6pZVacJWTlcZOsC8+R3F2mFDeA6OdxC8KGYE0B1KobF6CLqjmhRUuN0Pz223g rG9QgMbNc8RB3JLNMmz+/kpRns66hLOjpPgYm9yAhKspvuoYXt50y5gdt5PhcV0imA4K sV3okPQ2FQvVnKraVQSq3xHHN1Iyb5HN9VUzHtEcTeE/HlDAuoyKp9dYNeDAI0pmwtP0 /OJA== X-Gm-Message-State: APjAAAXLQoNJnG/iVOrtmEYCcuLTeN/VRFAFgmo8m4VUxc7N+qlcse3g rGPvIamxnuZG1ou37YrYno0KHP9k6+c= X-Google-Smtp-Source: APXvYqyjCma6AmATAr5SXyiOAyHHImY03mcsbEQYtCJLMN15YK7n3UFxWigCz0Meb+8k0JNUCCRnZw== X-Received: by 2002:a65:64d0:: with SMTP id t16mr26765607pgv.0.1569874907792; Mon, 30 Sep 2019 13:21:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 16/22] tcg/ppc: Update vector support for VSX Date: Mon, 30 Sep 2019 13:21:19 -0700 Message-Id: <20190930202125.21064-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The VSX instruction set instructions include double-word loads and stores, double-word load and splat, double-word permute, and bit select. All of which require multiple operations in the Altivec instruction set. Because the VSX registers map %vsr32 to %vr0, and we have no current intention or need to use vector registers outside %vr0-%vr19, force on the {ax,bx,cx,tx} bits within the added VSX insns so that we don't have to otherwise modify the VR[TABC] macros. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 5 ++-- tcg/ppc/tcg-target.inc.c | 52 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 51 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index f50b7f4bac..c974ca274a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -66,6 +66,7 @@ typedef enum { =20 extern TCGPowerISA have_isa; extern bool have_altivec; +extern bool have_vsx; =20 #define have_isa_2_06 (have_isa >=3D tcg_isa_2_06) #define have_isa_3_00 (have_isa >=3D tcg_isa_3_00) @@ -149,7 +150,7 @@ extern bool have_altivec; * instruction and substituting two 32-bit stores makes the generated * code quite large. */ -#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v64 have_vsx #define TCG_TARGET_HAS_v128 have_altivec #define TCG_TARGET_HAS_v256 0 =20 @@ -165,7 +166,7 @@ extern bool have_altivec; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 =20 void flush_icache_range(uintptr_t start, uintptr_t stop); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d739f4b605..2388958405 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr; TCGPowerISA have_isa; static bool have_isel; bool have_altivec; +bool have_vsx; =20 #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG 30 @@ -467,9 +468,12 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define LVEBX XO31(7) #define LVEHX XO31(39) #define LVEWX XO31(71) +#define LXSDX (XO31(588) | 1) /* v2.06, force tx=3D1 */ +#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=3D1 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) +#define STXSDX (XO31(716) | 1) /* v2.06, force sx=3D1 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -558,6 +562,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, =20 #define VSLDOI VX4(44) =20 +#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=3Dbx=3Dt= x=3D1 */ +#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=3Dbx=3Dc= x=3Dtx=3D1 */ + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -884,11 +891,21 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, TCGReg ret, add =3D 0; } =20 - load_insn =3D LVX | VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_l2(s, rel, s->code_ptr, add, val, val); + if (have_vsx) { + load_insn =3D type =3D=3D TCG_TYPE_V64 ? LXSDX : LXVDSX; + load_insn |=3D VRT(ret) | RB(TCG_REG_TMP1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + new_pool_label(s, val, rel, s->code_ptr, add); + } else { + new_pool_l2(s, rel, s->code_ptr, add, val, val); + } } else { - new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + load_insn =3D LVX | VRT(ret) | RB(TCG_REG_TMP1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + new_pool_l2(s, rel, s->code_ptr, add, val, val); + } else { + new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + } } =20 if (USE_REG_TB) { @@ -1136,6 +1153,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg ret, /* fallthru */ case TCG_TYPE_V64: tcg_debug_assert(ret >=3D TCG_REG_V0); + if (have_vsx) { + tcg_out_mem_long(s, 0, LXSDX, ret, base, offset); + break; + } tcg_debug_assert((offset & 7) =3D=3D 0); tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); if (offset & 8) { @@ -1180,6 +1201,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, /* fallthru */ case TCG_TYPE_V64: tcg_debug_assert(arg >=3D TCG_REG_V0); + if (have_vsx) { + tcg_out_mem_long(s, 0, STXSDX, arg, base, offset); + break; + } tcg_debug_assert((offset & 7) =3D=3D 0); if (offset & 8) { tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); @@ -2899,6 +2924,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shri_vec: case INDEX_op_sari_vec: return vece <=3D MO_32 ? -1 : 0; + case INDEX_op_bitsel_vec: + return have_vsx; default: return 0; } @@ -2925,6 +2952,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType t= ype, unsigned vece, tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); break; case MO_64: + if (have_vsx) { + tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); + break; + } tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); break; @@ -2968,6 +2999,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType = type, unsigned vece, tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); break; case MO_64: + if (have_vsx) { + tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); + break; + } tcg_debug_assert((offset & 7) =3D=3D 0); tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); @@ -3102,6 +3137,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_bitsel_vec: + tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); + return; + case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS =3D=3D 32); /* With inputs a1 =3D xLxx, a2 =3D xHxx */ @@ -3497,6 +3536,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_vec: case INDEX_op_dupm_vec: return &v_r; + case INDEX_op_bitsel_vec: case INDEX_op_ppc_msum_vec: return &v_v_v_v; =20 @@ -3530,6 +3570,10 @@ static void tcg_target_init(TCGContext *s) =20 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { have_altivec =3D true; + /* We only care about the portion of VSX that overlaps Altivec. */ + if (hwcap & PPC_FEATURE_HAS_VSX) { + have_vsx =3D true; + } } =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569876227; cv=none; d=zoho.com; s=zohoarc; b=dHa/0iD3P0XTmRWt5G7k54geTppEamuFTIgIUzigLO1pJadXGu+ZW6MsHZ/1XdlXWupvFn5IqCq0SNTQ8lT1TcmLR1GPgz+N/on19iwany1IuW5TZSJtSeFFg/qq9XF4o4cyA4lW/rbFOIq7CRmqU5pG53k9RpQwvnStWHOX4Sk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569876227; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jLNbcp2nOrZ2ZLaJ9eyqETFPjvsCI5cyn5OFcvkWp5Q=; b=QXSPU3TllqgKO/smV6FFd/EH41JhYWzGiF7aC6wgJPxmnO7XC6J3kddbWkuOZlgy09sJ57ZJsZdiM+P81YAnBTYqKa7grBKiUoLBS1v5KxLCPRjbwRamx+cp3JjsDWgP4i0A9hby5hEMWdL5dJzeV5EglJXpIP7FN7ZLTtQYzAE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569876227394477.67191402173535; Mon, 30 Sep 2019 13:43:47 -0700 (PDT) Received: from localhost ([::1]:57090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2WH-0000hg-Gq for importer@patchew.org; Mon, 30 Sep 2019 16:43:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44991) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B7-0004tq-GM for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B4-0005kK-OM for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:53 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B4-0005k8-GJ for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:50 -0400 Received: by mail-pf1-x442.google.com with SMTP id b128so6246703pfa.1 for ; Mon, 30 Sep 2019 13:21:50 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jLNbcp2nOrZ2ZLaJ9eyqETFPjvsCI5cyn5OFcvkWp5Q=; b=oAh3toL23wpmK4aaBtMy6MtJNdsZc0xeeAzmnriU5Fx5fbsEOohg+2penPNQ78iEOH rJfW+l8EuImOhw4KkdVCO0hrrcgOH4ZbCa1l1+kzPlalDjOmfuaBDWGNvBjogVaVUXMG YcfMDOoQ7HohxWmlywi0ThKFUwyDFbt1W9cZerJSg5kw+DgrQVjX/iDR/U6+naee/xZW sX/CCzmmSnanLEuswyJXQ4V4UAkC4uUEsVV5W31qfu3vOBPdVrL2N4SqKM4ChieXRSvF SKI0rjyuBKDdmrcC75B3KEuQNUf5p3CI49GOiMbEUDB4fnOGKPFZFfM+5Y8JlCacyPcL zoAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jLNbcp2nOrZ2ZLaJ9eyqETFPjvsCI5cyn5OFcvkWp5Q=; b=UvlkAS0isLtgrR8uGcw1kxafQBWQJooF7ajQ4c6dCe3LCzzAFfHrXdMRAoiDK4C01j dnOhGXCF90ul7bgvZ23WYdi3vgfEu3FZ/zeUVSm/dPv4Fu4oB41IrEpLAhmvAYaY32VN oWd8+wR4UPwj/Bz1AMwiSFHVZfJUWHntjyr4DttYwibepmmhiY3g5UOjK0g6uUIlTS7j fFWqUkKk9J9En8kqxXXM4IvwgnL3w5uJmxQwrHbavp//ps4N88+0Q8gIScS/FtAcnO+S 9/bxjBqFDRFRvqjk3GbqwW5scJQU/J3Qi/g4wnzsnWD/BQIWxW70IdLJGGWNhEZxd5kf DjRQ== X-Gm-Message-State: APjAAAXOYh4VrJpb9RM45Mjio0IOOjCjSG6WLd0Z1LSJgrll9eTK1hSj 01VF9bqrhQi3lDQrqNNm1I6Ve2vU8ww= X-Google-Smtp-Source: APXvYqzQ0CYK41eAKARvmiU//P99FfBYhmy+fNUCObFc8t6VKpFZzqsygdmeplu2dQZbx/uSeW7foA== X-Received: by 2002:a62:5cc3:: with SMTP id q186mr23133716pfb.15.1569874909135; Mon, 30 Sep 2019 13:21:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 17/22] tcg/ppc: Update vector support for v2.07 Altivec Date: Mon, 30 Sep 2019 13:21:20 -0700 Message-Id: <20190930202125.21064-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional only on MSR.VEC and are thus part of the Altivec instruction set, and not VSX. This includes lots of double-word arithmetic and a few extra logical operations. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 4 +- tcg/ppc/tcg-target.inc.c | 85 ++++++++++++++++++++++++++++++---------- 2 files changed, 67 insertions(+), 22 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c974ca274a..13197eddce 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -61,6 +61,7 @@ typedef enum { typedef enum { tcg_isa_base, tcg_isa_2_06, + tcg_isa_2_07, tcg_isa_3_00, } TCGPowerISA; =20 @@ -69,6 +70,7 @@ extern bool have_altivec; extern bool have_vsx; =20 #define have_isa_2_06 (have_isa >=3D tcg_isa_2_06) +#define have_isa_2_07 (have_isa >=3D tcg_isa_2_07) #define have_isa_3_00 (have_isa >=3D tcg_isa_3_00) =20 /* optional instructions automatically implemented */ @@ -155,7 +157,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_v256 0 =20 #define TCG_TARGET_HAS_andc_vec 1 -#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_orc_vec have_isa_2_07 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 2388958405..bc3a669cb4 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -484,6 +484,7 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VADDSWS VX4(896) #define VADDUWS VX4(640) #define VADDUWM VX4(128) +#define VADDUDM VX4(192) /* v2.07 */ =20 #define VSUBSBS VX4(1792) #define VSUBUBS VX4(1536) @@ -494,47 +495,62 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define VSUBSWS VX4(1920) #define VSUBUWS VX4(1664) #define VSUBUWM VX4(1152) +#define VSUBUDM VX4(1216) /* v2.07 */ =20 #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) +#define VMAXSD VX4(450) /* v2.07 */ #define VMAXUB VX4(2) #define VMAXUH VX4(66) #define VMAXUW VX4(130) +#define VMAXUD VX4(194) /* v2.07 */ #define VMINSB VX4(770) #define VMINSH VX4(834) #define VMINSW VX4(898) +#define VMINSD VX4(962) /* v2.07 */ #define VMINUB VX4(514) #define VMINUH VX4(578) #define VMINUW VX4(642) +#define VMINUD VX4(706) /* v2.07 */ =20 #define VCMPEQUB VX4(6) #define VCMPEQUH VX4(70) #define VCMPEQUW VX4(134) +#define VCMPEQUD VX4(199) /* v2.07 */ #define VCMPGTSB VX4(774) #define VCMPGTSH VX4(838) #define VCMPGTSW VX4(902) +#define VCMPGTSD VX4(967) /* v2.07 */ #define VCMPGTUB VX4(518) #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) +#define VCMPGTUD VX4(711) /* v2.07 */ =20 #define VSLB VX4(260) #define VSLH VX4(324) #define VSLW VX4(388) +#define VSLD VX4(1476) /* v2.07 */ #define VSRB VX4(516) #define VSRH VX4(580) #define VSRW VX4(644) +#define VSRD VX4(1732) /* v2.07 */ #define VSRAB VX4(772) #define VSRAH VX4(836) #define VSRAW VX4(900) +#define VSRAD VX4(964) /* v2.07 */ #define VRLB VX4(4) #define VRLH VX4(68) #define VRLW VX4(132) +#define VRLD VX4(196) /* v2.07 */ =20 #define VMULEUB VX4(520) #define VMULEUH VX4(584) +#define VMULEUW VX4(648) /* v2.07 */ #define VMULOUB VX4(8) #define VMULOUH VX4(72) +#define VMULOUW VX4(136) /* v2.07 */ +#define VMULUWM VX4(137) /* v2.07 */ #define VMSUMUHM VX4(38) =20 #define VMRGHB VX4(12) @@ -552,6 +568,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VNOR VX4(1284) #define VOR VX4(1156) #define VXOR VX4(1220) +#define VEQV VX4(1668) /* v2.07 */ +#define VNAND VX4(1412) /* v2.07 */ +#define VORC VX4(1348) /* v2.07 */ =20 #define VSPLTB VX4(524) #define VSPLTH VX4(588) @@ -2904,26 +2923,37 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_andc_vec: case INDEX_op_not_vec: return 1; + case INDEX_op_orc_vec: + return have_isa_2_07; case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return vece <=3D MO_32 || have_isa_2_07; case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: - case INDEX_op_mul_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return vece <=3D MO_32 ? -1 : 0; + return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_mul_vec: + switch (vece) { + case MO_8: + case MO_16: + return -1; + case MO_32: + return have_isa_2_07 ? 1 : -1; + } + return 0; case INDEX_op_bitsel_vec: return have_vsx; default: @@ -3027,28 +3057,28 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, const TCGArg *args, const int *const_args) { static const uint32_t - add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, 0 }, - sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, 0 }, - eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, - gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, - gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, + sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, ussub_op[4] =3D { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, - umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, - smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, - umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, - smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, - shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, - shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, - sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }, + umin_op[4] =3D { VMINUB, VMINUH, VMINUW, VMINUD }, + smin_op[4] =3D { VMINSB, VMINSH, VMINSW, VMINSD }, + umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, + shlv_op[4] =3D { VSLB, VSLH, VSLW, VSLD }, + shrv_op[4] =3D { VSRB, VSRH, VSRW, VSRD }, + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, VSRAD }, mrgh_op[4] =3D { VMRGHB, VMRGHH, VMRGHW, 0 }, mrgl_op[4] =3D { VMRGLB, VMRGLH, VMRGLW, 0 }, - muleu_op[4] =3D { VMULEUB, VMULEUH, 0, 0 }, - mulou_op[4] =3D { VMULOUB, VMULOUH, 0, 0 }, + muleu_op[4] =3D { VMULEUB, VMULEUH, VMULEUW, 0 }, + mulou_op[4] =3D { VMULOUB, VMULOUH, VMULOUW, 0 }, pkum_op[4] =3D { VPKUHUM, VPKUWUM, 0, 0 }, - rotl_op[4] =3D { VRLB, VRLH, VRLW, 0 }; + rotl_op[4] =3D { VRLB, VRLH, VRLW, VRLD }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3071,6 +3101,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_mul_vec: + tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07); + insn =3D VMULUWM; + break; case INDEX_op_ssadd_vec: insn =3D ssadd_op[vece]; break; @@ -3120,6 +3154,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, insn =3D VNOR; a2 =3D a1; break; + case INDEX_op_orc_vec: + insn =3D VORC; + break; =20 case INDEX_op_cmp_vec: switch (args[3]) { @@ -3200,7 +3237,7 @@ static void expand_vec_cmp(TCGType type, unsigned vec= e, TCGv_vec v0, { bool need_swap =3D false, need_inv =3D false; =20 - tcg_debug_assert(vece <=3D MO_32); + tcg_debug_assert(vece <=3D MO_32 || have_isa_2_07); =20 switch (cond) { case TCG_COND_EQ: @@ -3264,6 +3301,7 @@ static void expand_vec_mul(TCGType type, unsigned vec= e, TCGv_vec v0, break; =20 case MO_32: + tcg_debug_assert(!have_isa_2_07); t3 =3D tcg_temp_new_vec(type); t4 =3D tcg_temp_new_vec(type); tcg_gen_dupi_vec(MO_8, t4, -16); @@ -3554,6 +3592,11 @@ static void tcg_target_init(TCGContext *s) if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa =3D tcg_isa_2_06; } +#ifdef PPC_FEATURE2_ARCH_2_07 + if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { + have_isa =3D tcg_isa_2_07; + } +#endif #ifdef PPC_FEATURE2_ARCH_3_00 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { have_isa =3D tcg_isa_3_00; --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xEcXFFwqOctiA3QPkHa6PrMKHQqTuGEioojAtcvmLA0=; b=OuZkGTKWyp9AxznhZKDAIfj+uzC3CaNCFQaYXUFw4p1gbfEri1swMY4pwSQyiZ74Ee DQ7DAgWiOCy2mMIqv1pFGNr/coK2RDm7A7L7DCtVd1fv1iJThGt34QEDoMDVxD9BnWZH TzrdUhWyS6nEJsh9hzPQRyQwsAKA2Vhz/+lkZZ/uueREEpG6duMDlWv/wElASeJ2PGga Ru2jh0ujzvOk3VZAKjrBBQzId/Fywi9KFQ0/cS6Yhj8EbmwXUcwIi1Ecy3BiszXjHYnU Qt2iFIga279q1rn9o3SP7THld1vyL2xUE7XyytgzZiICgM2saD7ApXjDLro/PnhCWFAs 72ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xEcXFFwqOctiA3QPkHa6PrMKHQqTuGEioojAtcvmLA0=; b=HObqNzeLEll+jqt0kI8Ghk3p7nZxmX1aukE2cZWqJI+L7GAerA0asUqaSYDnWoqBzZ krRrAMVFYWdQppssSh89s6y+F3/FL4LNFwTOD98YQ0R7N9fzEiDkZSuJBmj2bRafAKhz Y9b5iroZJldLh4HYtxGZtxCMox0rYElvdFpEJ2v/9FQ1rhci4H/biYp7Pnjt9VlSu04i dM7iADZyvQZme8F+0ksngnGbVacssMOE3rsxRpgnbeXDeYDlK4smOWLkxEqMvYal+Ri5 Syi2AErteFbmdvrI82VOswdoe5BmP1FjxW2lzWzUPUOGzRr+Ob1pXivBanxV8PV2x1Y3 DWfg== X-Gm-Message-State: APjAAAUDKWkQKWMwRU25sJDk02C6trwKag/h61mhWXl4x2eIrDF3Wwbj 2oiAJwyU/kJAdW1kvAQenbkiYy+eIJ8= X-Google-Smtp-Source: APXvYqzm+dLGm04PhZP90PUOe1RlbNFmTnkOVLuOR4o+mgXkM6dyAVsoYAy56Epw+4GmBpEYL8VQaA== X-Received: by 2002:a17:902:b110:: with SMTP id q16mr21893813plr.262.1569874910293; Mon, 30 Sep 2019 13:21:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 18/22] tcg/ppc: Update vector support for v2.07 VSX Date: Mon, 30 Sep 2019 13:21:21 -0700 Message-Id: <20190930202125.21064-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional only on MSR.VSX and are thus part of the VSX instruction set, and not Altivec. This includes double-word loads and stores. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index bc3a669cb4..6321e0767f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -470,10 +470,12 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define LVEWX XO31(71) #define LXSDX (XO31(588) | 1) /* v2.06, force tx=3D1 */ #define LXVDSX (XO31(332) | 1) /* v2.06, force tx=3D1 */ +#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=3D1 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) #define STXSDX (XO31(716) | 1) /* v2.06, force sx=3D1 */ +#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=3D1 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -1156,6 +1158,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg ret, tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); break; } + if (have_isa_2_07 && have_vsx) { + tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); + break; + } tcg_debug_assert((offset & 3) =3D=3D 0); tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); shift =3D (offset - 4) & 0xc; @@ -1203,6 +1209,11 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, tcg_out_mem_long(s, STW, STWX, arg, base, offset); break; } + if (have_isa_2_07 && have_vsx) { + tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); + break; + } + assert((offset & 3) =3D=3D 0); tcg_debug_assert((offset & 3) =3D=3D 0); shift =3D (offset - 4) & 0xc; if (shift) { --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875197; cv=none; d=zoho.com; s=zohoarc; b=GBfsuTidUo53buC/nMU8Gkl9GgGev1fe1ehcJkVrs77JgW9YaEXOEjgBfM6zPdjFQauWFFu9DWWck0ggksc/DSTiAN5QxczaMZxPn2JtbjS5zfiYkKHNtXd1ecGTO9TPRkEVzYaRYVCHIfezNlEYamgmDfSYGoDFnjVDa/sNCfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875197; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=TMW87VFE4aaAyrSbIdPCRdi4/pYOXWGaazKqSKeXpbw=; b=lYrSddfjOTriYGc/T+M9/bmHISz/oFI/v9Q5owbIvX7guj1OouXlMk/PhNpFcjLonvO+AU+XhYkl7u2tV21MJTT4LkgUCdlr+OLvjqK9kUbVaHnT7uZC2UTIU2pKQ/r5doGxI5xNS8tVGo6Elq9keM7DIor3jxX9tUpqFm8C8Nw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875197221474.74507114323774; Mon, 30 Sep 2019 13:26:37 -0700 (PDT) Received: from localhost ([::1]:56864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Ff-0001Ex-FH for importer@patchew.org; Mon, 30 Sep 2019 16:26:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45004) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B8-0004v6-D5 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B7-0005lw-6A for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:54 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:38699) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B6-0005l4-W9 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:53 -0400 Received: by mail-pl1-x642.google.com with SMTP id w8so3870347plq.5 for ; Mon, 30 Sep 2019 13:21:52 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TMW87VFE4aaAyrSbIdPCRdi4/pYOXWGaazKqSKeXpbw=; b=J2nsgtmPn7O7GLLpoThqsZ/VHa3QUECjSVzu1gMkiASuSuQDUeXPHrPkBZTvFh41Fa hs9yuJH81IDxT8XgbyuwK4B1gziMu+Yq9/3+AUQ00xD/3HEqvQvFOuQE/LFAL144UfSk Db0SmRO3cQH29mUJVtZ/cyL3aFBT1bmXo90+rjo6IbOOfMpPNbI5GeiRXplcmN5dq3gU YOHTcWQAWsaW7/East5MPMZ3cbr7bEESYgxRKcj0j0tIZJdoDjMa0jRxGMF7+qIFzNtK yWD2dKq3p5Bm91TYMxeju81r3nCZ2YtrOjIMPWqi1BI94imk4uRkJ1laGNtPFN+6PqXP aoeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TMW87VFE4aaAyrSbIdPCRdi4/pYOXWGaazKqSKeXpbw=; b=r5oVmQR6r490GzxaDX1K4A6RtnX93s7IsbAVL/S2sAYKMepux2m/osirPh8mC9k3u3 ziJfFXLSJk3UyruvufLoGoChf74rgwChJEhths8zc0wyNnnCwlYyfyTxeP0fQBnuxT+Q 0SbId0PsNZW3qCcRPZSiZxmpzGllQ1kLglyx5rgcrXi6J1zOLoiYH+yFcLPwoEC+6HwG BSw7gU7++p9z8+B0ojWvVs8/8gKsBX0h+mFg/whD0EnaZ+69S7i7wkwG3Sak5aA58aFU 7+yq0rCtzNArHilBnIGJXlNgCeRTjzl585sMR1bwD0FAk+GYmJ0kqPfy+GNPgICB5gEc 6j9A== X-Gm-Message-State: APjAAAXuRjfjtPup9wCb+Q90IrJur7X9tDZe7I9Vw/9AoxSyq3ef47OL AhUAD8RqL6mYQvzWTGsi+N+CTQpGnyY= X-Google-Smtp-Source: APXvYqxBicyedOkSiIvbrK/WQWNOR16mrc7jSRHGVMGosn13GSd4OdsSWc1pDs1ooZvdm12nd2LV2w== X-Received: by 2002:a17:902:6b02:: with SMTP id o2mr22102443plk.302.1569874911637; Mon, 30 Sep 2019 13:21:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 19/22] tcg/ppc: Update vector support for v2.07 FP Date: Mon, 30 Sep 2019 13:21:22 -0700 Message-Id: <20190930202125.21064-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional on MSR.FP when TX=3D0 and MSR.VEC when TX=3D1. Since we only care about the Altivec registers, and force TX=3D1, we can consider these to be Altivec instructions. Since Altivec is true for any use of vector types, we only need test have_isa_2_07. This includes moves to and from the integer registers. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 6321e0767f..840464aab5 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -586,6 +586,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=3Dbx=3Dt= x=3D1 */ #define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=3Dbx=3Dc= x=3Dtx=3D1 */ =20 +#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=3D1 */ +#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=3D1 */ +#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=3D1 */ +#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=3D1 */ + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -715,12 +720,27 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); /* fallthru */ case TCG_TYPE_I32: - if (ret < TCG_REG_V0 && arg < TCG_REG_V0) { - tcg_out32(s, OR | SAB(arg, ret, arg)); - break; - } else if (ret < TCG_REG_V0 || arg < TCG_REG_V0) { - /* Altivec does not support vector/integer moves. */ - return false; + if (ret < TCG_REG_V0) { + if (arg < TCG_REG_V0) { + tcg_out32(s, OR | SAB(arg, ret, arg)); + break; + } else if (have_isa_2_07) { + tcg_out32(s, (type =3D=3D TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) + | VRT(arg) | RA(ret)); + break; + } else { + /* Altivec does not support vector->integer moves. */ + return false; + } + } else if (arg < TCG_REG_V0) { + if (have_isa_2_07) { + tcg_out32(s, (type =3D=3D TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) + | VRT(ret) | RA(arg)); + break; + } else { + /* Altivec does not support integer->vector moves. */ + return false; + } } /* fallthru */ case TCG_TYPE_V64: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569875556; cv=none; d=zoho.com; s=zohoarc; b=O2qQ7/a2+o4ALgXWoiet3JNvwc0kUHIbr7Xk4UvifPFEubkhBwkm0q9Vy6FuCmVSEwu5ih5RcJAxqpigGdKrt8KWTYfJuxG5ZRYJZV7jojYYvyoorcDzz2T2PYTMVHA1vrKTuWmsi+pBAHvc+P1yJwCs6iIfssGSSBoxq8dtRy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569875556; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Cci9veTgtcLoAvyGrfQMINQKyTlVjrX+2t66fnd3opE=; b=aCBhn4WAqmbGViZM16iFTPoQqzq684lHTPQC5wzEgS3ZpuA0XffQTR+aOBrybOMvdb4jXtHhCGuWXvA72pWVG/9gXv73xtajg77IqkbXyJii+9KkTw40Zy7MxezWTMwXLFUdBHZUHjOdmJqWtsv3+nhraaIrOCtiYD2EQPf9fFw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569875556272778.7414813512578; Mon, 30 Sep 2019 13:32:36 -0700 (PDT) Received: from localhost ([::1]:56936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2LR-0006Bc-Dk for importer@patchew.org; Mon, 30 Sep 2019 16:32:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45025) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2B9-0004ws-Kj for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B8-0005oK-Bd for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:55 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:37033) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B8-0005o0-64 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:54 -0400 Received: by mail-pg1-x544.google.com with SMTP id c17so8001551pgg.4 for ; Mon, 30 Sep 2019 13:21:54 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cci9veTgtcLoAvyGrfQMINQKyTlVjrX+2t66fnd3opE=; b=v2LM3FdiLSTrNZWBFNixompm+O/X9LAqHsU0a9F5oL4ywBSSV87p+r3wbcQq/aKu3s RXgHzWeYjH5WBMiMNlzwV/zuPUZqiF+XbcUhw/zSVE1guCc0PPwDQjLAfUP9ZOxtxmBV z+ziOZaM68LeAf0x60Wk2a93YQNd763Kkip2DWzfmw/cIU12RpkAXhqg56wqCM2Nd+tQ evLISv48YkfzuWRKgQd+ZJTIoEudVHjSzOCQf3nHnCsNTuzKjGrBYdXhJ8jqkcJpO/hd 6rL9LEuTbHk2BiIfhbZCLQoughHJKqUlbzxRHPzEKz50wdC51MLHcKpyMZLEZrUqfz65 ja6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cci9veTgtcLoAvyGrfQMINQKyTlVjrX+2t66fnd3opE=; b=VITR6wioXwoyFMqIy3/62ik0UMGL0yEgknpuZFgA9sMWycn5v0PezQujs0UTrI39/p Hnf1Sq4r22kYV+nc7b1UZulthKmcVTckORvWFcoarrgzlArT/u4MDfxUgtTdCeyik/oD ckk+7HL0vDX/wffH6ewKOKHv1BmnmNZ4oHA4uvTRUnBgX8j5HjRiYHc0rrR6I39xocCy 64XsOa+z8cRrn/OfXdLhQoEPyRug814UXvZm27tUsojT37wYyHEhHLiLtHgL1LkRayfP fkYxCWju00CQk/iGMw6UC7l9RHCxFvWdua0zq2f1uTVWK7atGaX5n/M4Qj7qhPJ31O9X 60CA== X-Gm-Message-State: APjAAAVbR0mO9L0HHrtZacyZWnD6C0+cM4oOPR72UJT225k9r0RVLiIu P/pMqUEvc7f4Lw21drYEFyHjvecPAN0= X-Google-Smtp-Source: APXvYqxwHdOcegh0z6KVaSBY4WklJQwWFG46mL6A46CEPv8nAffrIRNoUzoGxB2z6mHLmTs30KnI/w== X-Received: by 2002:a17:90a:7d06:: with SMTP id g6mr1099175pjl.53.1569874912837; Mon, 30 Sep 2019 13:21:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 20/22] tcg/ppc: Update vector support for v3.00 Altivec Date: Mon, 30 Sep 2019 13:21:23 -0700 Message-Id: <20190930202125.21064-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional only on MSR.VEC and are thus part of the Altivec instruction set, and not VSX. This includes negation and compare not equal. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 13197eddce..4fa21f0e71 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -159,7 +159,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_andc_vec 1 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 #define TCG_TARGET_HAS_not_vec 1 -#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_neg_vec have_isa_3_00 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 840464aab5..bd9259c60f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -499,6 +499,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VSUBUWM VX4(1152) #define VSUBUDM VX4(1216) /* v2.07 */ =20 +#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ +#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ + #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) @@ -528,6 +531,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) #define VCMPGTUD VX4(711) /* v2.07 */ +#define VCMPNEB VX4(7) /* v3.00 */ +#define VCMPNEH VX4(71) /* v3.00 */ +#define VCMPNEW VX4(135) /* v3.00 */ =20 #define VSLB VX4(260) #define VSLH VX4(324) @@ -2976,6 +2982,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shri_vec: case INDEX_op_sari_vec: return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_neg_vec: + return vece >=3D MO_32 && have_isa_3_00; case INDEX_op_mul_vec: switch (vece) { case MO_8: @@ -3090,7 +3098,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, static const uint32_t add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + neg_op[4] =3D { 0, 0, VNEGW, VNEGD }, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, @@ -3132,6 +3142,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_neg_vec: + insn =3D neg_op[vece]; + a2 =3D a1; + a1 =3D 0; + break; case INDEX_op_mul_vec: tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07); insn =3D VMULUWM; @@ -3194,6 +3209,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case TCG_COND_EQ: insn =3D eq_op[vece]; break; + case TCG_COND_NE: + insn =3D ne_op[vece]; + break; case TCG_COND_GT: insn =3D gts_op[vece]; break; @@ -3276,6 +3294,10 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, case TCG_COND_GTU: break; case TCG_COND_NE: + if (have_isa_3_00 && vece <=3D MO_32) { + break; + } + /* fall through */ case TCG_COND_LE: case TCG_COND_LEU: need_inv =3D true; @@ -3599,6 +3621,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: + case INDEX_op_neg_vec: case INDEX_op_dup_vec: return &v_v; case INDEX_op_ld_vec: --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569876215; cv=none; d=zoho.com; s=zohoarc; b=PX+azRVx8qIWJ0vyl0NC5fpuUkAUW3L/V7QVxV+6tOlCibdS5Yq7m0JjhjKb9R8qn7xxUINs5eKmRVtwXsD2hGSJnm4azN8hh7EjtrzGeNpyqEztGA4ZHPTC6c6m+vCmSWO2dUHMLfpGUQQEaKfAGmGx+9tkPqvFNXKgJ2XnA9g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569876215; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=HeKQyFXdAD3p3CrTgUxvWn1tBUXGzKhYow9Z2REu0SA=; b=PgOYgnt7C4DboKh0f3aOQgkaoIolET/lNgxtBgDLBdt37QI3EB/dOE2s9FPeKca0GKhT69Tl6cF0TQropJmaxEGH6ov9G6wbkCttQr135tH/fTU2D3wGB4iqHYLD9Uq06khJXt3u7EuxxAOPY17CnE5CDBjTF+hsCjgKatzYvIU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569876215156263.9934090937419; Mon, 30 Sep 2019 13:43:35 -0700 (PDT) Received: from localhost ([::1]:57086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2W5-0000X2-IX for importer@patchew.org; Mon, 30 Sep 2019 16:43:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45043) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2BB-0004z2-4b for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2B9-0005p1-Mn for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:56 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46086) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2B9-0005od-H6 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:55 -0400 Received: by mail-pf1-x444.google.com with SMTP id q5so6210085pfg.13 for ; Mon, 30 Sep 2019 13:21:55 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HeKQyFXdAD3p3CrTgUxvWn1tBUXGzKhYow9Z2REu0SA=; b=g59BHi7ycK/1gMeFlt/v4xzFWBdRUbi7mfa3y9F+6hERZR5K9L9wkBWsYq7yeYBKn/ 01pJC3XyLSmFNSRSwgpigmkoyX12o8xyGRs0IY9bDlq9Di3GnN0+XcKA/xfNah7rOdVO 42mGMN5CDmU7cByM+587JMyNoUgBWdFq93jc16Jw4pQUP8w7UMfGn56yhS1b7WKiL59e AjCaqb8nC0V0v30gcKMPGXpIOf2GNboYnJIqYh7jHsFoUOoxmmPB0ym/O+MTiIf/1R5f uVHvbIdl0ujPqEODORAjMOCRppPdFlXGcdEZiGnJZHBykTw5v1LOt7fMmWTVPGzUXVnR Hvmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HeKQyFXdAD3p3CrTgUxvWn1tBUXGzKhYow9Z2REu0SA=; b=nF0HHB34lPE/N/TuxIP8RRsKL+Ux+4P0asmvWdnV+bNW2w4BWdG91Fe/bp1wjcdrTd 03VniPP3YCQtc3YFurzzqoFRMSKbOincwGjvVu4RFvci3A6OKY4KoVmNvw2k0m9X62sh Xq2ADmR9TPnWmU5670WvZRDN5T0DMIF+C8bm1amktt53F6DvOPuYJrS+X7u934G5WDoV CWAomWGnU/MgiaAfcK2zVddVZUfElgB/yjtHtAD486k0R+0uaV/20bm3pvYksRYRhktb QgL1BXXrMJQ4wiqTGTevpKLKPsf4Nv5/hOOZh/V5Q8CbmtXsJjsZBKskBzEa116QujGs z4uA== X-Gm-Message-State: APjAAAV0HlHU/+RZWIwvzQdIyeSDop0vnLlRSzhjj2Gt4xkGqbEE0Eqn G74LVZpGk1hvkNzL1y0xVvI23t2GsZI= X-Google-Smtp-Source: APXvYqw7/UEveRUTPCVrQFPxvy/bPjTo9PEGewxq2Rd3gDL1z3a9AWG4mR4sT1kmHKTKkBjSXfI5mA== X-Received: by 2002:a17:90a:5ae4:: with SMTP id n91mr1122499pji.143.1569874914139; Mon, 30 Sep 2019 13:21:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 21/22] tcg/ppc: Update vector support for v3.00 load/store Date: Mon, 30 Sep 2019 13:21:24 -0700 Message-Id: <20190930202125.21064-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are a mix of those like LXSD that are only conditional only on MSR.VEC and those like LXV that are conditional on MSR.VEC for TX=3D1. Thus, in the end, we can consider all of these as Altivec instructions. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 47 ++++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index bd9259c60f..5b7d1bd2dc 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -471,11 +471,16 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define LXSDX (XO31(588) | 1) /* v2.06, force tx=3D1 */ #define LXVDSX (XO31(332) | 1) /* v2.06, force tx=3D1 */ #define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=3D1 */ +#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=3D1 */ +#define LXSD (OPCD(57) | 2) /* v3.00 */ +#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=3D1 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) #define STXSDX (XO31(716) | 1) /* v2.06, force sx=3D1 */ #define STXSIWX (XO31(140) | 1) /* v2.07, force sx=3D1 */ +#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=3D1 */ +#define STXSD (OPCD(61) | 2) /* v3.00 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -1114,7 +1119,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, = int opx, TCGReg rt, TCGReg base, tcg_target_long offset) { tcg_target_long orig =3D offset, l0, l1, extra =3D 0, align =3D 0; - bool is_store =3D false; + bool is_int_store =3D false; TCGReg rs =3D TCG_REG_TMP1; =20 switch (opi) { @@ -1127,11 +1132,19 @@ static void tcg_out_mem_long(TCGContext *s, int opi= , int opx, TCGReg rt, break; } break; + case LXSD: + case STXSD: + align =3D 3; + break; + case LXV: + case STXV: + align =3D 15; + break; case STD: align =3D 3; /* FALLTHRU */ case STB: case STH: case STW: - is_store =3D true; + is_int_store =3D true; break; } =20 @@ -1140,7 +1153,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, = int opx, TCGReg rt, if (rs =3D=3D base) { rs =3D TCG_REG_R0; } - tcg_debug_assert(!is_store || rs !=3D rt); + tcg_debug_assert(!is_int_store || rs !=3D rt); tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); tcg_out32(s, opx | TAB(rt & 31, base, rs)); return; @@ -1205,7 +1218,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, case TCG_TYPE_V64: tcg_debug_assert(ret >=3D TCG_REG_V0); if (have_vsx) { - tcg_out_mem_long(s, 0, LXSDX, ret, base, offset); + tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, + ret, base, offset); break; } tcg_debug_assert((offset & 7) =3D=3D 0); @@ -1217,7 +1231,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, case TCG_TYPE_V128: tcg_debug_assert(ret >=3D TCG_REG_V0); tcg_debug_assert((offset & 15) =3D=3D 0); - tcg_out_mem_long(s, 0, LVX, ret, base, offset); + tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, + LVX, ret, base, offset); break; default: g_assert_not_reached(); @@ -1258,7 +1273,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, case TCG_TYPE_V64: tcg_debug_assert(arg >=3D TCG_REG_V0); if (have_vsx) { - tcg_out_mem_long(s, 0, STXSDX, arg, base, offset); + tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, + STXSDX, arg, base, offset); break; } tcg_debug_assert((offset & 7) =3D=3D 0); @@ -1271,7 +1287,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, break; case TCG_TYPE_V128: tcg_debug_assert(arg >=3D TCG_REG_V0); - tcg_out_mem_long(s, 0, STVX, arg, base, offset); + tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, + STVX, arg, base, offset); break; default: g_assert_not_reached(); @@ -3042,7 +3059,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType = type, unsigned vece, tcg_debug_assert(out >=3D TCG_REG_V0); switch (vece) { case MO_8: - tcg_out_mem_long(s, 0, LVEBX, out, base, offset); + if (have_isa_3_00) { + tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); + } else { + tcg_out_mem_long(s, 0, LVEBX, out, base, offset); + } elt =3D extract32(offset, 0, 4); #ifndef HOST_WORDS_BIGENDIAN elt ^=3D 15; @@ -3051,7 +3072,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType = type, unsigned vece, break; case MO_16: tcg_debug_assert((offset & 1) =3D=3D 0); - tcg_out_mem_long(s, 0, LVEHX, out, base, offset); + if (have_isa_3_00) { + tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); + } else { + tcg_out_mem_long(s, 0, LVEHX, out, base, offset); + } elt =3D extract32(offset, 1, 3); #ifndef HOST_WORDS_BIGENDIAN elt ^=3D 7; @@ -3059,6 +3084,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType = type, unsigned vece, tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); break; case MO_32: + if (have_isa_3_00) { + tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); + break; + } tcg_debug_assert((offset & 3) =3D=3D 0); tcg_out_mem_long(s, 0, LVEWX, out, base, offset); elt =3D extract32(offset, 2, 2); --=20 2.17.1 From nobody Sun May 12 07:29:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1569876446; cv=none; d=zoho.com; s=zohoarc; b=UPtXtI9MGFKMrcLjrgGu0zxbXQue/HBa/EId3cmqZKa8o7MZNUCPzenfW0fR+Lx5Hw6kpOpsUsoFK8zmI5Hk0IGXMhDOoy1aOpnD90OUVwzK85SGH7D8BIZY4vqmlqQPC6B6ugrIbUh2+kWmIFCighSiOTTskgYj2604dooZ+zI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569876446; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BGOdnUQ7n88wshKpceGoTB4ILfGRgsQjpAICNmjMH9Y=; b=Mewz4wLOlvu0D4fXs0i849n1CCr6JdlHj6vBnj04SGo3NNQ56AEk2ubBQvwhUq1y6tGYJUcb29mxg/683zjTb7Q0qUqFLvQnT84MZfPg6F64Ej+l1dVBA65y1T9I7GQtNBReqSPezP5s8elBSJw8JahX7gMrQC3u18g5obPTUrg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569876445970330.7745065421784; Mon, 30 Sep 2019 13:47:25 -0700 (PDT) Received: from localhost ([::1]:57128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2Zo-0003C8-Ch for importer@patchew.org; Mon, 30 Sep 2019 16:47:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45058) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iF2BC-00050M-43 for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iF2BA-0005pW-SF for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:57 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iF2BA-0005p9-MX for qemu-devel@nongnu.org; Mon, 30 Sep 2019 16:21:56 -0400 Received: by mail-pf1-x443.google.com with SMTP id h195so6232119pfe.5 for ; Mon, 30 Sep 2019 13:21:56 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id r28sm15336802pfg.62.2019.09.30.13.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:21:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BGOdnUQ7n88wshKpceGoTB4ILfGRgsQjpAICNmjMH9Y=; b=mieC1GDejv/UZEP3ApfvREDw5Bmg/f7WChqK9wp2Dqhm/fSkuwefySH+bVl1dIpvT7 5jeHSy5LNuxd1R24thDVO8ukY3Bjui5XYXduOATSrCCv5SPOqMyDOe7sokYlj1OLDlnw V+q2HJWQziD90WnGhdC79KxhizabEnUm2wK6BKbThWpYNdnm5QsZrjDmnHHD9NMThMYj UzlKsCybinoq5vDiH2TAx7q9VUlKYsGWl2Nn3UZssJsrOz4+TpxAb97T9XXDRmA1SIJq e3CK3RRZaUGgI7dBk8WybvIVVT1EM+Ehu7kpScgYcYxDynIpenG8l9gpyJqK3BOw4AjZ fSpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BGOdnUQ7n88wshKpceGoTB4ILfGRgsQjpAICNmjMH9Y=; b=a8C62K5Z3qA0uS4xtTUzTS9xu4XM1jZuSmkyUOwaXJflk+b97tPFIpgFlku3hoYnB5 w0wuVxwgT3RrydthGKHoCShtuJtudvhOlMrMVNhlyrP+IA89uxWCXD3b9nNULh98oqQq iPgQJWms+jNONHwBgMYnBtpQtVLz4BvQNtXpslp9Oo9uLsHRVxjRhCmXFFj8kxr1vldt AxEXwiD3VO/FQGt/G5yQ5fE9lPL3sfz8QuP+PzsRUuRNCJTAv5rtSO/JtzgG12VOedsI XbXZh0in7w9do30T1+nKpllo1gmL7TnbRET15toCW6pG8KCAMLYTELegLvq70LbSVPEB 4Hkw== X-Gm-Message-State: APjAAAUcsdODnH8CUgm+NWVJTSKaRYGdiLvMzoVr7auy9WrId6We69y7 hb+uyOhbsRnYhG0wF53Q4xnJFMp2sxg= X-Google-Smtp-Source: APXvYqyao1mwnDBuz0kXimarnkqAgAAxi0vvirb8CZmni874A1EQOv5NakBFwC4FGZZmg41BBBl1Rw== X-Received: by 2002:a17:90a:2687:: with SMTP id m7mr1135371pje.25.1569874915433; Mon, 30 Sep 2019 13:21:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 22/22] tcg/ppc: Update vector support for v3.00 dup/dupi Date: Mon, 30 Sep 2019 13:21:25 -0700 Message-Id: <20190930202125.21064-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org> References: <20190930202125.21064-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These new instructions are conditional on MSR.VEC for TX=3D1, so we can consider these Altivec instructions. Signed-off-by: Richard Henderson Reviewed-by: Aleksandar Markovic Tested-by: Mark Cave-Ayland (PPC32) --- tcg/ppc/tcg-target.inc.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 5b7d1bd2dc..d308d69aba 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -596,11 +596,14 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, =20 #define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=3Dbx=3Dt= x=3D1 */ #define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=3Dbx=3Dc= x=3Dtx=3D1 */ +#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=3D1 */ =20 #define MFVSRD (XO31(51) | 1) /* v2.07, force sx=3D1 */ #define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=3D1 */ #define MTVSRD (XO31(179) | 1) /* v2.07, force tx=3D1 */ #define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=3D1 */ +#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=3D1 */ +#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=3D1 */ =20 #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) @@ -931,6 +934,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType ty= pe, TCGReg ret, return; } } + if (have_isa_3_00 && val =3D=3D (tcg_target_long)dup_const(MO_8, val))= { + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); + return; + } =20 /* * Otherwise we must load the value from the constant pool. @@ -3021,7 +3028,22 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType t= ype, unsigned vece, TCGReg dst, TCGReg src) { tcg_debug_assert(dst >=3D TCG_REG_V0); - tcg_debug_assert(src >=3D TCG_REG_V0); + + /* Splat from integer reg allowed via constraints for v3.00. */ + if (src < TCG_REG_V0) { + tcg_debug_assert(have_isa_3_00); + switch (vece) { + case MO_64: + tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); + return true; + case MO_32: + tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); + return true; + default: + /* Fail, so that we fall back on either dupm or mov+dup. */ + return false; + } + } =20 /* * Recall we use (or emulate) VSX integer loads, so the integer is @@ -3482,6 +3504,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; + static const TCGTargetOpDef v_vr =3D { .args_ct_str =3D { "v", "vr" } = }; static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; static const TCGTargetOpDef v_v_v_v @@ -3651,8 +3674,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &v_v_v; case INDEX_op_not_vec: case INDEX_op_neg_vec: - case INDEX_op_dup_vec: return &v_v; + case INDEX_op_dup_vec: + return have_isa_3_00 ? &v_vr : &v_v; case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_dupm_vec: --=20 2.17.1