From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15528138572248.103031722380251; Sun, 17 Mar 2019 02:10:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:52109 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Roh-0007AO-R7 for importer@patchew.org; Sun, 17 Mar 2019 05:10:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmb-0005bq-RK for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rma-00045N-C5 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:41 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:41137) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5RmZ-00043a-UJ for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:40 -0400 Received: by mail-pf1-x443.google.com with SMTP id d25so9218896pfn.8 for ; Sun, 17 Mar 2019 02:08:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hodYlcpRqUFAyF1u9EayD/KhJ3+IN8OK9GoDdoOHadc=; b=sg/YFPkJc52rgWQSSHVmujtSIe3QcNEJx+qFQJgxLNu6itx8oXd+olblfinDiNc8f9 BY/vQMLViTEQyDtjl6F8LdExhQeeTEPEoJTwqBWheWW+oFk1R0xGC6VGQ7zQnLRoEhVv 4R0oGc36Gkhxz/IJCnqAi69QAmCsrQoVAOl3RNNgP26u5dF2Nx6y/Y9k9pfDdQxYvNnC U4e2lZWgYkz/yrPCjJ8cvAyOSYm4HpNVdsKk8oBJrckHRovlfUrQdk0sMJTP8qWR5Vuh l+d6aiIuuPWz8nayW7DWl2AZ1eywiTz4J8J+rfaTLE4olz0GQOMkOsy2SaeC5MvhlxXc DG1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hodYlcpRqUFAyF1u9EayD/KhJ3+IN8OK9GoDdoOHadc=; b=WChpNUydcPDgMIi35E26t5cKscgO/R3rkO4zTaxBJjNP2k/HUm5PN3XHObf2JpyCfG QvNp9g4vYvjblAitXKKauY/atlpP+kdv1CsEvjBfduOa0F+GtRvzTwj6E6iIWvMIMvyl nnZpxsfY4Kdqk8BFZQzoMoETQqAHi/Vx9S3D5hGsDyUN/dQrJXtLKypEwcy+TXrKADnL ItIra5HOYXRA7r/pwDB7JWAylpagUmsPh+SexgRwmtONZoJlVJ2rIffnxUtd/Dya49Vq u1whMA/RTOb1npWPh8G+PrvsdJeAjuyE7b9FzbL50Soq0jNpoSoZVdM7Z55Nf2TXLCQn Wy9w== X-Gm-Message-State: APjAAAXAmh/S1dvQYq1ous72jmOnU/oHKCnJFBVrEjhsCF77zLYVwrhw 2ctOOgdW3lryvTqxJKwvjCL08IWaaHY= X-Google-Smtp-Source: APXvYqy4mhdtfmu+hY3Ca0u8+Enkx97nvWf+gatxbWJDLsM8mpFZpC3qZykQbt3hVoirvX7gOe+pfw== X-Received: by 2002:a17:902:1121:: with SMTP id d30mr13887081pla.104.1552813718215; Sun, 17 Mar 2019 02:08:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:22 -0700 Message-Id: <20190317090834.5552-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.1 v2 01/13] tcg: Assert fixed_reg is read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Signed-off-by: Richard Henderson --- tcg/tcg.c | 85 +++++++++++++++++++++++++------------------------------ 1 file changed, 38 insertions(+), 47 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 9b2bf7f439..6f320a4849 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3275,11 +3275,8 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCG= Temp *ots, tcg_target_ulong val, TCGLifeData arg_li= fe, TCGRegSet preferred_regs) { - if (ots->fixed_reg) { - /* For fixed registers, we do not do any constant propagation. */ - tcg_out_movi(s, ots->type, ots->reg, val); - return; - } + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); =20 /* The movi is not explicitly generated here. */ if (ots->val_type =3D=3D TEMP_VAL_REG) { @@ -3315,6 +3312,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) ots =3D arg_temp(op->args[0]); ts =3D arg_temp(op->args[1]); =20 + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); + /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; itype =3D ts->type; @@ -3339,7 +3339,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } =20 tcg_debug_assert(ts->val_type =3D=3D TEMP_VAL_REG); - if (IS_DEAD_ARG(0) && !ots->fixed_reg) { + if (IS_DEAD_ARG(0)) { /* mov to a non-saved dead register makes no sense (even with liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); @@ -3352,7 +3352,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } temp_dead(s, ots); } else { - if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { + if (IS_DEAD_ARG(1) && !ts->fixed_reg) { /* the mov can be suppressed */ if (ots->val_type =3D=3D TEMP_VAL_REG) { s->reg_to_temp[ots->reg] =3D NULL; @@ -3505,6 +3505,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if ((arg_ct->ct & TCG_CT_ALIAS) && !const_args[arg_ct->alias_index]) { reg =3D new_args[arg_ct->alias_index]; @@ -3513,29 +3517,19 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); } else { - /* if fixed register, we try to use it */ - reg =3D ts->reg; - if (ts->fixed_reg && - tcg_regset_test_reg(arg_ct->u.regs, reg)) { - goto oarg_end; - } reg =3D tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); - /* if a fixed register is used, then a move will be done after= wards */ - if (!ts->fixed_reg) { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - /* temp value is modified, so the value kept in memory is - potentially not the same */ - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; } - oarg_end: + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + /* temp value is modified, so the value kept in memory is + potentially not the same */ + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; new_args[i] =3D reg; } } @@ -3551,10 +3545,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { ts =3D arg_temp(op->args[i]); - reg =3D new_args[i]; - if (ts->fixed_reg && ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); } else if (IS_DEAD_ARG(i)) { @@ -3675,26 +3669,23 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) for(i =3D 0; i < nb_oargs; i++) { arg =3D op->args[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); - - if (ts->fixed_reg) { - if (ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } - } else { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; - if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); - } else if (IS_DEAD_ARG(i)) { - temp_dead(s, ts); - } + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; + } + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; + if (NEED_SYNC_ARG(i)) { + temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); + } else if (IS_DEAD_ARG(i)) { + temp_dead(s, ts); } } } --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=673pHgTWT8QRtFd/5n9jHy6LBEG0yAkhBqL83UHJaJU=; b=zvV93P6WHCkatLgm91FJiuCHRbbz+mxXfVpoKQaGjDBA8lk3MTMqqeU6XM/ztvvLnh VdxO3nsDKRsIfj8nG/A9ZzMNAgRixl3GXSM1DYsCiynxYuSeF4w3w5oTLjwm+1/XdNwD JTteGC3pJKTMJ4GoAiYEzeA6DIVw5HiR5Tgr0JJeNXTqLvYl+7qScE7xlsK/iB5KXqVl 3SNv6gpqJwpT1hpy20PH6t+3rT79FplvJk1GQ1/urC3DVnLC+pEEMsfpd5kwp35618mO Gzd01k/cdgKnB7L8kF7853UfKJ4rUKp+z1MKpYG+AGVPHKWUvfGRTJIBsTWNO54oj/Ds EQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=673pHgTWT8QRtFd/5n9jHy6LBEG0yAkhBqL83UHJaJU=; b=i/2GBfGKYUl2IZeaaAVyiycKgq2F3wDwKCprYW961J8PmkftGLhyG4e/hq75z4v3xu kBz5KfYbWKLRWapYnmv0lf7Y0lWtv7/4WfPcGzy9kwhRDa9AMkiIKxHGnCdGmtubNzB3 bA1VukJPvO9zkVVcwhaaU0Ai4bh4Y+AHGd8oifmHe4lbuJQnkyUC1At5af3LtJoObwqT ARSj31RNgi5iZ2MEXeFefr+Jd90tsDBLOEoXFsJJcu0bDAk4RgWsqGyDepcmAYlHMF09 HBMkeSLd7AW83/pL0XVLA+4GA3hzG4txnePQTD/jkRTZ6JqLJs1dVxyLqOTCWggQiDPh uXhA== X-Gm-Message-State: APjAAAXaKFYVeQ7Vv6TraKHeo/DB9eZe9x1NbPo3jc3i2zJDNs9CK0uw 1VQ6zuruLfuXieCUTv0zYvA4hBZ9fqY= X-Google-Smtp-Source: APXvYqy3Jsk7di1/FQPY2REqEuqXsjRx0OfAFstSlc1yW6JnqD6XzwHac7ZY4YllE9tsm3P+EwRrLA== X-Received: by 2002:a65:60c1:: with SMTP id r1mr12076302pgv.137.1552813719715; Sun, 17 Mar 2019 02:08:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:23 -0700 Message-Id: <20190317090834.5552-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH for-4.1 v2 02/13] tcg: Return bool success from tcg_out_mov X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch merely changes the interface, aborting on all failures, of which there are currently none. Signed-off-by: Richard Henderson Reviewed-by: David Gibson --- tcg/aarch64/tcg-target.inc.c | 5 +++-- tcg/arm/tcg-target.inc.c | 7 +++++-- tcg/i386/tcg-target.inc.c | 5 +++-- tcg/mips/tcg-target.inc.c | 3 ++- tcg/ppc/tcg-target.inc.c | 3 ++- tcg/riscv/tcg-target.inc.c | 5 +++-- tcg/s390/tcg-target.inc.c | 3 ++- tcg/sparc/tcg-target.inc.c | 3 ++- tcg/tcg.c | 14 ++++++++++---- tcg/tci/tcg-target.inc.c | 3 ++- 10 files changed, 34 insertions(+), 17 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index d57f9e500f..6ba9050d9a 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -938,10 +938,10 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -970,6 +970,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2245a8aeb9..b303befa50 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2250,10 +2250,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTy= pe type, TCGArg val, return false; } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0)); + if (ret !=3D arg) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(= 0)); + } + return true; } =20 static inline void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e0670e5098..7100cf7ac3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -808,12 +808,12 @@ static inline void tgen_arithr(TCGContext *s, int sub= op, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { int rexw =3D 0; =20 if (arg =3D=3D ret) { - return; + return true; } switch (type) { case TCG_TYPE_I64: @@ -851,6 +851,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 8a92e916dd..f31ebb43bf 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -558,13 +558,14 @@ static inline void tcg_out_dsra(TCGContext *s, TCGReg= rd, TCGReg rt, TCGArg sa) tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret !=3D arg) { tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 773690f1d9..ec8e336be8 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -566,12 +566,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); if (ret !=3D arg) { tcg_out32(s, OR | SAB(arg, ret, arg)); } + return true; } =20 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index b785f4acb7..e2bf1c2c6e 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -515,10 +515,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, * TCG intrinsics */ =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -528,6 +528,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 7db90b3bae..eb22188d1d 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -548,7 +548,7 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, = TCGReg dest, tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) { if (src !=3D dst) { if (type =3D=3D TCG_TYPE_I32) { @@ -557,6 +557,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg dst, TCGReg src) tcg_out_insn(s, RRE, LGR, dst, src); } } + return true; } =20 static const S390Opcode lli_insns[4] =3D { diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 7a61839dc1..83295955a7 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -407,12 +407,13 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, = TCGReg rs1, | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (ret !=3D arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); } + return true; } =20 static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 6f320a4849..34ee06564f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -102,7 +102,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, const char *ct_str, TCGType typ= e); static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, @@ -3368,7 +3368,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) allocated_regs, preferred_regs, ots->indirect_base); } - tcg_out_mov(s, otype, ots->reg, ts->reg); + if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { + abort(); + } } ots->val_type =3D TEMP_VAL_REG; ots->mem_coherent =3D 0; @@ -3468,7 +3470,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) i_allocated_regs, 0); reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } new_args[i] =3D reg; const_args[i] =3D 0; @@ -3625,7 +3629,9 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) if (ts->val_type =3D=3D TEMP_VAL_REG) { if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } } else { TCGRegSet arg_set =3D 0; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 0015a98485..992d50cb1e 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -509,7 +509,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; tcg_debug_assert(ret !=3D arg); @@ -521,6 +521,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) tcg_out_r(s, ret); tcg_out_r(s, arg); old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814034949610.3151245271719; Sun, 17 Mar 2019 02:13:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:52136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rrd-00017L-RK for importer@patchew.org; Sun, 17 Mar 2019 05:13:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rme-0005cE-15 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmc-00046u-Sy for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:43 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:43315) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmc-00046V-I7 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:42 -0400 Received: by mail-pf1-x430.google.com with SMTP id c8so2575372pfd.10 for ; Sun, 17 Mar 2019 02:08:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+1ZajJcyDX+UELwR6wwdOhI95L56RVVGuynDrcPGi6o=; b=oua6aqjv23rokNXdX59LeiVclUzvVCEYSBGWIyfW7uI8zhytVRbwsy7/Mhih59c1+N CaoZ1zQleljotf9mrPuuusMVEh5ZBmMf/LMUbbiHKot2FY7/cXXXDsxf1HisTQVoCEZF l7QNO1Kas0YLH8KU01AyYoymlZ2cuxEhEZNJyix0WS6Q86oK9fzqTWV9Bxy28cIhOEem GvEbDyjfPup/QKKN9Vtdr4PGKH/a4B6UaFyPdF8AW9GDXGou4+CgA+tYgaidXRFyYnW2 rw8RzwgBGz6jcurn+lRZPD0cC82F9Bo3+HIbQCUD7l3FJTXa+17pBbFWl2C9xFPf4D59 NWjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+1ZajJcyDX+UELwR6wwdOhI95L56RVVGuynDrcPGi6o=; b=sysaLffMiBZWJH5n7nLeMspZLpKJiah/77xNOLVy9Ip4R2Cew1IXCv/7hGDNsbl1xg wG+fRksfwwLUGsi2x8yENQVIs5fwJzg0LQW0rGOUwSydKlXt2PhKMVM2k+SNlDcqKP8a EFWI2JcORzWHAKP4XV4xYHjXQ4Nx4E6ntDotICGfPskHHuN4yieDf+ZddzczjziZV7qq +JizYnyfoDDaduagx/corm4miHH0br6ahSbBIGRJOOoWdXFtc4KwFX2vF4G2XcbGQXRX TGpljCLGaMEedh/skITrzO/yFon0IHGHzGk+Exr9/7AnYdVHRx1YLI9KaO+SjLSvuFA/ XXXg== X-Gm-Message-State: APjAAAWeFqUnkSL3p6Z74umUAcYNjuICLEwMHdh7jFO+Kpn0yAkM5akl f/N9H5aSxe54A0e5h+DB/+I/QS05HY4= X-Google-Smtp-Source: APXvYqzhwUMQNQ50RcNbQvLqXAzMSQQed08ii9clPFjm6vDTPIljAUIO10iMA5tdGkTmdigz7ZWBPQ== X-Received: by 2002:a65:60c7:: with SMTP id r7mr12480411pgv.37.1552813721226; Sun, 17 Mar 2019 02:08:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:24 -0700 Message-Id: <20190317090834.5552-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH for-4.1 v2 03/13] tcg: Support cross-class moves without instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Signed-off-by: Richard Henderson --- tcg/tcg.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 34ee06564f..b5389ea767 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3369,7 +3369,18 @@ static void tcg_reg_alloc_mov(TCGContext *s, const T= CGOp *op) ots->indirect_base); } if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { - abort(); + /* Cross register class move not supported. + Store the source register into the destination slot + and leave the destination temp as TEMP_VAL_MEM. */ + assert(!ots->fixed_reg); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ots); + } + tcg_out_st(s, ts->type, ts->reg, + ots->mem_base->reg, ots->mem_offset); + ots->mem_coherent =3D 1; + temp_free_or_dead(s, ots, -1); + return; } } ots->val_type =3D TEMP_VAL_REG; @@ -3471,7 +3482,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* Cross register class move not supported. Sync the + temp back to its slot and load from there. */ + temp_sync(s, ts, i_allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } new_args[i] =3D reg; @@ -3630,7 +3645,11 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* Cross register class move not supported. Sync = the + temp back to its slot and load from there. */ + temp_sync(s, ts, allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } } else { --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814035471444.5569483550063; Sun, 17 Mar 2019 02:13:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:52134 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rrc-00014b-F7 for importer@patchew.org; Sun, 17 Mar 2019 05:13:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmf-0005cZ-Ow for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rme-000496-EY for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:45 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:33020) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rme-00047O-3u for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:44 -0400 Received: by mail-pg1-x533.google.com with SMTP id i7so6118013pgq.0 for ; Sun, 17 Mar 2019 02:08:43 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GZIJyp4IPrmFxQhN2kp0EgDilGGl6wAJPSZllKgeFTA=; b=Fy9Au7kpULm9toqhBWajR2v+oa85vBzulSjqe6/0ZOw3ObAPnqLdiBxBnXhyJwZMqq nrUla9ZSXn7HUf4F5hkR4f0aPXTf5VQE/sifl91n/HHFkjgi2F2brfeBplcLV0fNTAMG 4Wlp7RKJuScGOrP81eRK8IeVW6chig2k3h/dmQV/yOTVCkVzkHSAn/b3IFPLHBbuh1/w mUC577JxzU/hYE4q71l9NfBxacNeS16lmmMtokrVz538DFd7rZ/3vmiQtDh1KKySYc8V V1JtKQIpeUT4/jUNp5ckO76m43dYNuReFB390LiimkJ298LjqSBlxMPkdBkR1YPPpBQS ru3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GZIJyp4IPrmFxQhN2kp0EgDilGGl6wAJPSZllKgeFTA=; b=lvKb8kkdX32lpdzXyCOqcU8NldTVSS6rFkC/hoakdXhlQscFIiTsODcpTbQZ5W83HT baYtZcMSzMwKC28h6nBwmuwFtV+POuY7392MIwwQgZXqPWWVBod6Z9f93sf1kkhfcaFF Z+o0z+iunCfzjYW62R+ISNYszTOPv8E4eEUh3PDl8571YYdkBvSmw/5qEP9ydDvsdOK4 lshDLPrPoCMtwvnEv1NJinnfhl0Yd/enFUmAHivGsJIhlfKONdXdLxkpcdDv6JMKnJn9 UrmedRbKuHqbF8VlXA7hNMBtJ/jHCjm47P1DG6eEJAFbjhML3B9fhLZlDQ8KyDzdybOq m7OQ== X-Gm-Message-State: APjAAAW9NJOzc/c71wLbt3BeohHZ8m8c56g2mVWPi80TM2bXqy6BW2vd ZyRJkXgX+TezW5ScKcfGk8bzuTuSsmo= X-Google-Smtp-Source: APXvYqzgtYof9nMTkgKI3z5jSx3J0fOht8MP7YX1bGbt0TLIdipj7RiHT0ZMhNubsRTI+wV70OXShA== X-Received: by 2002:a63:fc64:: with SMTP id r36mr12136191pgk.280.1552813722680; Sun, 17 Mar 2019 02:08:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:25 -0700 Message-Id: <20190317090834.5552-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PATCH for-4.1 v2 04/13] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 49 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 27f65600c3..cfb18682b1 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -226,16 +226,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o,= TCGType low_type) vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o); } =20 -void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_add_vec, vece, r, a, b); -} - -void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b); -} - void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { vec_gen_op3(INDEX_op_and_vec, 0, r, a, b); @@ -296,11 +286,30 @@ void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) tcg_gen_not_vec(0, r, r); } =20 +static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGType type =3D rt->base_type; + int can; + + tcg_debug_assert(at->base_type >=3D type); + can =3D tcg_can_emit_vec_op(opc, type, vece); + if (can > 0) { + vec_gen_2(opc, type, vece, ri, ai); + } else if (can < 0) { + tcg_expand_vec_op(opc, type, vece, ri, ai); + } else { + return false; + } + return true; +} + void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_not_vec) { - vec_gen_op2(INDEX_op_not_vec, 0, r, a); - } else { + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t =3D tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); @@ -309,9 +318,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a) =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_neg_vec) { - vec_gen_op2(INDEX_op_neg_vec, vece, r, a); - } else { + if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { TCGv_vec t =3D tcg_const_zeros_vec_matching(r); tcg_gen_sub_vec(vece, r, t, a); tcg_temp_free_vec(t); @@ -409,6 +416,16 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec= a, } } =20 +void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_add_vec); +} + +void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sub_vec); +} + void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_mul_vec); --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155281403512952.16875728596449; Sun, 17 Mar 2019 02:13:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:52132 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5RrV-0000zn-Uv for importer@patchew.org; Sun, 17 Mar 2019 05:13:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmg-0005ca-ME for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmf-00049g-Lw for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:46 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:46611) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmf-00049E-9T for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:45 -0400 Received: by mail-pf1-x442.google.com with SMTP id s23so9211116pfe.13 for ; Sun, 17 Mar 2019 02:08:45 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jmuyYwVXW/xQ7qX84YnbpLmhrhQYqlDYF9YCOZY12zU=; b=t1N9zA2+yFhNV2KlNZxpNzmFjjiAyrT4z3Y1gHhbVFyj4FgvWnzENvsPireJdQ1kFV 0XQ6OCIrhgeAhtLAPozV8uImSGikF/olDe1ySGXxqdmhDNHhChGSG8LFMY2dOAb5ujCr cCCqwDRrd7Z1a/SR6Rl07a5lqtBYleOZc5WYyUYO3C8pdh1chtMU/gTJ9iLSqmyH0erP 55Du2hxAvr0ojrMgZiuWt8VgM/xGS/muMuLeCH7kmRczD7K8oacBcyHq8WmdhCaqiJLT kOVdezrzb1kqDZL7kCQ76dOvbEcLw4sKF2vVxtuM+vbYCF5i229aMW338R/5yO+PKPfJ tHkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jmuyYwVXW/xQ7qX84YnbpLmhrhQYqlDYF9YCOZY12zU=; b=FSjEosQpOyrtbdGnnmVZtgchQLH626NJPvxDBgXm7mLVObWlbiRuFAU71Ym4R3Ix4H aSN85Rhvr1POU2KdMKIncz4EcMBO5YWsjb1SZzRTStf/hxCjTp3t99WYIBB4uR1kexND dhHJFEZRp9A4pJcrImYleTMxsBTK3Bk/Xn2NSMg0xIewkPM+1WPyBfAfSRjEmwQyRz10 GDWYVbn+i9XxA65qcWJ6NxJ7nvGaNjf9yWi8U3VDLS3Qs9U1KThOOCRcCHKXYoHJonMq ElgwZG2xoUooeF5m9c1ZupCHRTiRclrFklhEzPI9NqypkCoJ2UUnp6RDtPUvd9BA3s5v eG0g== X-Gm-Message-State: APjAAAWjzcHK3a3r2smVdnq5xrrTi69Uq+X5ix9yeZgYxSIraY0C5mfv iNnHlO2sf2U6WG65Tq2WPzBtGNnYJsI= X-Google-Smtp-Source: APXvYqzWVaZjmiQvgIvlIdnrtsSxCzqpKjUpHdsaS8IkQsinfeoEmeiL/dooAYqHVa8rOxG/3Kz2pA== X-Received: by 2002:a63:cd10:: with SMTP id i16mr11710839pgg.90.1552813723897; Sun, 17 Mar 2019 02:08:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:26 -0700 Message-Id: <20190317090834.5552-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1 v2 05/13] target/arm: Fill in .opc for cmtst_op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to fall back to integers if the tcg backend does not support comparisons in the given vece. Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index d408e4d7ef..13e2dc6562 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6140,16 +6140,20 @@ static void gen_cmtst_vec(unsigned vece, TCGv_vec d= , TCGv_vec a, TCGv_vec b) const GVecGen3 cmtst_op[4] =3D { { .fni4 =3D gen_helper_neon_tst_u8, .fniv =3D gen_cmtst_vec, + .opc =3D INDEX_op_cmp_vec, .vece =3D MO_8 }, { .fni4 =3D gen_helper_neon_tst_u16, .fniv =3D gen_cmtst_vec, + .opc =3D INDEX_op_cmp_vec, .vece =3D MO_16 }, { .fni4 =3D gen_cmtst_i32, .fniv =3D gen_cmtst_vec, + .opc =3D INDEX_op_cmp_vec, .vece =3D MO_32 }, { .fni8 =3D gen_cmtst_i64, .fniv =3D gen_cmtst_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .opc =3D INDEX_op_cmp_vec, .vece =3D MO_64 }, }; =20 --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814209017532.6465753886919; Sun, 17 Mar 2019 02:16:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:52189 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5RuJ-0003dn-Re for importer@patchew.org; Sun, 17 Mar 2019 05:16:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47732) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rml-0005iA-UP for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmi-0004AR-3I for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:51 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:40645) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmh-0004A7-E8 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:48 -0400 Received: by mail-pg1-x544.google.com with SMTP id u9so9319745pgo.7 for ; Sun, 17 Mar 2019 02:08:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ZpyABEAn28lHD6FwP3r05YYwY7hnG05nRp20SJKs4A=; b=zurOHqaajOruSuaxwEZ6yqkGdBlo88CzIh+i3vxyafxLhJgQF2JkaRRCwYj4TepSBd +gQTIys+WqPjjNNwsXbGVmjxnt/aCcmd3J36E/rhMD7Ny2gDxZRswYbKciL2mAm874RX 5njbLSm4UbhqprULEpriN3QrSJf+wLKJhX5GPNL9ySFGWtBnWkM3vYX+wrPCjtkOmO3s SSdmLeLeMRi/MQYCWiP0/p2zcNZXaolf269D4LFQp3RfWx1/YVveII42Js3Upk+yp5d/ NkvEDwboF1pN1vCeEfJFhqq1JpyIJFfMggo6wcrwra5wY26rbFEdJXR82iZ5x/H5BHlb MkWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ZpyABEAn28lHD6FwP3r05YYwY7hnG05nRp20SJKs4A=; b=ffGeXIxT6hJ6QjOLwHWVnOjdrzd+UEdKgHQ4q3D1Mtgzbgo6nIu6SFM5cfTbCiLhpv ihn6JWkjEyL7vM7mxooA6T5T8hE7HgPcMdAyVnjwaecbIt6azsBIwRXVvqCdwshbcqTl hpYP5Rq9CelftFibXE1nlKDt0icGL+hZvzyfNFfmG+oK/SEFgYtiu7Ckk5MCmuwO5ePQ ZSU3POI5LZxOSkD2BwI5MkrMkUfp+t04iUgVpyzUvjvH+W7KsGWo9wsuTyFAlbJbpesG ygv2WpcJQBYvEVieuOO5wKdOESWICsGbEVjJmyp7R7o5nYk8s21ZnDayWvmToQ7oA7wO ZY/g== X-Gm-Message-State: APjAAAXgRMBKOt6UI1kylzwWsEfOHRAP1xbRDT4K78SRwdhRaBNXzEgt 4K6jdBFPxyVVHLO8YFaq/hchcRkvBo8= X-Google-Smtp-Source: APXvYqz4+iSikDf3nuj8yHOSS0DA8JEN2Ee9N76tbjY/GBmCWgnHa7asez4MXsKogjqatvOVXj3BkA== X-Received: by 2002:a63:181a:: with SMTP id y26mr12216378pgl.268.1552813725440; Sun, 17 Mar 2019 02:08:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:27 -0700 Message-Id: <20190317090834.5552-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.1 v2 06/13] tcg/ppc: Initial backend support for Altivec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are a few missing operations yet, like expansion of multiply and shifts. But this has move, load, store, and basic arithmetic. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 31 +- tcg/ppc/tcg-target.opc.h | 3 + tcg/ppc/tcg-target.inc.c | 609 +++++++++++++++++++++++++++++++++++---- 3 files changed, 584 insertions(+), 59 deletions(-) create mode 100644 tcg/ppc/tcg-target.opc.h diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 52c1bb04b1..683eb807ae 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -31,7 +31,7 @@ # define TCG_TARGET_REG_BITS 32 #endif =20 -#define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 =20 @@ -45,10 +45,20 @@ typedef enum { TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27, TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31, =20 + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + TCG_REG_CALL_STACK =3D TCG_REG_R1, TCG_AREG0 =3D TCG_REG_R27 } TCGReg; =20 +extern bool have_isa_altivec; extern bool have_isa_2_06; extern bool have_isa_3_00; =20 @@ -124,6 +134,25 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +/* ??? Constant pool not yet supported for 32-bit. */ +#if TCG_TARGET_REG_BITS =3D=3D 64 +#define TCG_TARGET_HAS_v64 have_isa_altivec +#define TCG_TARGET_HAS_v128 have_isa_altivec +#define TCG_TARGET_HAS_v256 0 +#endif + +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_cmp_vec 1 +#define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 1 +#define TCG_TARGET_HAS_minmax_vec 1 + void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h new file mode 100644 index 0000000000..4816a6c3d4 --- /dev/null +++ b/tcg/ppc/tcg-target.opc.h @@ -0,0 +1,3 @@ +/* Target-specific opcodes for host vector expansion. These will be + emitted by tcg_expand_vec_op. For those familiar with GCC internals, + consider these to be UNSPEC with names. */ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index ec8e336be8..61a245b828 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -42,6 +42,9 @@ # define TCG_REG_TMP1 TCG_REG_R12 #endif =20 +#define TCG_VEC_TMP1 TCG_REG_V0 +#define TCG_VEC_TMP2 TCG_REG_V1 + #define TCG_REG_TB TCG_REG_R31 #define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64) =20 @@ -61,6 +64,7 @@ =20 static tcg_insn_unit *tb_ret_addr; =20 +bool have_isa_altivec; bool have_isa_2_06; bool have_isa_3_00; =20 @@ -72,39 +76,15 @@ bool have_isa_3_00; #endif =20 #ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "r0", - "r1", - "r2", - "r3", - "r4", - "r5", - "r6", - "r7", - "r8", - "r9", - "r10", - "r11", - "r12", - "r13", - "r14", - "r15", - "r16", - "r17", - "r18", - "r19", - "r20", - "r21", - "r22", - "r23", - "r24", - "r25", - "r26", - "r27", - "r28", - "r29", - "r30", - "r31" +static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] =3D { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", }; #endif =20 @@ -139,6 +119,26 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R5, TCG_REG_R4, TCG_REG_R3, + + /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ + TCG_REG_V2, /* call clobbered, vectors */ + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V8, + TCG_REG_V9, + TCG_REG_V10, + TCG_REG_V11, + TCG_REG_V12, + TCG_REG_V13, + TCG_REG_V14, + TCG_REG_V15, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, }; =20 static const int tcg_target_call_iarg_regs[] =3D { @@ -233,6 +233,10 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffff; break; + case 'v': + ct->ct |=3D TCG_CT_REG; + ct->u.regs =3D 0xffffffff00000000ull; + break; case 'L': /* qemu_ld constraint */ ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffff; @@ -320,6 +324,7 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) +#define VX4(opc) (OPCD(4)|(opc)) =20 #define B OPCD( 18) #define BC OPCD( 16) @@ -461,6 +466,71 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, =20 #define NOP ORI /* ori 0,0,0 */ =20 +#define LVX XO31(103) +#define LVEWX XO31(71) + +#define STVX XO31(231) +#define STVEWX XO31(199) + +#define VADDSBS VX4(768) +#define VADDUBS VX4(512) +#define VADDUBM VX4(0) +#define VADDSHS VX4(832) +#define VADDUHS VX4(576) +#define VADDUHM VX4(64) +#define VADDSWS VX4(896) +#define VADDUWS VX4(640) +#define VADDUWM VX4(128) + +#define VSUBSBS VX4(1792) +#define VSUBUBS VX4(1536) +#define VSUBUBM VX4(1024) +#define VSUBSHS VX4(1856) +#define VSUBUHS VX4(1600) +#define VSUBUHM VX4(1088) +#define VSUBSWS VX4(1920) +#define VSUBUWS VX4(1664) +#define VSUBUWM VX4(1152) + +#define VMAXSB VX4(258) +#define VMAXSH VX4(322) +#define VMAXSW VX4(386) +#define VMAXUB VX4(2) +#define VMAXUH VX4(66) +#define VMAXUW VX4(130) +#define VMINSB VX4(770) +#define VMINSH VX4(834) +#define VMINSW VX4(898) +#define VMINUB VX4(514) +#define VMINUH VX4(578) +#define VMINUW VX4(642) + +#define VCMPEQUB VX4(6) +#define VCMPEQUH VX4(70) +#define VCMPEQUW VX4(134) +#define VCMPGTSB VX4(774) +#define VCMPGTSH VX4(838) +#define VCMPGTSW VX4(902) +#define VCMPGTUB VX4(518) +#define VCMPGTUH VX4(582) +#define VCMPGTUW VX4(646) + +#define VAND VX4(1028) +#define VANDC VX4(1092) +#define VNOR VX4(1284) +#define VOR VX4(1156) +#define VXOR VX4(1220) + +#define VSPLTB VX4(524) +#define VSPLTH VX4(588) +#define VSPLTW VX4(652) +#define VSPLTISB VX4(780) +#define VSPLTISH VX4(844) +#define VSPLTISW VX4(908) + +#define VPERM VX4(43) +#define VSLDOI VX4(44) + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -473,6 +543,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define MB64(b) ((b)<<5) #define FXM(b) (1 << (19 - (b))) =20 +#define VRT(r) (((r) & 31) << 21) +#define VRA(r) (((r) & 31) << 16) +#define VRB(r) (((r) & 31) << 11) +#define VRC(r) (((r) & 31) << 6) + #define LK 1 =20 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) @@ -568,9 +643,29 @@ static void tcg_out_mem_long(TCGContext *s, int opi, i= nt opx, TCGReg rt, =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (ret !=3D arg) { - tcg_out32(s, OR | SAB(arg, ret, arg)); + if (ret =3D=3D arg) { + return true; + } + switch (type) { + case TCG_TYPE_I64: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + /* fallthru */ + case TCG_TYPE_I32: + if (ret < 32 && arg < 32) { + tcg_out32(s, OR | SAB(arg, ret, arg)); + break; + } else if (ret < 32 || arg < 32) { + /* Altivec does not support vector/integer moves. */ + return false; + } + /* fallthru */ + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D 32 && arg >=3D 32); + tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); + break; + default: + g_assert_not_reached(); } return true; } @@ -720,10 +815,64 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, } } =20 -static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) +static void tcg_out_imm_vec(TCGContext *s, TCGReg ret, + uint64_t h, uint64_t l) { - tcg_out_movi_int(s, type, ret, arg, false); +#ifndef HOST_WORDS_BIGENDIAN + uint64_t t =3D l; l =3D h; h =3D t; +#endif + + /* FIXME: 32-bit altivec */ + new_pool_l2(s, R_PPC_ADDR16, s->code_ptr, + -(intptr_t)s->code_gen_ptr, h, l); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); + tcg_out32(s, LVX | VRT(ret) | RB(TCG_REG_TMP1)); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long val) +{ + int low =3D (int8_t)val; + + if (low >=3D -16 && low < 16) { + if (val =3D=3D (tcg_target_long)dup_const(MO_8, low)) { + tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val =3D=3D (tcg_target_long)dup_const(MO_16, low)) { + tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val =3D=3D (tcg_target_long)dup_const(MO_32, low)) { + tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); + return; + } + } + + /* With Altivec, we load the whole 128-bit value. */ + tcg_out_imm_vec(s, ret, val, val); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(ret < 32); + tcg_out_movi_int(s, type, ret, arg, false); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D 32); + tcg_out_dupi_vec(s, type, ret, arg); + break; + + default: + g_assert_not_reached(); + } } =20 static bool mask_operand(uint32_t c, int *mb, int *me) @@ -876,7 +1025,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, i= nt opx, TCGReg rt, } =20 /* For unaligned, or very large offsets, use the indexed form. */ - if (offset & align || offset !=3D (int32_t)offset) { + if (offset & align || offset !=3D (int32_t)offset || opi =3D=3D 0) { if (rs =3D=3D base) { rs =3D TCG_REG_R0; } @@ -907,32 +1056,92 @@ static void tcg_out_mem_long(TCGContext *s, int opi,= int opx, TCGReg rt, } } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg base, intptr_t offset) { - int opi, opx; + int shift; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (type =3D=3D TCG_TYPE_I32) { - opi =3D LWZ, opx =3D LWZX; - } else { - opi =3D LD, opx =3D LDX; + switch (type) { + case TCG_TYPE_I32: + if (ret < 32) { + tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); + break; + } + assert((offset & 3) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEWX, ret & 31, base, offset); + shift =3D (offset - 4) & 0xc; + if (shift) { + tcg_out32(s, VSLDOI | VRT(ret) | VRA(ret) | VRB(ret) + | (shift << 6)); + } + break; + case TCG_TYPE_I64: + if (ret < 32) { + tcg_out_mem_long(s, LD, LDX, ret, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(ret >=3D 32); + assert((offset & 7) =3D=3D 0); + tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset); + if (offset & 8) { + tcg_out32(s, VSLDOI | VRT(ret) | VRA(ret) | VRB(ret) | (8 << 6= )); + } + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D 32); + tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset); + break; + default: + g_assert_not_reached(); } - tcg_out_mem_long(s, opi, opx, ret, arg1, arg2); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg base, intptr_t offset) { - int opi, opx; + int shift; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (type =3D=3D TCG_TYPE_I32) { - opi =3D STW, opx =3D STWX; - } else { - opi =3D STD, opx =3D STDX; + switch (type) { + case TCG_TYPE_I32: + if (arg < 32) { + tcg_out_mem_long(s, STW, STWX, arg, base, offset); + break; + } + assert((offset & 3) =3D=3D 0); + shift =3D (offset - 4) & 0xc; + if (shift) { + tcg_out32(s, VSLDOI | VRT(TCG_VEC_TMP1) + | VRA(arg) | VRB(arg) | (shift << 6)); + arg =3D TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset); + break; + case TCG_TYPE_I64: + if (arg < 32) { + tcg_out_mem_long(s, STD, STDX, arg, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(arg >=3D 32); + assert((offset & 7) =3D=3D 0); + if (offset & 8) { + tcg_out32(s, VSLDOI | VRT(TCG_VEC_TMP1) + | VRA(arg) | VRB(arg) | (8 << 6)); + arg =3D TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset); + tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset + 4); + break; + case TCG_TYPE_V128: + tcg_debug_assert(arg >=3D 32); + tcg_out_mem_long(s, 0, STVX, arg & 31, base, offset); + break; + default: + g_assert_not_reached(); } - tcg_out_mem_long(s, opi, opx, arg, arg1, arg2); } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -2618,6 +2827,232 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, } } =20 +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_not_vec: + return 1; + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + return vece <=3D MO_32; + case INDEX_op_cmp_vec: + return vece <=3D MO_32 ? -1 : 0; + default: + return 0; + } +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + static const uint32_t + add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, 0 }, + sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, 0 }, + eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, + gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, + usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, + sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, + ussub_op[4] =3D { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, + umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 },=20 + smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 },=20 + umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 },=20 + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }; + + TCGType type =3D vecl + TCG_TYPE_V64; + TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + uint32_t insn; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + return; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + return; + + case INDEX_op_add_vec: + insn =3D add_op[vece]; + break; + case INDEX_op_sub_vec: + insn =3D sub_op[vece]; + break; + case INDEX_op_ssadd_vec: + insn =3D ssadd_op[vece]; + break; + case INDEX_op_sssub_vec: + insn =3D sssub_op[vece]; + break; + case INDEX_op_usadd_vec: + insn =3D usadd_op[vece]; + break; + case INDEX_op_ussub_vec: + insn =3D ussub_op[vece]; + break; + case INDEX_op_smin_vec: + insn =3D smin_op[vece]; + break; + case INDEX_op_umin_vec: + insn =3D umin_op[vece]; + break; + case INDEX_op_smax_vec: + insn =3D smax_op[vece]; + break; + case INDEX_op_umax_vec: + insn =3D umax_op[vece]; + break; + case INDEX_op_and_vec: + insn =3D VAND; + break; + case INDEX_op_or_vec: + insn =3D VOR; + break; + case INDEX_op_xor_vec: + insn =3D VXOR; + break; + case INDEX_op_andc_vec: + insn =3D VANDC; + break; + case INDEX_op_not_vec: + insn =3D VNOR; + a2 =3D a1; + break; + + case INDEX_op_dup_vec: + /* Recall we use VSX integer loads, so the integer is right + justified within the left (zero-index) double-word. */ + switch (vece) { + case MO_8: + tcg_out32(s, VSPLTB | VRT(a0) | VRB(a1) | (7 << 16)); + break; + case MO_16: + tcg_out32(s, VSPLTH | VRT(a0) | VRB(a1) | (3 << 16)); + break; + case MO_32: + tcg_out32(s, VSPLTW | VRT(a0) | VRB(a1) | (1 << 16)); + break; + case MO_64: + /* FIXME: 32-bit altivec */ + tcg_out_dupi_vec(s, TCG_TYPE_V128, TCG_VEC_TMP1, + 0x0001020304050607ull); + tcg_out32(s, VPERM | VRT(a0) | VRA(a1) | VRB(a1) + | VRC(TCG_VEC_TMP1)); + break; + } + return; + + case INDEX_op_cmp_vec: + { + TCGCond cond =3D args[3]; + + switch (cond) { + case TCG_COND_EQ: + insn =3D eq_op[vece]; + break; + case TCG_COND_GT: + insn =3D gts_op[vece]; + break; + case TCG_COND_GTU: + insn =3D gtu_op[vece]; + break; + default: + g_assert_not_reached(); + } + tcg_debug_assert(insn !=3D 0); + + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); + } + return; + + default: + g_assert_not_reached(); + } + + tcg_debug_assert(insn !=3D 0); + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap =3D false, need_inv =3D false; + + tcg_debug_assert(vece <=3D MO_32); + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv =3D true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap =3D true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap =3D need_inv =3D true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond =3D tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 =3D v1, v1 =3D v2, v2 =3D t1; + cond =3D tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + if (need_inv) { + tcg_gen_not_vec(vece, v0, v0); + } +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + va_list va; + TCGv_vec v0, v1, v2; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_cmp_vec: + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + default: + g_assert_not_reached(); + } + va_end(va); +} + static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; @@ -2655,6 +3090,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "r", "r", "r", "r", "rI", "rZM" } }; static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; + static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; + static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; + static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2790,6 +3228,31 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return (TCG_TARGET_REG_BITS =3D=3D 64 ? &S_S : TARGET_LONG_BITS =3D=3D 32 ? &S_S_S : &S_S_S_S); =20 + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_mul_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_orc_vec: + case INDEX_op_cmp_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + return &v_v_v; + case INDEX_op_not_vec: + case INDEX_op_dup_vec: + return &v_v; + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + return &v_r; + default: return NULL; } @@ -2800,6 +3263,9 @@ static void tcg_target_init(TCGContext *s) unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); unsigned long hwcap2 =3D qemu_getauxval(AT_HWCAP2); =20 + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { + have_isa_altivec =3D true; + } if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 =3D true; } @@ -2811,6 +3277,10 @@ static void tcg_target_init(TCGContext *s) =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; + if (have_isa_altivec) { + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xffffffff00000000ull; + } =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); @@ -2826,6 +3296,27 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); =20 + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ @@ -2836,6 +3327,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ } --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+YKY+LXp9zIw9Md5dKypZwukvaZ0fElP7+gnW7iZQI0=; b=eHrxIYYC/vKGI1Vd6HDkfM0oygGjyDrXnwaDD/9W6YSa9IqiZ2y2Qw96fvW2zC+Z+7 GrJWykvNygQ13GIUbPb426P3RZsOAZb6jWaVgIoqKNfcL7fXFwQUMlVSNUi/StnIa12G K88eKZ8u6bRkN7H8wVG4ubi4AXbwILGr//yPi7ok6WUAbDb/LNaA7oq+Jm/YTwKUaI8c QSenqWBJn2vI0ZJFr1rEDzvAH/2mGYerUrkIl7dfRZ2ih+uCKS8CCx+IMakcZ9bY9oSW IONK3lBezTcmVi3NivnFIimaJkLWStmKvS2B80Ave71BcTAvFdNmBNNHZMZP5ei6AUWQ t2vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+YKY+LXp9zIw9Md5dKypZwukvaZ0fElP7+gnW7iZQI0=; b=BQ0YTKM8vYkPgpJiEPM9Dl6T5mfQ0VVAzoSELJbKaq3DXf6oPIs/TSivGGJ82HNX7s D+FoON5tG8eafO0lPWh00nmzl3OXtYruQZfVD75NiqhTXqqMKokzOxyiQwoGjYbu2yuu kbClwjKvNEi9ft94GswHyNWqlig1/1c7y8T7nIyYTgUe1AhLMLaGiCRpBEYXKK9U7J4I q0meXKC+O1irP9f08OP1hDK4RzFC+nVnxLusJ6n6fL5PdtjPcDAeIS4FjPb2TkD6Hn9I Iit0jxLRQvluOIgF5Tj/zDhbLO6+11eaq7Obeb/bQxM3/8gBReZLE8h+GjIg3wvcfV6L hPng== X-Gm-Message-State: APjAAAW/GaDK+XnqzTevxbgzfbvgOfzhkIQdlBS6dTpQttkhTyGIwLY2 VsJv+vT+qOQ540w6htBsIbug2oV37hQ= X-Google-Smtp-Source: APXvYqzUpNqxaLCGg0I8DhvwQN/hXMzyrJ4c1SFBCBaZQdAJlJFQNMLBk8gQ6K9DLGH+eawsojLVXg== X-Received: by 2002:a63:da43:: with SMTP id l3mr12306395pgj.164.1552813726763; Sun, 17 Mar 2019 02:08:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:28 -0700 Message-Id: <20190317090834.5552-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 07/13] tcg: Add INDEX_op_dup_mem_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + tcg/tcg-op-gvec.c | 88 +++++++++++++++++++++------------------- tcg/tcg-op-vec.c | 11 +++++ tcg/tcg.c | 2 + 9 files changed, 66 insertions(+), 41 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 2d93cf404e..8ce99fc9c8 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,6 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7995fe3eab..8e8d59f4f4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -187,6 +187,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 683eb807ae..5143ee853a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -152,6 +152,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 =20 void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d3e51b15af..64cd3f58ef 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -950,6 +950,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv= _i64, TCGArg, TCGMemOp); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4e0238ad1a..b8ad147377 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -211,6 +211,7 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, =20 DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) +DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR | IMPL(TCG_TARGET_HAS_dupm_vec)) =20 DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS =3D=3D 32)) diff --git a/tcg/tcg.h b/tcg/tcg.h index 32b7cf3489..f7c12de75a 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -185,6 +185,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_dupm_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0996ef0812..59ab516bf0 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -390,6 +390,40 @@ static TCGType choose_vector_type(TCGOpcode op, unsign= ed vece, uint32_t size, return 0; } =20 +static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, + uint32_t maxsz, TCGv_vec t_vec) +{ + uint32_t i =3D 0; + + switch (type) { + case TCG_TYPE_V256: + /* Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + */ + for (; i + 32 <=3D oprsz; i +=3D 32) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); + } + /* fallthru */ + case TCG_TYPE_V128: + for (; i + 16 <=3D oprsz; i +=3D 16) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); + } + break; + case TCG_TYPE_V64: + for (; i < oprsz; i +=3D 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + } + break; + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. * Only one of IN_32 or IN_64 may be set; * IN_C is used if IN_32 and IN_64 are unset. @@ -429,49 +463,11 @@ static void do_dup(unsigned vece, uint32_t dofs, uint= 32_t oprsz, } else if (in_64) { tcg_gen_dup_i64_vec(vece, t_vec, in_64); } else { - switch (vece) { - case MO_8: - tcg_gen_dup8i_vec(t_vec, in_c); - break; - case MO_16: - tcg_gen_dup16i_vec(t_vec, in_c); - break; - case MO_32: - tcg_gen_dup32i_vec(t_vec, in_c); - break; - default: - tcg_gen_dup64i_vec(t_vec, in_c); - break; - } + tcg_gen_dupi_vec(vece, t_vec, in_c); } - - i =3D 0; - switch (type) { - case TCG_TYPE_V256: - /* Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. - */ - for (; i + 32 <=3D oprsz; i +=3D 32) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); - } - /* fallthru */ - case TCG_TYPE_V128: - for (; i + 16 <=3D oprsz; i +=3D 16) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); - } - break; - case TCG_TYPE_V64: - for (; i < oprsz; i +=3D 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); - } - break; - default: - g_assert_not_reached(); - } - + do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); - goto done; + return; } =20 /* Otherwise, inline with an integer type, unless "large". */ @@ -1287,6 +1283,16 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t do= fs, uint32_t oprsz, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + if (TCG_TARGET_HAS_dupm_vec) { + TCGType type =3D choose_vector_type(INDEX_op_dupm_vec, vece, oprsz= , 0); + if (type !=3D 0) { + TCGv_vec t_vec =3D tcg_temp_new_vec(type); + tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); + do_dup_store(type, dofs, oprsz, maxsz, t_vec); + tcg_temp_free_vec(t_vec); + return; + } + } if (vece <=3D MO_32) { TCGv_i32 in =3D tcg_temp_new_i32(); switch (vece) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cfb18682b1..ce7987b858 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -194,6 +194,17 @@ void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TC= Gv_i32 a) vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } =20 +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, + tcg_target_long ofs) +{ + TCGArg ri =3D tcgv_vec_arg(r); + TCGArg bi =3D tcgv_ptr_arg(b); + TCGTemp *rt =3D arg_temp(ri); + TCGType type =3D rt->base_type; + + vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs); +} + static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o) { TCGArg ri =3D tcgv_vec_arg(r); diff --git a/tcg/tcg.c b/tcg/tcg.c index b5389ea767..e0d771d610 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1623,6 +1623,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_smax_vec: case INDEX_op_umax_vec: return have_vec && TCG_TARGET_HAS_minmax_vec; + case INDEX_op_dupm_vec: + return have_vec && TCG_TARGET_HAS_dupm_vec; =20 default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814188581519.3011762449414; Sun, 17 Mar 2019 02:16:28 -0700 (PDT) Received: from localhost ([127.0.0.1]:52185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Ru2-0003Si-CS for importer@patchew.org; Sun, 17 Mar 2019 05:16:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmk-0005fy-M2 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmj-0004Au-Gl for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:50 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40643) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmj-0004Ab-6b for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:49 -0400 Received: by mail-pg1-x541.google.com with SMTP id u9so9319770pgo.7 for ; Sun, 17 Mar 2019 02:08:49 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9zMlnJaHcUe6qi5C/L7hjCRWpfIzUjgoN4LyEuyE5B4=; b=h6hJONKhpR+7bEu00044SbNNXny5YCYfc2mUcwulbtRhbWoFU7s2WXtJw2L+Dgz/u/ EA5hsGe4jvDHNyvOhGxmtFOt2C76fgmPLGNAiL5cJvx4qEAje3FHqd/Gl/DlCiNYEYiw V/LIPos3WxMEJU05kAuWCVgCl9ZuGSieZ4Ts5u1XMK08RschsGAT2r7CNOc7lWw+xHde doKLFOlXUe4lJEVaVjCQNGQN2OwkDTuQrJxTzJJ/VmCGAi5uQC2AE1JKhL/1AvCpT3q5 AzfnUcxrFpU5/aFVKBqIlmK/YyPv5mzZxKdsXu1lWYPyQ76ro1RuQBVFIPeCg+C64u2i PHGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9zMlnJaHcUe6qi5C/L7hjCRWpfIzUjgoN4LyEuyE5B4=; b=YNNHLl8dVAgpbemfYHBVXyHeKDMYYanyxtgWuR+zC2bY1cFy0PT85NQf3PTKuCwVa1 cr2G3bubBcG9FK/i99355TooNsWUJ4IHxLKaGqziNefiHIX3DiFPC6ymewZoSGFRk5Wq /GtY/Anv5QdlxIOsscffwg5nHhZ4aibSm7SjA+2IQ3zO/lowk+agBkIXGqopv08HMs4a jHfobD80HeFYQ3DjxaRw6jpSKJpDAfysrJfJvuwWqgvIZoFJyafBqUgvpKapclDmajdt XzWEtwzJyEXnUxD2YZJbh4H4yk33defHzoox7B28HWLbYPqKdehJ0Dd0lstejtfpxs4x lT5w== X-Gm-Message-State: APjAAAUuY/65IyOsgiT+IroT6ZOzGvW/KTi4c6oTCXOQa4jHcglrj3J8 e9zNlT7uq1j5SurbTvDNjXV6cX6OaAU= X-Google-Smtp-Source: APXvYqzIdEdsHtKOoDlsNztBf4lTT83hGZA1JFtQGLUAUW3qCy+adBTCZUkJQTr4jgtTYAcx9OGNDQ== X-Received: by 2002:a17:902:788d:: with SMTP id q13mr13942165pll.154.1552813728017; Sun, 17 Mar 2019 02:08:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:29 -0700 Message-Id: <20190317090834.5552-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH for-4.1 v2 08/13] tcg/ppc: Implement INDEX_op_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This saves a round trip through an integer register and back to memory. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 57 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5143ee853a..8ba5668fae 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -152,7 +152,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_dupm_vec 0 +#define TCG_TARGET_HAS_dupm_vec 1 =20 void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 61a245b828..85e332fcd3 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -467,6 +467,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define NOP ORI /* ori 0,0,0 */ =20 #define LVX XO31(103) +#define LVEBX XO31(7) +#define LVEHX XO31(39) #define LVEWX XO31(71) =20 #define STVX XO31(231) @@ -2835,6 +2837,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_xor_vec: case INDEX_op_andc_vec: case INDEX_op_not_vec: + case INDEX_op_dupm_vec: return 1; case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2854,6 +2857,55 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } } =20 +static void tcg_out_dupm_vec(TCGContext *s, unsigned vece, TCGReg out, + TCGReg base, intptr_t offset) +{ + int elt; + + out &=3D 31; + switch (vece) { + case MO_8: + tcg_out_mem_long(s, 0, LVEBX, out, base, offset); + elt =3D extract32(offset, 0, 4); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 15; +#endif + tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_16: + assert((offset & 1) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEHX, out, base, offset); + elt =3D extract32(offset, 1, 3); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 7; +#endif + tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_32: + assert((offset & 3) =3D=3D 0); + tcg_out_mem_long(s, 0, LVEWX, out, base, offset); + elt =3D extract32(offset, 2, 2); +#ifndef HOST_WORDS_BIGENDIAN + elt ^=3D 3; +#endif + tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_64: + assert((offset & 7) =3D=3D 0); + tcg_out_mem_long(s, 0, LVX, out, base, offset); + /* FIXME: 32-bit altivec */ + tcg_out_dupi_vec(s, TCG_TYPE_V128, TCG_VEC_TMP1, + offset & 8 + ? 0x08090a0b0c0d0e0full + : 0x0001020304050607ull); + tcg_out32(s, VPERM | VRT(out) | VRA(out) | VRB(out) + | VRC(TCG_VEC_TMP1)); + break; + default: + g_assert_not_reached(); + } +} + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) @@ -2884,7 +2936,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); return; - + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, vece, a0, a1, a2); + return; case INDEX_op_add_vec: insn =3D add_op[vece]; break; @@ -3251,6 +3305,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &v_v; case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_dupm_vec: return &v_r; =20 default: --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814042178282.17095937696104; Sun, 17 Mar 2019 02:14:02 -0700 (PDT) Received: from localhost ([127.0.0.1]:52138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rrl-00019P-30 for importer@patchew.org; Sun, 17 Mar 2019 05:14:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmm-0005iU-4B for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rml-0004Cg-2c for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:52 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:32975) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmk-0004BD-Kv for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:50 -0400 Received: by mail-pf1-x442.google.com with SMTP id i19so9249856pfd.0 for ; Sun, 17 Mar 2019 02:08:50 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DI+dKOMHlj5qC6BlkD+neUxReHyEoxD6l7ZaHgSu0oA=; b=zCe9fX43l8rKSEyjDYhJMo8eX25/tf+TZr4aHTTx4ilEoPZOSuev2dGSXHxUtWWya3 RJkBetzclBBvjqX0Jg+28C/kOXezoXmXymzPhPn6Hl5SxSFAWaHxDdN0eQztp8Q2HoKj 7fIp0P0P4ExiFPbb0Mz6Wp+x0nvbbMgC/vslVYMliP3wy+YzlvdNkrFG1NLQOgdtpDLZ XFkU2kQZKymaj15vn+c2QZT+lTHZBqvCCxKQ+JWm2CHkPE3hBH6V0O6J7rOmIio4R6j1 54fTkfjs0jwDRmMyHUol5FNCBoYIHXDO6u0KeZw3BcZ0v4mM0vOR6iCpMEWafxieNT2P 4vMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DI+dKOMHlj5qC6BlkD+neUxReHyEoxD6l7ZaHgSu0oA=; b=pSu2dK0T2QVZbQ0gu6FxNHuFOVznjJQ+9wfcHWr6Eoq+J8ixFWIQt2Qltedko5NcuP OEBRsfnP6mb3qYx82mOoxhbJERc7LlhY1v5YGj7qMDLtJuyxGk4G31Mca75byhu/rGiU yqJLG/14gO0+vDYx4NUyVreKGimWY5nGLTYrT0dWrrhaOqzeZ/wYuga1dHKCR4+hc03G 0sANzqSlKXuH12W42WUy4aVk04dfUnhsJo1mbrE99DKQyITIAaUUf7x0H4fYJPUYSrFM zXFh15N3dfbWyIedsZn0yAZA1u46Gu449EyGgjxof3if6IOQBcqajkH0Mcq7VYpt1Ogk BZGA== X-Gm-Message-State: APjAAAV7JTV4Z/eNuauO6YNjamUg0NbCXFFfpJesMhHNNrjRZo0JH2/x xAf5Su5NudJcu89zt3zhYRIi45uNkco= X-Google-Smtp-Source: APXvYqzb0gGj0/PMWQCncqJhU6+Ai2NOzdrWMWxosPpz+EUdrxcMkBj3eIvshd4uoQdu/c4UqIfEDA== X-Received: by 2002:a63:b242:: with SMTP id t2mr12162038pgo.451.1552813729466; Sun, 17 Mar 2019 02:08:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:30 -0700 Message-Id: <20190317090834.5552-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1 v2 09/13] tcg/ppc: Support vector shift by immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Altivec, this is done via vector shift by vector, and loading the immediate into a register. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 8ba5668fae..5797ad35d5 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -147,7 +147,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 85e332fcd3..d91bc9a229 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) =20 +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) + #define VAND VX4(1028) #define VANDC VX4(1092) #define VNOR VX4(1284) @@ -2849,8 +2859,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return vece <=3D MO_32 ? -1 : 0; default: return 0; @@ -2923,7 +2939,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 },=20 smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 },=20 umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 },=20 - smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }; + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, + shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, + shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -2969,6 +2988,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umax_vec: insn =3D umax_op[vece]; break; + case INDEX_op_shlv_vec: + insn =3D shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn =3D shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn =3D sarv_op[vece]; + break; case INDEX_op_and_vec: insn =3D VAND; break; @@ -3040,6 +3068,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); } =20 +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { @@ -3091,14 +3131,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, { va_list va; TCGv_vec v0, v1, v2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); =20 switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; case INDEX_op_cmp_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; default: @@ -3299,6 +3350,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15528143519561021.5243110296316; Sun, 17 Mar 2019 02:19:11 -0700 (PDT) Received: from localhost ([127.0.0.1]:52204 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rwf-0005D2-M5 for importer@patchew.org; Sun, 17 Mar 2019 05:19:05 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmo-0005kh-4a for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmm-0004DY-Fe for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:54 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:35906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmm-0004D8-21 for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:52 -0400 Received: by mail-pf1-x436.google.com with SMTP id p10so2418570pff.3 for ; Sun, 17 Mar 2019 02:08:51 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HIQEudpRWlN5xdTx9c+W/8J2x/PPALhy0uzfy+9f2a8=; b=aZdX2FNCMBRt9I/qurvRPcUNl8/JQk3+VLCt2GMdv91gwsKcwTKMWBCsha1S+tMU2y jMZCYSfp01AX5onJVPJ9Sv/ESCOsAiAo2QlOEr705HwVUL9W6o3kSZbGYAeIYxnYhZpf Lc82aNOwAdI9g/K7Kf7O995jlxxjYErDU6JTG7zVts/gqETrj05gIqDWtfDIWOqyy1MA rg7yG40jRpQxqqhY2Mh67t5fpp3gbMDeriAF2sF+/NwSle0um59TJPG3sz0ibDV08WXb 4NBAYfBHkC8C9orPGhC2R/Dz/ZEIu4c9EYYqrrrxyXc6doJyxYQWI9ExhnL2YU1bfrYA MsXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HIQEudpRWlN5xdTx9c+W/8J2x/PPALhy0uzfy+9f2a8=; b=dt/sPqggP9xT7kETMHmsURZ81IXxwzUY5JSSGShensQN4eHZgJK54KBU+dzMoG85r1 vYkSAxewGz9oCa+h3k7bFadW2pQqP5uSqWoOuVSnrzKll659F3iJNQAu9f2zlgpbbpxi HPQ7TZc3Cc9h+ZEGLTUOIChJB2oC4W5DwH4W48ZntUf+7PI/0FHgwNhXWlQ2hzSCK0gm IUPM+x2fmDVL58C4O2+CtAiPVIGVtLy6gLbhcm9N5Mdz7FNP8iENI5FE0XQ+22Vw/5sY 2A72siyFDSjgfzS9l21NlcEIqZLra7lbU7wzZUBTbhDd2dB/AXUmzDp3rBJ4EEf7lHAt kWOA== X-Gm-Message-State: APjAAAWWP+kArSJBbPFtRrRFuDfd7K4JevEnR0mnsj3gIwQ2A2X998Ut vwekDSyJa9idEetmPCeGSLcqmM3rHMo= X-Google-Smtp-Source: APXvYqz7rGlk9tLkuLTYCvUNOjWjmzWUc/5kDbYN6EwSFdSb6e6PSw7juNipJo6Cz1avbzSdN2Te6A== X-Received: by 2002:a63:6ecb:: with SMTP id j194mr12515826pgc.250.1552813730683; Sun, 17 Mar 2019 02:08:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:31 -0700 Message-Id: <20190317090834.5552-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PATCH for-4.1 v2 10/13] tcg/ppc: Support vector multiply X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Altivec, this is always an expansion. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.opc.h | 8 +++ tcg/ppc/tcg-target.inc.c | 112 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h index 4816a6c3d4..5c6a5ad52c 100644 --- a/tcg/ppc/tcg-target.opc.h +++ b/tcg/ppc/tcg-target.opc.h @@ -1,3 +1,11 @@ /* Target-specific opcodes for host vector expansion. These will be emitted by tcg_expand_vec_op. For those familiar with GCC internals, consider these to be UNSPEC with names. */ + +DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) +DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d91bc9a229..4c5943be03 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -526,6 +526,25 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VSRAB VX4(772) #define VSRAH VX4(836) #define VSRAW VX4(900) +#define VRLB VX4(4) +#define VRLH VX4(68) +#define VRLW VX4(132) + +#define VMULEUB VX4(520) +#define VMULEUH VX4(584) +#define VMULOUB VX4(8) +#define VMULOUH VX4(72) +#define VMSUMUHM VX4(38) + +#define VMRGHB VX4(12) +#define VMRGHH VX4(76) +#define VMRGHW VX4(140) +#define VMRGLB VX4(268) +#define VMRGLH VX4(332) +#define VMRGLW VX4(396) + +#define VPKUHUM VX4(14) +#define VPKUWUM VX4(78) =20 #define VAND VX4(1028) #define VANDC VX4(1092) @@ -2864,6 +2883,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: @@ -2942,7 +2962,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, - sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }, + mrgh_op[4] =3D { VMRGHB, VMRGHH, VMRGHW, 0 }, + mrgl_op[4] =3D { VMRGLB, VMRGLH, VMRGLW, 0 }, + muleu_op[4] =3D { VMULEUB, VMULEUH, 0, 0 }, + mulou_op[4] =3D { VMULOUB, VMULOUH, 0, 0 }, + pkum_op[4] =3D { VPKUHUM, VPKUWUM, 0, 0 }, + rotl_op[4] =3D { VRLB, VRLH, VRLW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3060,6 +3086,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } return; =20 + case INDEX_op_ppc_mrgh_vec: + insn =3D mrgh_op[vece]; + break; + case INDEX_op_ppc_mrgl_vec: + insn =3D mrgl_op[vece]; + break; + case INDEX_op_ppc_muleu_vec: + insn =3D muleu_op[vece]; + break; + case INDEX_op_ppc_mulou_vec: + insn =3D mulou_op[vece]; + break; + case INDEX_op_ppc_pkum_vec: + insn =3D pkum_op[vece]; + break; + case INDEX_op_ppc_rotl_vec: + insn =3D rotl_op[vece]; + break; + case INDEX_op_ppc_msum_vec: + tcg_debug_assert(vece =3D=3D MO_16); + tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])= ); + return; + default: g_assert_not_reached(); } @@ -3126,6 +3175,53 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, } } =20 +static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + TCGv_vec t2 =3D tcg_temp_new_vec(type); + TCGv_vec t3, t4; + + switch (vece) { + case MO_8: + case MO_16: + vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v0), tcgv_vec_arg(t1)); + break; + + case MO_32: + t3 =3D tcg_temp_new_vec(type); + t4 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(MO_8, t4, -16); + vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_dupi_vec(MO_8, t3, 0); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), + tcgv_vec_arg(t3), tcgv_vec_arg(t4)); + tcg_gen_add_vec(MO_32, v0, t2, t3); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -3152,6 +3248,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_mul_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; default: g_assert_not_reached(); } @@ -3198,6 +3298,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; + static const TCGTargetOpDef v_v_v_v + =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -3353,6 +3455,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_ppc_mrgh_vec: + case INDEX_op_ppc_mrgl_vec: + case INDEX_op_ppc_muleu_vec: + case INDEX_op_ppc_mulou_vec: + case INDEX_op_ppc_pkum_vec: + case INDEX_op_ppc_rotl_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: @@ -3361,6 +3469,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_vec: case INDEX_op_dupm_vec: return &v_r; + case INDEX_op_ppc_msum_vec: + return &v_v_v_v; =20 default: return NULL; --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814192625790.9853075611444; Sun, 17 Mar 2019 02:16:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:52187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Ru8-0003Xh-G6 for importer@patchew.org; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 11/13] tcg/ppc: Update vector support to v2.06 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes double-word loads and stores, double-word load and splat, and double-word permute. All of which require multiple operations in the base Altivec instruction set. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 4c5943be03..e6f3dca394 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -66,6 +66,7 @@ static tcg_insn_unit *tb_ret_addr; =20 bool have_isa_altivec; bool have_isa_2_06; +bool have_isa_2_06_vsx; bool have_isa_3_00; =20 #define HAVE_ISA_2_06 have_isa_2_06 @@ -470,9 +471,12 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define LVEBX XO31(7) #define LVEHX XO31(39) #define LVEWX XO31(71) +#define LXSDX XO31(588) /* v2.06 */ +#define LXVDSX XO31(332) /* v2.06 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) +#define STXSDX XO31(716) /* v2.06 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -562,6 +566,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VPERM VX4(43) #define VSLDOI VX4(44) =20 +#define XXPERMDI (OPCD(60) | (10 << 3)) /* 2.06 */ + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -853,6 +859,15 @@ static void tcg_out_imm_vec(TCGContext *s, TCGReg ret, uint64_t t =3D l; l =3D h; h =3D t; #endif =20 + if (have_isa_2_06_vsx && l =3D=3D h) { + new_pool_label(s, l, R_PPC_ADDR16, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); + tcg_out32(s, LXVDSX | 1 | VRT(ret) | RB(TCG_REG_TMP1)); + return; + } + /* FIXME: 32-bit altivec */ new_pool_l2(s, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr, h, l); @@ -1114,6 +1129,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg ret, /* fallthru */ case TCG_TYPE_V64: tcg_debug_assert(ret >=3D 32); + if (have_isa_2_06_vsx) { + tcg_out_mem_long(s, 0, LXSDX | 1, ret & 31, base, offset); + break; + } assert((offset & 7) =3D=3D 0); tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset); if (offset & 8) { @@ -1157,6 +1176,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, /* fallthru */ case TCG_TYPE_V64: tcg_debug_assert(arg >=3D 32); + if (have_isa_2_06_vsx) { + tcg_out_mem_long(s, 0, STXSDX | 1, arg & 31, base, offset); + break; + } assert((offset & 7) =3D=3D 0); if (offset & 8) { tcg_out32(s, VSLDOI | VRT(TCG_VEC_TMP1) @@ -2927,6 +2950,10 @@ static void tcg_out_dupm_vec(TCGContext *s, unsigned= vece, TCGReg out, tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); break; case MO_64: + if (have_isa_2_06_vsx) { + tcg_out_mem_long(s, 0, LXVDSX | 1, out, base, offset); + break; + } assert((offset & 7) =3D=3D 0); tcg_out_mem_long(s, 0, LVX, out, base, offset); /* FIXME: 32-bit altivec */ @@ -3054,6 +3081,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out32(s, VSPLTW | VRT(a0) | VRB(a1) | (1 << 16)); break; case MO_64: + if (have_isa_2_06_vsx) { + tcg_out32(s, XXPERMDI | 7 | VRT(a0) | VRA(a1) | VRB(a1)); + break; + } /* FIXME: 32-bit altivec */ tcg_out_dupi_vec(s, TCG_TYPE_V128, TCG_VEC_TMP1, 0x0001020304050607ull); @@ -3487,6 +3518,9 @@ static void tcg_target_init(TCGContext *s) } if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 =3D true; + if (hwcap & PPC_FEATURE_HAS_VSX) { + have_isa_2_06_vsx =3D true; + } } #ifdef PPC_FEATURE2_ARCH_3_00 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814355439852.9092792539327; Sun, 17 Mar 2019 02:19:15 -0700 (PDT) Received: from localhost ([127.0.0.1]:52206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rwj-0005Fa-7r for importer@patchew.org; Sun, 17 Mar 2019 05:19:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47780) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmr-0005oG-In for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.1 v2 12/13] tcg/ppc: Update vector support to v2.07 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes single-word loads and stores, lots of double-word arithmetic, and a few extra logical operations. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 3 +- tcg/ppc/tcg-target.inc.c | 155 +++++++++++++++++++++++++++++++++------ 2 files changed, 134 insertions(+), 24 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5797ad35d5..4bbb33df7e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -60,6 +60,7 @@ typedef enum { =20 extern bool have_isa_altivec; extern bool have_isa_2_06; +extern bool have_isa_2_07_vsx; extern bool have_isa_3_00; =20 /* optional instructions automatically implemented */ @@ -142,7 +143,7 @@ extern bool have_isa_3_00; #endif =20 #define TCG_TARGET_HAS_andc_vec 1 -#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index e6f3dca394..b8df9b55cf 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr; bool have_isa_altivec; bool have_isa_2_06; bool have_isa_2_06_vsx; +bool have_isa_2_07_vsx; bool have_isa_3_00; =20 #define HAVE_ISA_2_06 have_isa_2_06 @@ -473,10 +474,12 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define LVEWX XO31(71) #define LXSDX XO31(588) /* v2.06 */ #define LXVDSX XO31(332) /* v2.06 */ +#define LXSIWZX XO31(12) /* v2.07 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) #define STXSDX XO31(716) /* v2.06 */ +#define STXSIWX XO31(140) /* v2.07 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -487,6 +490,7 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VADDSWS VX4(896) #define VADDUWS VX4(640) #define VADDUWM VX4(128) +#define VADDUDM VX4(192) /* v2.07 */ =20 #define VSUBSBS VX4(1792) #define VSUBUBS VX4(1536) @@ -497,47 +501,62 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define VSUBSWS VX4(1920) #define VSUBUWS VX4(1664) #define VSUBUWM VX4(1152) +#define VSUBUDM VX4(1216) /* v2.07 */ =20 #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) +#define VMAXSD VX4(450) /* v2.07 */ #define VMAXUB VX4(2) #define VMAXUH VX4(66) #define VMAXUW VX4(130) +#define VMAXUD VX4(194) /* v2.07 */ #define VMINSB VX4(770) #define VMINSH VX4(834) #define VMINSW VX4(898) +#define VMINSD VX4(962) /* v2.07 */ #define VMINUB VX4(514) #define VMINUH VX4(578) #define VMINUW VX4(642) +#define VMINUD VX4(706) /* v2.07 */ =20 #define VCMPEQUB VX4(6) #define VCMPEQUH VX4(70) #define VCMPEQUW VX4(134) +#define VCMPEQUD VX4(199) /* v2.07 */ #define VCMPGTSB VX4(774) #define VCMPGTSH VX4(838) #define VCMPGTSW VX4(902) +#define VCMPGTSD VX4(967) /* v2.07 */ #define VCMPGTUB VX4(518) #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) +#define VCMPGTUD VX4(711) /* v2.07 */ =20 #define VSLB VX4(260) #define VSLH VX4(324) #define VSLW VX4(388) +#define VSLD VX4(1476) /* v2.07 */ #define VSRB VX4(516) #define VSRH VX4(580) #define VSRW VX4(644) +#define VSRD VX4(1732) /* v2.07 */ #define VSRAB VX4(772) #define VSRAH VX4(836) #define VSRAW VX4(900) +#define VSRAD VX4(964) /* v2.07 */ #define VRLB VX4(4) #define VRLH VX4(68) #define VRLW VX4(132) +#define VRLD VX4(196) /* v2.07 */ =20 #define VMULEUB VX4(520) #define VMULEUH VX4(584) +#define VMULEUW VX4(648) /* v2.07 */ #define VMULOUB VX4(8) #define VMULOUH VX4(72) +#define VMULOUW VX4(136) /* v2.07 */ +#define VMULUWM VX4(137) /* v2.07 */ #define VMSUMUHM VX4(38) =20 #define VMRGHB VX4(12) @@ -555,6 +574,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VNOR VX4(1284) #define VOR VX4(1156) #define VXOR VX4(1220) +#define VEQV VX4(1668) /* v2.07 */ +#define VNAND VX4(1412) /* v2.07 */ +#define VORC VX4(1348) /* v2.07 */ =20 #define VSPLTB VX4(524) #define VSPLTH VX4(588) @@ -568,6 +590,11 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, =20 #define XXPERMDI (OPCD(60) | (10 << 3)) /* 2.06 */ =20 +#define MFVSRD XO31(51) /* v2.07 */ +#define MFVSRWZ XO31(115) /* v2.07 */ +#define MTVSRD XO31(179) /* v2.07 */ +#define MTVSRWZ XO31(179) /* v2.07 */ + #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) #define RA(r) ((r)<<16) @@ -691,7 +718,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) if (ret < 32 && arg < 32) { tcg_out32(s, OR | SAB(arg, ret, arg)); break; - } else if (ret < 32 || arg < 32) { + } else if (ret < 32 && have_isa_2_07_vsx) { + tcg_out32(s, (type =3D=3D TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) + | VRT(arg) | RA(ret) | 1); + break; + } else if (arg < 32 && have_isa_2_07_vsx) { + tcg_out32(s, (type =3D=3D TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) + | VRT(ret) | RA(arg) | 1); + break; + } else { /* Altivec does not support vector/integer moves. */ return false; } @@ -1113,6 +1148,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg ret, tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); break; } + if (have_isa_2_07_vsx) { + tcg_out_mem_long(s, 0, LXSIWZX | 1, ret & 31, base, offset); + break; + } assert((offset & 3) =3D=3D 0); tcg_out_mem_long(s, 0, LVEWX, ret & 31, base, offset); shift =3D (offset - 4) & 0xc; @@ -1159,6 +1198,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, tcg_out_mem_long(s, STW, STWX, arg, base, offset); break; } + if (have_isa_2_07_vsx) { + tcg_out_mem_long(s, 0, STXSIWX | 1, arg & 31, base, offset); + break; + } assert((offset & 3) =3D=3D 0); shift =3D (offset - 4) & 0xc; if (shift) { @@ -2891,26 +2934,39 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_not_vec: case INDEX_op_dupm_vec: return 1; + case INDEX_op_orc_vec: + return have_isa_2_07_vsx; case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return vece <=3D MO_32 || have_isa_2_07_vsx; case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: - case INDEX_op_mul_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return vece <=3D MO_32 ? -1 : 0; + return vece <=3D MO_32 || have_isa_2_07_vsx ? -1 : 0; + case INDEX_op_mul_vec: + switch (vece) { + case MO_8: + case MO_16: + return -1; + case MO_32: + return have_isa_2_07_vsx ? 1 : -1; + case MO_64: + return have_isa_2_07_vsx ? -1 : 0; + } + return 0; default: return 0; } @@ -2974,28 +3030,28 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, const TCGArg *args, const int *const_args) { static const uint32_t - add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, 0 }, - sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, 0 }, - eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, - gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, - gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, + sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, ussub_op[4] =3D { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, - umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 },=20 - smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 },=20 - umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 },=20 - smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, - shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, - shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, - sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }, + umin_op[4] =3D { VMINUB, VMINUH, VMINUW, VMINUD },=20 + smin_op[4] =3D { VMINSB, VMINSH, VMINSW, VMINSD },=20 + umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, VMAXUD },=20 + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, + shlv_op[4] =3D { VSLB, VSLH, VSLW, VSLD }, + shrv_op[4] =3D { VSRB, VSRH, VSRW, VSRD }, + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, VSRAD }, mrgh_op[4] =3D { VMRGHB, VMRGHH, VMRGHW, 0 }, mrgl_op[4] =3D { VMRGLB, VMRGLH, VMRGLW, 0 }, - muleu_op[4] =3D { VMULEUB, VMULEUH, 0, 0 }, - mulou_op[4] =3D { VMULOUB, VMULOUH, 0, 0 }, + muleu_op[4] =3D { VMULEUB, VMULEUH, VMULEUW, 0 }, + mulou_op[4] =3D { VMULOUB, VMULOUH, VMULOUW, 0 }, pkum_op[4] =3D { VPKUHUM, VPKUWUM, 0, 0 }, - rotl_op[4] =3D { VRLB, VRLH, VRLW, 0 }; + rotl_op[4] =3D { VRLB, VRLH, VRLW, VRLD }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3017,6 +3073,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_mul_vec: + tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07_vsx); + insn =3D VMULUWM; + break; case INDEX_op_ssadd_vec: insn =3D ssadd_op[vece]; break; @@ -3066,8 +3126,28 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, insn =3D VNOR; a2 =3D a1; break; + case INDEX_op_orc_vec: + insn =3D VORC; + break; =20 case INDEX_op_dup_vec: + if (a1 < 32) { + bool ok; + switch (vece) { + case MO_64: + ok =3D tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + break; + case MO_32: + case MO_16: + case MO_8: + ok =3D tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + break; + default: + g_assert_not_reached(); + } + tcg_debug_assert(ok); + a1 =3D a0; + } /* Recall we use VSX integer loads, so the integer is right justified within the left (zero-index) double-word. */ switch (vece) { @@ -3165,7 +3245,7 @@ static void expand_vec_cmp(TCGType type, unsigned vec= e, TCGv_vec v0, { bool need_swap =3D false, need_inv =3D false; =20 - tcg_debug_assert(vece <=3D MO_32); + tcg_debug_assert(vece <=3D MO_32 || have_isa_2_07_vsx); =20 switch (cond) { case TCG_COND_EQ: @@ -3229,6 +3309,7 @@ static void expand_vec_mul(TCGType type, unsigned vec= e, TCGv_vec v0, break; =20 case MO_32: + tcg_debug_assert(!have_isa_2_07_vsx); t3 =3D tcg_temp_new_vec(type); t4 =3D tcg_temp_new_vec(type); tcg_gen_dupi_vec(MO_8, t4, -16); @@ -3246,6 +3327,27 @@ static void expand_vec_mul(TCGType type, unsigned ve= ce, TCGv_vec v0, tcg_temp_free_vec(t4); break; =20 + case MO_64: + tcg_debug_assert(have_isa_2_07_vsx); + t3 =3D tcg_temp_new_vec(type); + t4 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(MO_8, t4, 32); + vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_64, tcgv_vec_arg(t2), + tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_32, tcgv_vec_arg(t3), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_muleu_vec, type, MO_32, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_add_vec(MO_64, t2, t2, t3); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t2), + tcgv_vec_arg(t2), tcgv_vec_arg(t4)); + tcg_gen_add_vec(MO_64, v0, t1, t2); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + default: g_assert_not_reached(); } @@ -3327,6 +3429,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rZM", "r", "r" } }; static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; + static const TCGTargetOpDef v_vr =3D { .args_ct_str =3D { "v", "vr" } = }; static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; static const TCGTargetOpDef v_v_v_v @@ -3494,8 +3597,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ppc_rotl_vec: return &v_v_v; case INDEX_op_not_vec: - case INDEX_op_dup_vec: return &v_v; + case INDEX_op_dup_vec: + return have_isa_2_07_vsx ? &v_vr : &v_v; case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_dupm_vec: @@ -3522,6 +3626,11 @@ static void tcg_target_init(TCGContext *s) have_isa_2_06_vsx =3D true; } } + if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { + if (hwcap & PPC_FEATURE_HAS_VSX) { + have_isa_2_07_vsx =3D true; + } + } #ifdef PPC_FEATURE2_ARCH_3_00 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { have_isa_3_00 =3D true; --=20 2.17.2 From nobody Thu May 2 22:04:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552814471150876.2209292906066; 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X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH for-4.1 v2 13/13] tcg/ppc: Update vector support to v3.00 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes vector load/store with immediate offset, some extra move and splat insns, compare ne, and negate. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 3 +- tcg/ppc/tcg-target.inc.c | 115 +++++++++++++++++++++++++++++---------- 2 files changed, 89 insertions(+), 29 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 4bbb33df7e..2babcff45f 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -62,6 +62,7 @@ extern bool have_isa_altivec; extern bool have_isa_2_06; extern bool have_isa_2_07_vsx; extern bool have_isa_3_00; +extern bool have_isa_3_00_vsx; =20 /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ @@ -145,7 +146,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_andc_vec 1 #define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx #define TCG_TARGET_HAS_not_vec 1 -#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_neg_vec have_isa_3_00_vsx #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index b8df9b55cf..3e99d3cadb 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -69,6 +69,7 @@ bool have_isa_2_06; bool have_isa_2_06_vsx; bool have_isa_2_07_vsx; bool have_isa_3_00; +bool have_isa_3_00_vsx; =20 #define HAVE_ISA_2_06 have_isa_2_06 #define HAVE_ISEL have_isa_2_06 @@ -475,11 +476,16 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define LXSDX XO31(588) /* v2.06 */ #define LXVDSX XO31(332) /* v2.06 */ #define LXSIWZX XO31(12) /* v2.07 */ +#define LXV (OPCD(61) | 1) /* v3.00 */ +#define LXSD (OPCD(51) | 2) /* v3.00 */ +#define LXVWSX XO31(364) /* v3.00 */ =20 #define STVX XO31(231) #define STVEWX XO31(199) #define STXSDX XO31(716) /* v2.06 */ #define STXSIWX XO31(140) /* v2.07 */ +#define STXV (OPCD(61) | 5) /* v3.00 */ +#define STXSD (OPCD(61) | 2) /* v3.00 */ =20 #define VADDSBS VX4(768) #define VADDUBS VX4(512) @@ -503,6 +509,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VSUBUWM VX4(1152) #define VSUBUDM VX4(1216) /* v2.07 */ =20 +#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ +#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ + #define VMAXSB VX4(258) #define VMAXSH VX4(322) #define VMAXSW VX4(386) @@ -532,6 +541,9 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) #define VCMPGTUD VX4(711) /* v2.07 */ +#define VCMPNEB VX4(7) /* v3.00 */ +#define VCMPNEH VX4(71) /* v3.00 */ +#define VCMPNEW VX4(135) /* v3.00 */ =20 #define VSLB VX4(260) #define VSLH VX4(324) @@ -588,12 +600,15 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define VPERM VX4(43) #define VSLDOI VX4(44) =20 -#define XXPERMDI (OPCD(60) | (10 << 3)) /* 2.06 */ +#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */ +#define XXSPLTIB (OPCD(60) | (360 << 1)) /* v3.00 */ =20 #define MFVSRD XO31(51) /* v2.07 */ #define MFVSRWZ XO31(115) /* v2.07 */ #define MTVSRD XO31(179) /* v2.07 */ #define MTVSRWZ XO31(179) /* v2.07 */ +#define MTVSRDD XO31(435) /* v3.00 */ +#define MTVSRWS XO31(403) /* v3.00 */ =20 #define RT(r) ((r)<<21) #define RS(r) ((r)<<21) @@ -931,6 +946,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType ty= pe, TCGReg ret, } } =20 + if (have_isa_3_00_vsx && val =3D=3D (tcg_target_long)dup_const(MO_8, v= al)) { + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11) | 1); + return; + } + /* With Altivec, we load the whole 128-bit value. */ tcg_out_imm_vec(s, ret, val, val); } @@ -1084,7 +1104,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, = int opx, TCGReg rt, TCGReg base, tcg_target_long offset) { tcg_target_long orig =3D offset, l0, l1, extra =3D 0, align =3D 0; - bool is_store =3D false; + bool is_int_store =3D false; TCGReg rs =3D TCG_REG_TMP1; =20 switch (opi) { @@ -1097,11 +1117,20 @@ static void tcg_out_mem_long(TCGContext *s, int opi= , int opx, TCGReg rt, break; } break; + case LXSD: + case STXSD: + align =3D 3; + break; + case LXV: case LXV | 8: + case STXV: case STXV | 8: + /* The |8 cases force altivec registers. */ + align =3D 15; + break; case STD: align =3D 3; /* FALLTHRU */ case STB: case STH: case STW: - is_store =3D true; + is_int_store =3D true; break; } =20 @@ -1110,7 +1139,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, = int opx, TCGReg rt, if (rs =3D=3D base) { rs =3D TCG_REG_R0; } - tcg_debug_assert(!is_store || rs !=3D rt); + tcg_debug_assert(!is_int_store || rs !=3D rt); tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); tcg_out32(s, opx | TAB(rt, base, rs)); return; @@ -1169,7 +1198,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, case TCG_TYPE_V64: tcg_debug_assert(ret >=3D 32); if (have_isa_2_06_vsx) { - tcg_out_mem_long(s, 0, LXSDX | 1, ret & 31, base, offset); + tcg_out_mem_long(s, have_isa_3_00_vsx ? LXSD : 0, LXSDX | 1, + ret & 31, base, offset); break; } assert((offset & 7) =3D=3D 0); @@ -1180,7 +1210,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, break; case TCG_TYPE_V128: tcg_debug_assert(ret >=3D 32); - tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset); + tcg_out_mem_long(s, have_isa_3_00_vsx ? LXV | 8 : 0, LVX, + ret & 31, base, offset); break; default: g_assert_not_reached(); @@ -1220,7 +1251,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, case TCG_TYPE_V64: tcg_debug_assert(arg >=3D 32); if (have_isa_2_06_vsx) { - tcg_out_mem_long(s, 0, STXSDX | 1, arg & 31, base, offset); + tcg_out_mem_long(s, have_isa_3_00_vsx ? STXSD : 0, + STXSDX | 1, arg & 31, base, offset); break; } assert((offset & 7) =3D=3D 0); @@ -1234,7 +1266,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, break; case TCG_TYPE_V128: tcg_debug_assert(arg >=3D 32); - tcg_out_mem_long(s, 0, STVX, arg & 31, base, offset); + tcg_out_mem_long(s, have_isa_3_00_vsx ? STXV | 8 : 0, STVX, + arg & 31, base, offset); break; default: g_assert_not_reached(); @@ -2956,6 +2989,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_shri_vec: case INDEX_op_sari_vec: return vece <=3D MO_32 || have_isa_2_07_vsx ? -1 : 0; + case INDEX_op_neg_vec: + return vece >=3D MO_32 && have_isa_3_00_vsx; case INDEX_op_mul_vec: switch (vece) { case MO_8: @@ -2997,6 +3032,10 @@ static void tcg_out_dupm_vec(TCGContext *s, unsigned= vece, TCGReg out, tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); break; case MO_32: + if (have_isa_3_00_vsx) { + tcg_out_mem_long(s, 0, LXVWSX | 1, out, base, offset); + break; + } assert((offset & 3) =3D=3D 0); tcg_out_mem_long(s, 0, LVEWX, out, base, offset); elt =3D extract32(offset, 2, 2); @@ -3032,7 +3071,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, static const uint32_t add_op[4] =3D { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + neg_op[4] =3D { 0, 0, VNEGW, VNEGD }, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, @@ -3073,6 +3114,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_neg_vec: + insn =3D neg_op[vece]; + a2 =3D a1; + a1 =3D 0; + break; case INDEX_op_mul_vec: tcg_debug_assert(vece =3D=3D MO_32 && have_isa_2_07_vsx); insn =3D VMULUWM; @@ -3135,9 +3181,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, bool ok; switch (vece) { case MO_64: + if (have_isa_3_00_vsx) { + tcg_out32(s, MTVSRDD | 1 | VRT(a0) | RA(a1) | RB(a1)); + return; + } ok =3D tcg_out_mov(s, TCG_TYPE_I64, a0, a1); break; case MO_32: + if (have_isa_3_00_vsx) { + tcg_out32(s, MTVSRWS | 1 | VRT(a0) | RA(a1)); + return; + } + /* fall through */ case MO_16: case MO_8: ok =3D tcg_out_mov(s, TCG_TYPE_I32, a0, a1); @@ -3175,27 +3230,23 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, return; =20 case INDEX_op_cmp_vec: - { - TCGCond cond =3D args[3]; - - switch (cond) { - case TCG_COND_EQ: - insn =3D eq_op[vece]; - break; - case TCG_COND_GT: - insn =3D gts_op[vece]; - break; - case TCG_COND_GTU: - insn =3D gtu_op[vece]; - break; - default: - g_assert_not_reached(); - } - tcg_debug_assert(insn !=3D 0); - - tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); + switch (args[3]) { + case TCG_COND_EQ: + insn =3D eq_op[vece]; + break; + case TCG_COND_NE: + insn =3D ne_op[vece]; + break; + case TCG_COND_GT: + insn =3D gts_op[vece]; + break; + case TCG_COND_GTU: + insn =3D gtu_op[vece]; + break; + default: + g_assert_not_reached(); } - return; + break; =20 case INDEX_op_ppc_mrgh_vec: insn =3D mrgh_op[vece]; @@ -3253,6 +3304,10 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, case TCG_COND_GTU: break; case TCG_COND_NE: + if (have_isa_3_00_vsx && vece <=3D MO_32) { + break; + } + /* fall through */ case TCG_COND_LE: case TCG_COND_LEU: need_inv =3D true; @@ -3597,6 +3652,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ppc_rotl_vec: return &v_v_v; case INDEX_op_not_vec: + case INDEX_op_neg_vec: return &v_v; case INDEX_op_dup_vec: return have_isa_2_07_vsx ? &v_vr : &v_v; @@ -3634,6 +3690,9 @@ static void tcg_target_init(TCGContext *s) #ifdef PPC_FEATURE2_ARCH_3_00 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { have_isa_3_00 =3D true; + if (hwcap & PPC_FEATURE_HAS_VSX) { + have_isa_3_00_vsx =3D true; + } } #endif =20 --=20 2.17.2