Add a FIXME regarding exceptions during the second store.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/insn-data.def      |  2 ++
 target/s390x/translate_vx.inc.c | 22 ++++++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ab3309c54b..2b18f4ab54 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1035,6 +1035,8 @@
     F(0xe78d, VSEL,    VRR_e, V,   0, 0, 0, 0, vsel, 0, IF_VEC)
 /* VECTOR SIGN EXTEND TO DOUBLEWORD */
     F(0xe75f, VSEG,    VRR_a, V,   0, 0, 0, 0, vseg, 0, IF_VEC)
+/* VECTOR STORE */
+    F(0xe70e, VST,     VRX,   V,   la2, 0, 0, 0, vst, 0, IF_VEC)
 
 #ifndef CONFIG_USER_ONLY
 /* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 23cdae0970..69b12e79a1 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -137,6 +137,17 @@ static void load_vec_element(DisasContext *s, uint8_t reg, uint8_t enr,
     tcg_temp_free_i64(tmp);
 }
 
+static void store_vec_element(DisasContext *s, uint8_t reg, uint8_t enr,
+                              TCGv_i64 addr, TCGMemOp es)
+{
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    read_vec_element_i64(tmp, reg, enr, es);
+    tcg_gen_qemu_st_i64(tmp, addr, get_mem_index(s), MO_TE | es);
+
+    tcg_temp_free_i64(tmp);
+}
+
 static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
                                     uint8_t es)
 {
@@ -764,3 +775,14 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
     tcg_temp_free_i64(tmp);
     return DISAS_NEXT;
 }
+
+static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
+{
+    /*
+     * FIXME: On exceptions we must not modify any memory.
+     */
+    store_vec_element(s, get_field(s->fields, v1), 0, o->addr1, MO_64);
+    gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+    store_vec_element(s, get_field(s->fields, v1), 1, o->addr1, MO_64);
+    return DISAS_NEXT;
+}
-- 
2.17.2

On 2/26/19 3:39 AM, David Hildenbrand wrote:
> +static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
> +{
> +    /*
> +     * FIXME: On exceptions we must not modify any memory.
> +     */
> +    store_vec_element(s, get_field(s->fields, v1), 0, o->addr1, MO_64);
> +    gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
> +    store_vec_element(s, get_field(s->fields, v1), 1, o->addr1, MO_64);
> +    return DISAS_NEXT;

Should handle alignment though.

FWIW, there is a probe_write function that can be called to make sure a region
is writable before actually accessing it.  But this is common enough that we
should probably just handle 16-byte quantities as a native tcg type.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

On 28.02.19 00:46, Richard Henderson wrote:
> On 2/26/19 3:39 AM, David Hildenbrand wrote:
>> +static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
>> +{
>> +    /*
>> +     * FIXME: On exceptions we must not modify any memory.
>> +     */
>> +    store_vec_element(s, get_field(s->fields, v1), 0, o->addr1, MO_64);
>> +    gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
>> +    store_vec_element(s, get_field(s->fields, v1), 1, o->addr1, MO_64);
>> +    return DISAS_NEXT;
> 
> Should handle alignment though.

Again, as unaligned access must not trigger an exception, I don't think
we can use MO_ALIGN.

> 
> FWIW, there is a probe_write function that can be called to make sure a region
> is writable before actually accessing it.  But this is common enough that we
> should probably just handle 16-byte quantities as a native tcg type.

That would make most sense. It won't help for the VECTOR_STORE_MULTIPLE
part, though.

I'll keep it as is for now.

Thanks!

> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~
> 


-- 

Thanks,

David / dhildenb