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[PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model

Pavel Dovgalyuk posted 4 patches 3 years, 7 months ago
[PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model
Posted by Pavel Dovgalyuk 3 years, 7 months ago 
This patch adds Cavium Octeon 68XX vCPU which provides
Octeon-specific instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

--
v3 changes:
 - split the patch to instruction set introduction and new vCPU
   (suggested by Philippe Mathieu-Daudé)
v2 changes:
 - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
 target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 582f940070..7f53c94ec8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /*
+         * Octeon 68xx with MIPS64 Cavium Octeon features.
+         */
+        .name = "Octeon68XX",
+        .CP0_PRid = 0x000D9100,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+                       (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
+                       (3U << CP0C4_MMUSizeExt),
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .CP0_PageGrain = (1 << CP0PG_ELPA),
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x12F8FFFF,
+        .SEGBITS = 42,
+        .PABITS = 49,
+        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 
 #endif
 };
Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model
Posted by Pavel Dovgalyuk 3 years, 7 months ago 
ping

This is the only non-reviewed patch in the series.

On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
> This patch adds Cavium Octeon 68XX vCPU which provides
> Octeon-specific instructions.
> 
> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
> 
> --
> v3 changes:
>   - split the patch to instruction set introduction and new vCPU
>     (suggested by Philippe Mathieu-Daudé)
> v2 changes:
>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
> ---
>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>   1 file changed, 28 insertions(+)
> 
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 582f940070..7f53c94ec8 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
>           .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
>           .mmu_type = MMU_TYPE_R4000,
>       },
> +    {
> +        /*
> +         * Octeon 68xx with MIPS64 Cavium Octeon features.
> +         */
> +        .name = "Octeon68XX",
> +        .CP0_PRid = 0x000D9100,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> +                       (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
> +                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
> +                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
> +        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
> +                       (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
> +                       (3U << CP0C4_MMUSizeExt),
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 4,
> +        .CP0_PageGrain = (1 << CP0PG_ELPA),
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x12F8FFFF,
> +        .SEGBITS = 42,
> +        .PABITS = 49,
> +        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
>   
>   #endif
>   };
>
Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model
Posted by Philippe Mathieu-Daudé via 3 years, 7 months ago 
On 4/7/22 12:59, Pavel Dovgalyuk wrote:
> ping
> 
> This is the only non-reviewed patch in the series.

I've been looking for doc/datasheets but no luck (except the Linux 
kernel comments).

What kind of testing are you doing?

> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>> This patch adds Cavium Octeon 68XX vCPU which provides
>> Octeon-specific instructions.
>>
>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>
>> -- 
>> v3 changes:
>>   - split the patch to instruction set introduction and new vCPU
>>     (suggested by Philippe Mathieu-Daudé)
>> v2 changes:
>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>> ---
>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)
Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model
Posted by Pavel Dovgalyuk 3 years, 7 months ago 
On 06.07.2022 23:53, Philippe Mathieu-Daudé wrote:
> On 4/7/22 12:59, Pavel Dovgalyuk wrote:
>> ping
>>
>> This is the only non-reviewed patch in the series.
> 
> I've been looking for doc/datasheets but no luck (except the Linux 
> kernel comments).
> 
> What kind of testing are you doing?

BTW, we found SDK here: https://github.com/amitmisra16/OCTEON-SDK


> 
>> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>>> This patch adds Cavium Octeon 68XX vCPU which provides
>>> Octeon-specific instructions.
>>>
>>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>>
>>> -- 
>>> v3 changes:
>>>   - split the patch to instruction set introduction and new vCPU
>>>     (suggested by Philippe Mathieu-Daudé)
>>> v2 changes:
>>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>>> ---
>>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)
Re: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model
Posted by Pavel Dovgalyuk 3 years, 7 months ago 
On 06.07.2022 23:53, Philippe Mathieu-Daudé wrote:
> On 4/7/22 12:59, Pavel Dovgalyuk wrote:
>> ping
>>
>> This is the only non-reviewed patch in the series.
> 
> I've been looking for doc/datasheets but no luck (except the Linux 
> kernel comments).
> 
> What kind of testing are you doing?

We compared the instruction emulation with the behavior on dev board.

> 
>> On 20.06.2022 15:05, Pavel Dovgalyuk wrote:
>>> This patch adds Cavium Octeon 68XX vCPU which provides
>>> Octeon-specific instructions.
>>>
>>> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>>>
>>> -- 
>>> v3 changes:
>>>   - split the patch to instruction set introduction and new vCPU
>>>     (suggested by Philippe Mathieu-Daudé)
>>> v2 changes:
>>>   - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
>>> ---
>>>   target/mips/cpu-defs.c.inc |   28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)

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