From nobody Tue Feb 10 06:58:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ispras.ru Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655726873727393.84567043621485; Mon, 20 Jun 2022 05:07:53 -0700 (PDT) Received: from localhost ([::1]:48192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3GC8-0001D9-B8 for importer@patchew.org; Mon, 20 Jun 2022 08:07:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3GA1-0006nK-9Q for qemu-devel@nongnu.org; Mon, 20 Jun 2022 08:05:41 -0400 Received: from mail.ispras.ru ([83.149.199.84]:41526) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3G9z-0004c6-Hd for qemu-devel@nongnu.org; Mon, 20 Jun 2022 08:05:40 -0400 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 11C7940737DD; Mon, 20 Jun 2022 12:05:38 +0000 (UTC) Subject: [PATCH v3 4/4] target/mips: introduce Cavium Octeon CPU model From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net, aleksandar.rikalo@syrmia.com Date: Mon, 20 Jun 2022 15:05:37 +0300 Message-ID: <165572673785.167724.7604881144978983510.stgit@pasha-ThinkPad-X280> In-Reply-To: <165572671617.167724.12940170194930233873.stgit@pasha-ThinkPad-X280> References: <165572671617.167724.12940170194930233873.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655726876097100001 This patch adds Cavium Octeon 68XX vCPU which provides Octeon-specific instructions. Signed-off-by: Pavel Dovgalyuk -- v3 changes: - split the patch to instruction set introduction and new vCPU (suggested by Philippe Mathieu-Daud=C3=A9) v2 changes: - vCPU name changed to Octeon68XX (suggested by Richard Henderson) --- target/mips/cpu-defs.c.inc | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 582f940070..7f53c94ec8 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, .mmu_type =3D MMU_TYPE_R4000, }, + { + /* + * Octeon 68xx with MIPS64 Cavium Octeon features. + */ + .name =3D "Octeon68XX", + .CP0_PRid =3D 0x000D9100, + .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_= AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA)= | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA)= | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSP= P) , + .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | + (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef)= | + (3U << CP0C4_MMUSizeExt), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 4, + .CP0_PageGrain =3D (1 << CP0PG_ELPA), + .SYNCI_Step =3D 32, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x12F8FFFF, + .SEGBITS =3D 42, + .PABITS =3D 49, + .insn_flags =3D CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP, + .mmu_type =3D MMU_TYPE_R4000, + }, =20 #endif };