The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions

v3 changes:
 - separated vCPU model definition and decodetree for Octeon
   (suggested by Philippe Mathieu-Daudé)
 - fixed length field for EXTS/CINS (bug found by Richard Henderson)

v2 changes:
 - simplified instruction decoding and translation (suggested by Richard Henderson)

---

Pavel Dovgalyuk (4):
      target/mips: introduce decodetree structure for Cavium Octeon extension
      target/mips: implement Octeon-specific BBIT instructions
      target/mips: implement Octeon-specific arithmetic instructions
      target/mips: introduce Cavium Octeon CPU model


 target/mips/cpu-defs.c.inc         |  28 +++++
 target/mips/tcg/octeon.decode      |  35 ++++++
 target/mips/tcg/octeon_translate.c | 185 +++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+)

--
Pavel Dovgalyuk