Previous commit dbfbda3bd6bf("riscv: mm: update T-Head memory type
definitions") missed a `<` for bit shifting, result in bit[61] does not set
in _PAGE_NOCACHE_THEAD and leaves bit[0] set instead. This patch get this
fixed.

Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
 arch/riscv/include/asm/pgtable-64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index b42017d76924..b99bd66107a6 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -136,7 +136,7 @@ enum napot_cont_order {
  * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
  */
 #define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
-#define _PAGE_NOCACHE_THEAD	((1UL < 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD	((1UL << 61) | (1UL << 60))
 #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
 #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
 
-- 
2.43.0

On Tue, Feb 20, 2024 at 12:32:09AM +0800, Yangyu Chen wrote:
> Previous commit dbfbda3bd6bf("riscv: mm: update T-Head memory type
> definitions") missed a `<` for bit shifting, result in bit[61] does not set
> in _PAGE_NOCACHE_THEAD and leaves bit[0] set instead. This patch get this
> fixed.
> 
> Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
> 
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>

Good catch! We're lucky just because _PAGE_NOCACHE_THEAD isn't used now.

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>

> ---
>  arch/riscv/include/asm/pgtable-64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index b42017d76924..b99bd66107a6 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -136,7 +136,7 @@ enum napot_cont_order {
>   * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
>   */
>  #define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
> -#define _PAGE_NOCACHE_THEAD	((1UL < 61) | (1UL << 60))
> +#define _PAGE_NOCACHE_THEAD	((1UL << 61) | (1UL << 60))
>  #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
>  #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>  
> -- 
> 2.43.0
>

On Tue, Feb 20, 2024 at 12:33 AM Yangyu Chen <cyy@cyyself.name> wrote:
>
> Previous commit dbfbda3bd6bf("riscv: mm: update T-Head memory type
> definitions") missed a `<` for bit shifting, result in bit[61] does not set
> in _PAGE_NOCACHE_THEAD and leaves bit[0] set instead. This patch get this
> fixed.
>
> Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
>  arch/riscv/include/asm/pgtable-64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index b42017d76924..b99bd66107a6 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -136,7 +136,7 @@ enum napot_cont_order {
>   * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
>   */
>  #define _PAGE_PMA_THEAD                ((1UL << 62) | (1UL << 61) | (1UL << 60))
> -#define _PAGE_NOCACHE_THEAD    ((1UL < 61) | (1UL << 60))
> +#define _PAGE_NOCACHE_THEAD    ((1UL << 61) | (1UL << 60))
>  #define _PAGE_IO_THEAD         ((1UL << 63) | (1UL << 60))
>  #define _PAGE_MTMASK_THEAD     (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> --
> 2.43.0
>

Oh, my genius. Thank you very much.

Reviewed-by: Guo Ren <guoren@kernel.org>

It's for bufferable signal, so that is why it does not affect the hardware :P

-- 
Best Regards
 Guo Ren