Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..7b077af62b27 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -32,6 +32,7 @@ properties:
oneOf:
- items:
- enum:
+ - amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
--
2.36.1Hi Conor, On 11/6/23 12:37, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 Can you please queue this patch to your tree? Thanks, Michal
On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. > > Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> I thought I had already done so, but must have forgot to actually send the email. Cheers, Conor. > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 > -- > 2.36.1 >
On Thu, 09 Nov 2023 09:15:09 PST (-0800), Conor Dooley wrote: > On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: >> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. >> It is hardware compatible with classic MicroBlaze processor. >> >> Signed-off-by: Michal Simek <michal.simek@amd.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > I thought I had already done so, but must have forgot to actually send > the email. Conor asked me to pick it up, it's over staged for testing. Pretty much no chance it fails anything, so should show up on for-next soon. > > Cheers, > Conor. > >> --- >> >> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml >> index 97e8441eda1c..7b077af62b27 100644 >> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml >> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml >> @@ -32,6 +32,7 @@ properties: >> oneOf: >> - items: >> - enum: >> + - amd,mbv32 >> - andestech,ax45mp >> - canaan,k210 >> - sifive,bullet0 >> -- >> 2.36.1 >>
On 12/20/23 16:15, Palmer Dabbelt wrote: > On Thu, 09 Nov 2023 09:15:09 PST (-0800), Conor Dooley wrote: >> On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: >>> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. >>> It is hardware compatible with classic MicroBlaze processor. >>> >>> Signed-off-by: Michal Simek <michal.simek@amd.com> >> >> Acked-by: Conor Dooley <conor.dooley@microchip.com> >> I thought I had already done so, but must have forgot to actually send >> the email. > > Conor asked me to pick it up, it's over staged for testing. Pretty much > no chance it fails anything, so should show up on for-next soon. Palmer: Any update on this? Thanks, Michal
On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. How is that possible? It's a different instruction set, right? I suppose the IP interfaces (signals) are the same/compatible. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) Anyways, Acked-by: Rob Herring <robh@kernel.org> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 > -- > 2.36.1 >
On 11/8/23 09:12, Rob Herring wrote: > On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: >> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. >> It is hardware compatible with classic MicroBlaze processor. > > How is that possible? It's a different instruction set, right? I suppose > the IP interfaces (signals) are the same/compatible. Coincidentally, I asked myself the same question, so I asked my former manager who designed the ancestor of this processor. The answer is | It is still the same MicroBlaze pipeline just with a different | instruction decoder up front. The “macro ops” are now RISC V | instructions, the “micro-ops” are still the same operations in the | various MicroBlaze pipeline stages. So, yes, all the hardware interface is the same. -- Ronan KERYELL, Research Labs / San José, California. AMD Research and Advanced Development.
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