From: "Chiam, Evon" <evon.chiam@altera.com>

This series adds clock manager support for the Altera SoCFPGA Agilex72
platform: the devicetree binding and clock ID header, the clock manager
driver, and the devicetree changes that instantiate it on the Agilex72
SoC and the SoCDK board.

The Agilex72 clock manager exposes multiple register regions (clkmgr and
three GPPLLs) and provides the peripheral clocks used by the SoC. The
driver registers the PLL, peripheral, and gate clock tree, while the DT
describes the external input references and the clock manager node.

Changes in v2:
- Dropped "dt-bindings: arm: altera: fix Agilex72 compatible vendor
  prefix" and "arm64: dts: altera: move Agilex72 DT and use altr
  prefix". The Agilex72 SoC and board compatible strings keep the
  "intel," prefix and the devicetree stays in dts/intel. Moving the
  SoCFPGA devicetrees is handled by a separate series:
  https://lore.kernel.org/r/cover.1789123511.git.evon.chiam@altera.com
- Reworked the clock manager driver following review; see the per-patch
  changelogs.
- Link to v1: https://lore.kernel.org/r/cover.1786006669.git.evon.chiam@altera.com

Chiam, Evon (3):
  dt-bindings: clock: altr,agilex72-clkmgr: add Agilex72 clock manager
  clk: socfpga: agilex72: add clock manager driver for Agilex72
  arm64: dts: socfpga: agilex72: add clock manager support

 .../bindings/clock/altr,agilex72-clkmgr.yaml  |   76 +
 .../boot/dts/intel/socfpga_agilex72.dtsi      |   44 +-
 .../boot/dts/intel/socfpga_agilex72_socdk.dts |   12 +
 drivers/clk/socfpga/Kconfig                   |    3 +-
 drivers/clk/socfpga/Makefile                  |    2 +-
 drivers/clk/socfpga/clk-agilex72.c            | 1299 +++++++++++++++++
 .../dt-bindings/clock/altr,agilex72-clkmgr.h  |  115 ++
 7 files changed, 1545 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/altr,agilex72-clkmgr.yaml
 create mode 100644 drivers/clk/socfpga/clk-agilex72.c
 create mode 100644 include/dt-bindings/clock/altr,agilex72-clkmgr.h

-- 
2.43.7