.../bindings/usb/altr,agilex5-dwc3.yaml | 112 ++++++++++++++++++ .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 ++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 4 +- drivers/usb/dwc3/dwc3-generic-plat.c | 1 + 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
Agilex5 integrates a Synopsys DesignWare USB3 controller via a SoC-specific wrapper that requires dedicated clock, reset, PHY, and optional SMMU integration. The USB DMA path on the interconnect is limited to a 40-bit address width. This series adds a device tree binding for the Agilex5 DWC3 controller and introduces the corresponding USB3.1 node in the Agilex5 SoC and SoCDK device trees. The controller is placed under a simple-bus with a 40-bit dma-ranges window so the DMA/IOMMU stack respects the interconnect address width when SMMU is enabled. As the SoCDK only exposes the USB3.1 interface, the unused USB0 node is removed. On this SoC the DWC3 "ref" and "suspend" inputs share the same hardware clock source, so both clock phandles use the already published AGILEX5_USB31_SUSPEND_CLK ID (no new clock binding ID). Finally, the Agilex5 compatible string is added to the dwc3 generic platform driver so the controller can probe through that glue driver. Merging: - Patches 1 and 4 (dt-bindings + dwc3-generic-plat): USB tree - Patches 2 and 3 (arm64 dts): SoC / arm64 dts tree (or taken with the USB series if preferred, with an appropriate Ack) --- changelog: v5->v6: * Make snps,dis_u2_susphy_quirk and snps,dis_u3_susphy_quirk required. There is only one DWC3 instance on Agilex5 and both quirks are used on that node. v5 patch link: https://lore.kernel.org/all/cover.1788757821.git.adrian.ho.yin.ng@altera.com/ v4->v5: * Binding: replace unevaluatedProperties: false with additionalProperties: false, and allow only the extra DWC3 properties used on this SoC via "foo: true" (dr_mode, maximum-speed, snps,dis_u2_susphy_quirk, snps,dis_u3_susphy_quirk). v4 patch link: https://lore.kernel.org/all/cover.1788503540.git.adrian.ho.yin.ng@altera.com/ v3->v4: * Drop dt-bindings/clock and clk driver patches; do not extend the published Agilex5 clock binding. Reuse AGILEX5_USB31_SUSPEND_CLK for both "ref" and "suspend" clock inputs. * Fix usb31_bus dma-ranges cell layout (sashiko comment): use #address-cells = <2> and a Stingray-style 40-bit dma-ranges window instead of a 32-bit child address space with a truncated 1 TiB size. * Update altr,agilex5-dwc3.yaml per review: drop obvious reg/resets descriptions, order clock-names as bus_early/ref/suspend (matching snps,dwc3.yaml), and rename reset-names to core/ecc. * Limit the series to USB binding, DTS, and dwc3-generic-plat (no clk subsystem patches in the same series). v3 patch link: https://lore.kernel.org/all/cover.1786518803.git.adrian.ho.yin.ng@altera.com/ v2->v3: * Add the missing USB3.1 reference clock ID and register usb31_ref_clk as a fixed-factor clock in the Agilex5 clock driver. * Drop dma_addressable_bits core/glue changes; describe the 40-bit DMA limit in DT with dma-ranges instead. * Wrap the USB3.1 node in a simple-bus with a 40-bit dma-ranges window. * Keep Agilex5 support in dwc3-generic-plat as a compatible match only (no platform-specific DMA mask override). v2 patch link: https://lore.kernel.org/all/cover.1765249127.git.adrianhoyin.ng@altera.com/ v1->v2: * Update new binding name to match compatible. * Update binding to use single node instead of parent child node structure. * Update binding according to comments from maintainer. * Split USB3 and USB2 changes in dts into separate commits. * Update to use flattened model and use dwc3-generic-plat driver instead of dwc3-of-simple driver. * Add dma_addressable_bits as a dwc3 property which is set by the glue driver which is used to configure the dma mask in the core driver. v1 patch link: https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/ --- Adrian Ng Ho Yin (4): dt-bindings: usb: add Altera Agilex5 DWC3 controller arm64: dts: intel: agilex5: add USB3.1 controller node arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK usb: dwc3: add Altera Agilex5 support to generic platform driver .../bindings/usb/altr,agilex5-dwc3.yaml | 112 ++++++++++++++++++ .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 ++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 4 +- drivers/usb/dwc3/dwc3-generic-plat.c | 1 + 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml -- 2.49.GIT
From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> Agilex5 integrates a Synopsys DesignWare USB3 controller that is probed through dwc3-generic-plat. This series adds: 1. dt-bindings for compatible "altr,agilex5-dwc3" 2. matching entry in dwc3-generic-plat arm64 DTS enablement is posted separately. --- changelog: v6->v7: * Drop arm64 DTS patches from this series (DTS must not be mixed into a USB-targeted series). DTS is reposted separately. v6 patch link: https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@altera.com/ v5->v6: * Make snps,dis_u2_susphy_quirk and snps,dis_u3_susphy_quirk required. v5 patch link: https://lore.kernel.org/all/cover.1788757821.git.adrian.ho.yin.ng@altera.com/ v4->v5: * Binding: replace unevaluatedProperties: false with additionalProperties: false, and allow only the extra DWC3 properties used on this SoC via "foo: true". v4 patch link: https://lore.kernel.org/all/cover.1788503540.git.adrian.ho.yin.ng@altera.com/ v3->v4: * Drop clk binding/driver patches; reuse AGILEX5_USB31_SUSPEND_CLK for both "ref" and "suspend". * Update altr,agilex5-dwc3.yaml per review. * Limit the series to USB binding, DTS, and dwc3-generic-plat. v3 patch link: https://lore.kernel.org/all/cover.1786518803.git.adrian.ho.yin.ng@altera.com/ v2->v3: * Drop dma_addressable_bits; describe 40-bit DMA limit with dma-ranges. * Keep Agilex5 support in dwc3-generic-plat as a compatible match only. v2 patch link: https://lore.kernel.org/all/cover.1765249127.git.adrianhoyin.ng@altera.com/ v1->v2: * Flattened model + dwc3-generic-plat instead of dwc3-of-simple. * Split USB3 add vs USB0 disable in DTS (still wrongly kept in USB series until v7). v1 patch link: https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/ --- Adrian Ng Ho Yin (2): dt-bindings: usb: add Altera Agilex5 DWC3 controller usb: dwc3: add Altera Agilex5 support to generic platform driver .../bindings/usb/altr,agilex5-dwc3.yaml | 112 ++++++++++++++++++ drivers/usb/dwc3/dwc3-generic-plat.c | 1 + 2 files changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml base-commit: bc35965f6940a9bf834d54187b6088b8eb09206d -- 2.49.GIT
On 9/11/2026 5:04 PM, adrian.ho.yin.ng@altera.com wrote: > From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> > > Agilex5 integrates a Synopsys DesignWare USB3 controller that is probed > through dwc3-generic-plat. This series adds: > > 1. dt-bindings for compatible "altr,agilex5-dwc3" > 2. matching entry in dwc3-generic-plat > > arm64 DTS enablement is posted separately. > Hi All, Gentle reminder for this patchset. The device tree patch has been applied by the DT maintainer. https://lore.kernel.org/all/02d94760-6e5e-40cf-9354-63b9bca5d682@kernel.org/ Thanks Adrian > --- > changelog: > v6->v7: > * Drop arm64 DTS patches from this series (DTS must not be mixed into a > USB-targeted series). DTS is reposted separately. > > v6 patch link: > https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@altera.com/ > > v5->v6: > * Make snps,dis_u2_susphy_quirk and snps,dis_u3_susphy_quirk required. > > v5 patch link: > https://lore.kernel.org/all/cover.1788757821.git.adrian.ho.yin.ng@altera.com/ > > v4->v5: > * Binding: replace unevaluatedProperties: false with additionalProperties: > false, and allow only the extra DWC3 properties used on this SoC via > "foo: true". > > v4 patch link: > https://lore.kernel.org/all/cover.1788503540.git.adrian.ho.yin.ng@altera.com/ > > v3->v4: > * Drop clk binding/driver patches; reuse AGILEX5_USB31_SUSPEND_CLK for > both "ref" and "suspend". > * Update altr,agilex5-dwc3.yaml per review. > * Limit the series to USB binding, DTS, and dwc3-generic-plat. > > v3 patch link: > https://lore.kernel.org/all/cover.1786518803.git.adrian.ho.yin.ng@altera.com/ > > v2->v3: > * Drop dma_addressable_bits; describe 40-bit DMA limit with dma-ranges. > * Keep Agilex5 support in dwc3-generic-plat as a compatible match only. > > v2 patch link: > https://lore.kernel.org/all/cover.1765249127.git.adrianhoyin.ng@altera.com/ > > v1->v2: > * Flattened model + dwc3-generic-plat instead of dwc3-of-simple. > * Split USB3 add vs USB0 disable in DTS (still wrongly kept in USB > series until v7). > > v1 patch link: > https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/ > --- > > Adrian Ng Ho Yin (2): > dt-bindings: usb: add Altera Agilex5 DWC3 controller > usb: dwc3: add Altera Agilex5 support to generic platform driver > > .../bindings/usb/altr,agilex5-dwc3.yaml | 112 ++++++++++++++++++ > drivers/usb/dwc3/dwc3-generic-plat.c | 1 + > 2 files changed, 113 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml > > > base-commit: bc35965f6940a9bf834d54187b6088b8eb09206d
On Sat, Sep 19, 2026, Ng, Adrian Ho Yin wrote: > On 9/11/2026 5:04 PM, adrian.ho.yin.ng@altera.com wrote: > > From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> > > > > Agilex5 integrates a Synopsys DesignWare USB3 controller that is probed > > through dwc3-generic-plat. This series adds: > > > > 1. dt-bindings for compatible "altr,agilex5-dwc3" > > 2. matching entry in dwc3-generic-plat > > > > arm64 DTS enablement is posted separately. > > > Hi All, > > Gentle reminder for this patchset. > The device tree patch has been applied by the DT maintainer. > https://urldefense.com/v3/__https://lore.kernel.org/all/02d94760-6e5e-40cf-9354-63b9bca5d682@kernel.org/__;!!A4F2R9G_pg!fOoRba7F0n_QcIeLW1hJWdqm-cZ-1LeU5F9IMVQONnR-eK5J5_SUcboibLdpMDbyKiobonza5DWeJd63mx8kk5_kzayZsEM$ > This series has already been reviewed and approved, and the corresponding Acked-by and Reviewed-by tags are included. It's just waiting for Greg to pick it up. BR, Thinh
From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
suspend). Reset names use core/ecc. On this SoC ref and suspend are the
same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/usb/altr,agilex5-dwc3.yaml | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
new file mode 100644
index 000000000000..610ddcb632e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Agilex5 DWC3 USB SoC Controller
+
+maintainers:
+ - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
+
+description:
+ The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
+ controller that supports host, device and DRD modes.
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+properties:
+ compatible:
+ const: altr,agilex5-dwc3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Master/Core bus clock
+ - description: Controller reference clock
+ - description: Controller suspend clock
+
+ clock-names:
+ items:
+ - const: bus_early
+ - const: ref
+ - const: suspend
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ minItems: 2
+ maxItems: 2
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ iommus:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: DWC3 core reset
+ - description: DWC3 ECC reset
+
+ reset-names:
+ items:
+ - const: core
+ - const: ecc
+
+ dr_mode: true
+
+ maximum-speed: true
+
+ snps,dis_u2_susphy_quirk: true
+
+ snps,dis_u3_susphy_quirk: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - phys
+ - phy-names
+ - resets
+ - reset-names
+ - snps,dis_u2_susphy_quirk
+ - snps,dis_u3_susphy_quirk
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+ #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usb@11000000 {
+ compatible = "altr,agilex5-dwc3";
+ reg = <0x11000000 0x100000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
+ <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+ <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
+ clock-names = "bus_early", "ref", "suspend";
+ phys = <&usbphy0>, <&usbphy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+ reset-names = "core", "ecc";
+ iommus = <&smmu 7>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
--
2.49.GITFrom: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Add the "altr,agilex5-dwc3" compatible string to dwc3-generic-plat so the
Agilex5 USB3.1 DWC3 controller can probe through the generic DWC3 platform
glue.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
---
drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index ca69ac0eb07c..8781d7ec6b9e 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -232,6 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = {
};
static const struct of_device_id dwc3_generic_of_match[] = {
+ { .compatible = "altr,agilex5-dwc3", },
{ .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
{ .compatible = "spacemit,k3-dwc3", },
{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
--
2.49.GIT© 2016 - 2026 Red Hat, Inc.