On Wed, Apr 08, 2026 at 12:37:05PM +0200, Tommaso Merciai wrote:
> Add DU0, DU1, DSI nodes to RZ/RZG3E SoC DTSI.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> v5->v6:
> - Update ports numbering accordingly to the latest DT bindings.
>
> v4->v5:
> - Rename du0_out_dsi0 into du0_out_dsi.
> - Rename du1_out_dsi0 into du1_out_dsi.
> - Drop renesas,id entry from DU nodes.
>
> v3->v4:
> - No changes.
>
> v2->v3:
> - No changes.
>
> v1->v2:
> - Use single compatible string instead of multiple compatible strings
> for the two DU instances, leveraging a 'renesas,id' property to
> differentiate between DU0 and DU1.
> - Use vclk instead of vclk1 for DSI Node and set to the right position.
>
> arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 120 +++++++++++++++++++++
> 1 file changed, 120 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> index f2fdaadd9d39..25d3a503a6cc 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -1585,6 +1585,126 @@ csi2cru: endpoint@0 {
> };
> };
>
> + dsi: dsi@16430000 {
> + compatible = "renesas,r9a09g047-mipi-dsi";
> + reg = <0 0x16430000 0 0x20000>;
> + interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "seq0", "seq1", "vin1", "rcv",
> + "ferr", "ppi", "debug";
> + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>,
> + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>,
> + <&cpg CPG_MOD 0x190>, <&cpg CPG_MOD 0xeb>;
> + clock-names = "pllrefclk", "aclk", "pclk", "vclk",
> + "lpclk", "vclk2";
> + resets = <&cpg 0xd8>, <&cpg 0xd7>;
> + reset-names = "arst", "prst";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi_in0: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi_in1: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + dsi_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + du0: display@16460000 {
> + compatible = "renesas,r9a09g047-du";
> + reg = <0 0x16460000 0 0x10000>;
> + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 0xed>,
> + <&cpg CPG_MOD 0xee>,
> + <&cpg CPG_MOD 0xef>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg 0xdc>;
I'm a bit concerned here. The same reset line is shared by the FCP, VSP
and DU. The FCP driver doesn't currently control it, but the VSP and DU
both assert and de-assert reset, without any coordination. Does it work
by chance ?
> + renesas,vsps = <&vspd0 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du0_out_dsi: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + du0_out_lvds0: endpoint {
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + du0_out_lvds1: endpoint {
> + };
> + };
> + };
> + };
> +
> + du1: display@16490000 {
> + compatible = "renesas,r9a09g047-du";
> + reg = <0 0x16490000 0 0x10000>;
> + interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 0x1a8>,
> + <&cpg CPG_MOD 0x1a9>,
> + <&cpg CPG_MOD 0x1aa>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg 0x11e>;
> + renesas,vsps = <&vspd1 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du1_out_dsi: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + du1_out_rgb: endpoint {
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + du1_out_lvds1: endpoint {
> + };
> + };
> + };
> + };
> +
> fcpvd0: fcp@16470000 {
> compatible = "renesas,r9a09g047-fcpvd",
> "renesas,fcpv";
--
Regards,
Laurent Pinchart