Future AMD processors will be increasing the number of EILVT registers.
Rather than hardcoding the maximum EILVT register count and using that
everywhere, introduce a variable to track the EILVT register count.

The number of EILVT registers is exposed through the extended APIC
Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the
count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if
the count is not available.

Export the new variable for KVM since it needs this for supporting
extended APIC register space on AMD.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as 
a related series adding support for KVM and needing access to the EILVT 
register count.

- Naveen


 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  1 +
 arch/x86/kernel/apic/apic.c    | 14 ++++++++++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..8b03c7a14706 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -74,6 +74,8 @@ enum apic_intr_mode_id {
 	APIC_SYMMETRIC_IO_NO_ROUTING
 };
 
+extern unsigned int apic_eilvt_count;
+
 /*
  * With 82489DX we can't rely on apic feature bit
  * retrieved via cpuid but still have to deal with
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index bc125c4429dc..ba7657e75ad1 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -134,6 +134,7 @@
 #define		APIC_TDR_DIV_64		0x9
 #define		APIC_TDR_DIV_128	0xA
 #define	APIC_EFEAT	0x400
+#define		APIC_EFEAT_XLC(x)	(((x) >> 16) & 0xff)
 #define	APIC_ECTRL	0x410
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 639904911444..748e09c5b322 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -341,6 +341,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  */
 
 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+unsigned int apic_eilvt_count __ro_after_init;
+EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count);
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
@@ -409,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
 }
 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
 
+static __init void init_eilvt(void)
+{
+	if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
+		apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
+
+	if (!apic_eilvt_count)
+		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+}
+
 /*
  * Program the next event, relative to now
  */
@@ -1644,6 +1655,9 @@ static void setup_local_APIC(void)
 	if (!cpu)
 		cmci_recheck();
 #endif
+
+	if (!apic_eilvt_count)
+		init_eilvt();
 }
 
 static void end_local_APIC_setup(void)
-- 
2.53.0