Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC
with integrated fully differential amplifiers (FDA).
The AD4880 has two independent ADC channels, each with its own SPI
configuration interface. This requires:
- Two entries in reg property for primary and secondary channel chip selects
- Two io-backends entries for the two data channels
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
Changes in v2:
- Replace custom adi,aux-spi-cs property with standard reg property
containing two entries for multi-channel devices
- Add conditional schema validation for reg and io-backends based on
compatible string
- Update example to use reg = <0 1> instead of adi,aux-spi-cs
- Add AD4880 datasheet link
.../bindings/iio/adc/adi,ad4080.yaml | 51 ++++++++++++++++++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
index ccd6a0ac1539..7108a91bb0bf 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
@@ -18,7 +18,11 @@ description: |
service a wide variety of precision, wide bandwidth data acquisition
applications.
+ The AD4880 is a dual-channel variant with two independent ADC channels,
+ each with its own SPI configuration interface.
+
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4880.pdf
$ref: /schemas/spi/spi-peripheral-props.yaml#
@@ -31,9 +35,15 @@ properties:
- adi,ad4084
- adi,ad4086
- adi,ad4087
+ - adi,ad4880
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+ description:
+ SPI chip select(s). For single-channel devices, one chip select.
+ For multi-channel devices like AD4880, two chip selects are required
+ as each channel has its own SPI configuration interface.
spi-max-frequency:
description: Configuration of the SPI bus.
@@ -57,7 +67,8 @@ properties:
vrefin-supply: true
io-backends:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
adi,lvds-cnv-enable:
description: Enable the LVDS signal type on the CNV pin. Default is CMOS.
@@ -78,6 +89,25 @@ required:
- vdd33-supply
- vrefin-supply
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ad4880
+ then:
+ properties:
+ reg:
+ minItems: 2
+ io-backends:
+ minItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
+ io-backends:
+ maxItems: 1
+
additionalProperties: false
examples:
@@ -98,4 +128,21 @@ examples:
io-backends = <&iio_backend>;
};
};
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4880";
+ reg = <0 1>;
+ spi-max-frequency = <10000000>;
+ vdd33-supply = <&vdd33>;
+ vddldo-supply = <&vddldo>;
+ vrefin-supply = <&vrefin>;
+ clocks = <&cnv>;
+ clock-names = "cnv";
+ io-backends = <&iio_backend_cha>, <&iio_backend_chb>;
+ };
+ };
...
--
2.43.0On Fri, Feb 06, 2026 at 06:07:15PM +0200, Antoniu Miclaus wrote:
> Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC
> with integrated fully differential amplifiers (FDA).
>
> The AD4880 has two independent ADC channels, each with its own SPI
> configuration interface. This requires:
> - Two entries in reg property for primary and secondary channel chip selects
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
Please run scripts/checkpatch.pl on the patches and fix reported
warnings.
> - Two io-backends entries for the two data channels
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> Changes in v2:
> - Replace custom adi,aux-spi-cs property with standard reg property
> containing two entries for multi-channel devices
> - Add conditional schema validation for reg and io-backends based on
> compatible string
> - Update example to use reg = <0 1> instead of adi,aux-spi-cs
> - Add AD4880 datasheet link
>
> .../bindings/iio/adc/adi,ad4080.yaml | 51 ++++++++++++++++++-
> 1 file changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> index ccd6a0ac1539..7108a91bb0bf 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
> @@ -18,7 +18,11 @@ description: |
> service a wide variety of precision, wide bandwidth data acquisition
> applications.
>
> + The AD4880 is a dual-channel variant with two independent ADC channels,
> + each with its own SPI configuration interface.
> +
> https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf
> + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4880.pdf
>
> $ref: /schemas/spi/spi-peripheral-props.yaml#
>
> @@ -31,9 +35,15 @@ properties:
> - adi,ad4084
> - adi,ad4086
> - adi,ad4087
> + - adi,ad4880
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> + description:
> + SPI chip select(s). For single-channel devices, one chip select.
> + For multi-channel devices like AD4880, two chip selects are required
> + as each channel has its own SPI configuration interface.
>
> spi-max-frequency:
> description: Configuration of the SPI bus.
> @@ -57,7 +67,8 @@ properties:
> vrefin-supply: true
>
> io-backends:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
Instead list the items with minItems, so the order is defined.
>
> adi,lvds-cnv-enable:
> description: Enable the LVDS signal type on the CNV pin. Default is CMOS.
> @@ -78,6 +89,25 @@ required:
> - vdd33-supply
> - vrefin-supply
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: adi,ad4880
> + then:
> + properties:
> + reg:
> + minItems: 2
> + io-backends:
> + minItems: 2
> + else:
> + properties:
> + reg:
> + maxItems: 1
> + io-backends:
> + maxItems: 1
> +
> additionalProperties: false
>
> examples:
> @@ -98,4 +128,21 @@ examples:
> io-backends = <&iio_backend>;
> };
> };
> + - |
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + adc@0 {
> + compatible = "adi,ad4880";
> + reg = <0 1>;
<0>, <1>, no? You want two separate chip selects, right? (size-cells is
0).
Best regards,
Krzysztof
On Sat, 2026-02-07 at 11:41 +0100, Krzysztof Kozlowski wrote: > On Fri, Feb 06, 2026 at 06:07:15PM +0200, Antoniu Miclaus wrote: > > Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC > > with integrated fully differential amplifiers (FDA). > > > > The AD4880 has two independent ADC channels, each with its own SPI > > configuration interface. This requires: > > - Two entries in reg property for primary and secondary channel chip selects > > Please wrap commit message according to Linux coding style / submission > process (neither too early nor over the limit): > https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 > > Please run scripts/checkpatch.pl on the patches and fix reported > warnings. > > > - Two io-backends entries for the two data channels > > > > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> > > --- > > Changes in v2: > > - Replace custom adi,aux-spi-cs property with standard reg property > > containing two entries for multi-channel devices > > - Add conditional schema validation for reg and io-backends based on > > compatible string > > - Update example to use reg = <0 1> instead of adi,aux-spi-cs > > - Add AD4880 datasheet link > > > > .../bindings/iio/adc/adi,ad4080.yaml | 51 ++++++++++++++++++- > > 1 file changed, 49 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > index ccd6a0ac1539..7108a91bb0bf 100644 > > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml > > @@ -18,7 +18,11 @@ description: | > > service a wide variety of precision, wide bandwidth data acquisition > > applications. > > > > + The AD4880 is a dual-channel variant with two independent ADC channels, > > + each with its own SPI configuration interface. > > + > > https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf > > + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4880.pdf > > > > $ref: /schemas/spi/spi-peripheral-props.yaml# > > > > @@ -31,9 +35,15 @@ properties: > > - adi,ad4084 > > - adi,ad4086 > > - adi,ad4087 > > + - adi,ad4880 > > > > reg: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > + description: > > + SPI chip select(s). For single-channel devices, one chip select. > > + For multi-channel devices like AD4880, two chip selects are required > > + as each channel has its own SPI configuration interface. > > > > spi-max-frequency: > > description: Configuration of the SPI bus. > > @@ -57,7 +67,8 @@ properties: > > vrefin-supply: true > > > > io-backends: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > Instead list the items with minItems, so the order is defined. > Also looks like we now need 'io-backend-names'. - Nuno Sá > >
On 08/02/2026 10:16, Nuno Sá wrote: >>> >>> io-backends: >>> - maxItems: 1 >>> + minItems: 1 >>> + maxItems: 2 >> >> Instead list the items with minItems, so the order is defined. >> > > Also looks like we now need 'io-backend-names'. No. Just define the order here. Best regards, Krzysztof
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