From: Biju Das <biju.das.jz@bp.renesas.com>
Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 231b118ecc62..c6b042ac9c36 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -181,9 +181,19 @@ sysc: system-controller@11020000 {
};
pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a08g046-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 232>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G046_GPIO_RSTN>,
+ <&cpg R9A08G046_GPIO_PORT_RESETN>,
+ <&cpg R9A08G046_GPIO_SPARE_RESETN>;
+ reset-names = "rstn", "port", "spare";
};
dmac: dma-controller@11820000 {
--
2.43.0