This series introduces support for Agilex5 SoC in the Synopsys DesignWare
AXI DMA binding and updates the device tree to use the platform-specific
compatible string.

The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
this specific addition will enable driver to handle this limitation.

---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.20

Changes in v5:
	- Drop driver changes since Rob's comment that the core will merge the
          device's mask with the bus ranges.

Changes in v4:
	- Use common code to get dma ranges.
	- Simplify the code to only in hw_init that will set the bit mask.

Changes in v3:
	- simplify dma-ranges addition without description as per input
	  from Rob.
	- Add simple-bus to with address-cells, size-cells, dma-ranges
	  added under this bus-node.
	- Move dma controller device node under simple-bus node.
	- Rename "arm64: dts: intel: agilex5: Add dma-ranges, address and size
	  cells to dma node" to #2
	- Drop "dt-bindings: dma: snps,dw-axi-dmac: Add #address-cells and
	  #size-cells"
	- Refactor "dma: dw-axi-dmac: Add support for Agilex5 and dynamic bus
	  width" to align with dma controller node now under simple-bus node.

Changes in v2:
	- Add dma-ranges property.
	- Add address-cells and size-cells due to warning when dma-ranges
	  is define without address-cells and size-cells present. Also
	  prevent kernel panic if address-cells and size-cells are not
	  defined.
	- Add driver support to handle defined properties and set the DMA
	  BIT MASK according to value from DT.
	- Rename "arm64: dts: agilex5: Use platform-specific compatible for
          AXI DMA" to "arm64: dts: intel: agilex5: Add dma-ranges and
          address cells to dma node"

This changes is validated on:
	- intel/socfpga_agilex5_socdk.dtb
	- snps,dw-axi-dmac.yaml
	- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb
	- Agilex5 devkit
---
Khairul Anuar Romli (2):
  dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma
    controller node

 .../bindings/dma/snps,dw-axi-dmac.yaml        | 14 ++--
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
 2 files changed, 52 insertions(+), 40 deletions(-)

-- 
2.43.7

On Mon, 29 Dec 2025 11:49:00 +0800, Khairul Anuar Romli wrote:
> This series introduces support for Agilex5 SoC in the Synopsys DesignWare
> AXI DMA binding and updates the device tree to use the platform-specific
> compatible string.
> 
> The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
> this specific addition will enable driver to handle this limitation.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
      commit: 0a6946644f0d1151d31212820497e1a49fe1a0a6

Best regards,
-- 
~Vinod

On 2/1/2026 1:41 am, Vinod Koul wrote:
> 
> On Mon, 29 Dec 2025 11:49:00 +0800, Khairul Anuar Romli wrote:
>> This series introduces support for Agilex5 SoC in the Synopsys DesignWare
>> AXI DMA binding and updates the device tree to use the platform-specific
>> compatible string.
>>
>> The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
>> this specific addition will enable driver to handle this limitation.
>>
>> [...]
> 
> Applied, thanks!
> 
> [1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
>        commit: 0a6946644f0d1151d31212820497e1a49fe1a0a6
> 
> Best regards,

Thank you so much for getting this patch series reviewed and accepted.

Regards,
Khairul