Convert binding for ti,omap3isp from TXT to YAML format.
Signed-off-by: Alex Tran <alex.t.tran@gmail.com>
---
.../devicetree/bindings/media/ti,omap3isp.txt | 71 -------
.../bindings/media/ti,omap3isp.yaml | 182 ++++++++++++++++++
2 files changed, 182 insertions(+), 71 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/media/ti,omap3isp.txt
create mode 100644 Documentation/devicetree/bindings/media/ti,omap3isp.yaml
diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt
deleted file mode 100644
index ac23de855641..000000000000
--- a/Documentation/devicetree/bindings/media/ti,omap3isp.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-OMAP 3 ISP Device Tree bindings
-===============================
-
-The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
-
-Required properties
-===================
-
-compatible : must contain "ti,omap3-isp"
-
-reg : the two registers sets (physical address and length) for the
- ISP. The first set contains the core ISP registers up to
- the end of the SBL block. The second set contains the
- CSI PHYs and receivers registers.
-interrupts : the ISP interrupt specifier
-iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP
-syscon : the phandle and register offset to the Complex I/O or CSI-PHY
- register
-ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
- 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
-#clock-cells : Must be 1 --- the ISP provides two external clocks,
- cam_xclka and cam_xclkb, at indices 0 and 1,
- respectively. Please find more information on common
- clock bindings in ../clock/clock-bindings.txt.
-
-Port nodes (optional)
----------------------
-
-More documentation on these bindings is available in
-video-interfaces.txt in the same directory.
-
-reg : The interface:
- 0 - parallel (CCDC)
- 1 - CSIPHY1 -- CSI2C / CCP2B on 3630;
- CSI1 -- CSIb on 3430
- 2 - CSIPHY2 -- CSI2A / CCP2B on 3630;
- CSI2 -- CSIa on 3430
-
-Optional properties
-===================
-
-vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
-vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
-
-Endpoint nodes
---------------
-
-lane-polarities : lane polarity (required on CSI-2)
- 0 -- not inverted; 1 -- inverted
-data-lanes : an array of data lanes from 1 to 3. The length can
- be either 1 or 2. (required on CSI-2)
-clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
-
-
-Example
-=======
-
- isp@480bc000 {
- compatible = "ti,omap3-isp";
- reg = <0x480bc000 0x12fc
- 0x480bd800 0x0600>;
- interrupts = <24>;
- iommus = <&mmu_isp>;
- syscon = <&scm_conf 0x2f0>;
- ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
- #clock-cells = <1>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.yaml b/Documentation/devicetree/bindings/media/ti,omap3isp.yaml
new file mode 100644
index 000000000000..3f3b0c0f46e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti,omap3isp.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/ti,omap3isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OMAP 3 Image Signal Processor (ISP)
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ - Sakari Ailus <sakari.ailus@iki.fi>
+
+description:
+ The OMAP 3 ISP is an image signal processor present in OMAP 3 SoCs.
+
+properties:
+ compatible:
+ const: ti,omap3-isp
+
+ reg:
+ items:
+ - description: Core ISP registers up to the end of the SBL block
+ - description: CSI PHYs and receivers registers
+
+ interrupts:
+ maxItems: 1
+ description: the ISP interrupt specifier
+
+ iommus:
+ maxItems: 1
+ description: phandle and IOMMU specifier for the IOMMU that serves the ISP
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Control Module
+ - description: register offset to Complex I/O or CSI-PHY register
+ description:
+ Phandle and register offset to the Complex I/O or CSI-PHY register
+
+ ti,phy-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ 0 - OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. OMAP 3430)
+ 1 - OMAP3ISP_PHY_TYPE_CSIPHY (e.g. OMAP 3630)
+
+ '#clock-cells':
+ const: 1
+ description:
+ The ISP provides two external clocks, cam_xclka and cam_xclkb,
+ at indices 0 and 1 respectively.
+
+ vdd-csiphy1-supply:
+ description: Voltage supply of the CSI-2 PHY 1
+
+ vdd-csiphy2-supply:
+ description: Voltage supply of the CSI-2 PHY 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Parallel (CCDC) interface
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: |
+ CSIPHY1 interface:
+ OMAP 3630: CSI2C / CCP2B
+ OMAP 3430: CSI1 (CSIb)
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ lane-polarities:
+ description: |
+ The lane polarity (required on CSI-2):
+ 0 - not inverted
+ 1 - inverted
+ minItems: 2
+ maxItems: 3
+ items:
+ enum: [0, 1]
+
+ data-lanes:
+ description: Data lanes (required on CSI-2)
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 1
+ maximum: 3
+
+ clock-lanes:
+ description: The clock lane (required on CSI-2)
+ maxItems: 1
+ items:
+ minimum: 1
+ maximum: 3
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: |
+ CSIPHY2 interface:
+ OMAP 3630: CSI2A / CCP2B
+ OMAP 3430: CSI2 (CSIa)
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ lane-polarities:
+ description: |
+ The lane polarity (required on CSI-2):
+ 0 - not inverted
+ 1 - inverted
+ minItems: 2
+ maxItems: 3
+ items:
+ enum: [0, 1]
+
+ data-lanes:
+ description: Data lanes (required on CSI-2)
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 1
+ maximum: 3
+
+ clock-lanes:
+ description: The clock lane (required on CSI-2)
+ maxItems: 1
+ items:
+ minimum: 1
+ maximum: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - iommus
+ - syscon
+ - ti,phy-type
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/media/omap3-isp.h>
+
+ isp@480bc000 {
+ compatible = "ti,omap3-isp";
+ reg = <0x480bc000 0x12fc>,
+ <0x480bd800 0x0600>;
+ interrupts = <24>;
+ iommus = <&mmu_isp>;
+ syscon = <&scm_conf 0x2f0>;
+ ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
--
2.51.0On Sat, Dec 20, 2025 at 02:03:25PM -0800, Alex Tran wrote:
Thank you for your patch. There is something to discuss/improve.
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + - Sakari Ailus <sakari.ailus@iki.fi>
> +
> +description:
> + The OMAP 3 ISP is an image signal processor present in OMAP 3 SoCs.
> +
> +properties:
> + compatible:
> + const: ti,omap3-isp
> +
> + reg:
> + items:
> + - description: Core ISP registers up to the end of the SBL block
> + - description: CSI PHYs and receivers registers
> +
> + interrupts:
> + maxItems: 1
> + description: the ISP interrupt specifier
Drop description, obvious.
> +
> + iommus:
> + maxItems: 1
> + description: phandle and IOMMU specifier for the IOMMU that serves the ISP
Ditto
> +
> + syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to System Control Module
> + - description: register offset to Complex I/O or CSI-PHY register
> + description:
> + Phandle and register offset to the Complex I/O or CSI-PHY register
> +
> + ti,phy-type:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
> + description:
> + 0 - OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. OMAP 3430)
> + 1 - OMAP3ISP_PHY_TYPE_CSIPHY (e.g. OMAP 3630)
> +
> + '#clock-cells':
> + const: 1
> + description:
> + The ISP provides two external clocks, cam_xclka and cam_xclkb,
> + at indices 0 and 1 respectively.
> +
> + vdd-csiphy1-supply:
> + description: Voltage supply of the CSI-2 PHY 1
> +
> + vdd-csiphy2-supply:
> + description: Voltage supply of the CSI-2 PHY 2
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Parallel (CCDC) interface
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: |
> + CSIPHY1 interface:
> + OMAP 3630: CSI2C / CCP2B
> + OMAP 3430: CSI1 (CSIb)
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + lane-polarities:
> + description: |
> + The lane polarity (required on CSI-2):
> + 0 - not inverted
> + 1 - inverted
You do not need to describe standard properties. Are the values
different than what video-interfaces define?
Same everywhere else. Look at other bindings how these properties should
be defined/written.
> + minItems: 2
> + maxItems: 3
> + items:
> + enum: [0, 1]
> +
> + data-lanes:
> + description: Data lanes (required on CSI-2)
> + minItems: 1
> + maxItems: 2
> + items:
> + minimum: 1
> + maximum: 3
> +
> + clock-lanes:
> + description: The clock lane (required on CSI-2)
> + maxItems: 1
> + items:
> + minimum: 1
> + maximum: 3
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: |
> + CSIPHY2 interface:
> + OMAP 3630: CSI2A / CCP2B
> + OMAP 3430: CSI2 (CSIa)
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + lane-polarities:
> + description: |
> + The lane polarity (required on CSI-2):
> + 0 - not inverted
> + 1 - inverted
> + minItems: 2
> + maxItems: 3
> + items:
> + enum: [0, 1]
> +
> + data-lanes:
> + description: Data lanes (required on CSI-2)
> + minItems: 1
> + maxItems: 2
> + items:
> + minimum: 1
> + maximum: 3
> +
> + clock-lanes:
> + description: The clock lane (required on CSI-2)
> + maxItems: 1
> + items:
> + minimum: 1
> + maximum: 3
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - iommus
> + - syscon
> + - ti,phy-type
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/media/omap3-isp.h>
> +
> + isp@480bc000 {
> + compatible = "ti,omap3-isp";
> + reg = <0x480bc000 0x12fc>,
> + <0x480bd800 0x0600>;
> + interrupts = <24>;
> + iommus = <&mmu_isp>;
> + syscon = <&scm_conf 0x2f0>;
> + ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
> + #clock-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
Make example complete, please.
Best regards,
Krzysztof
On Sun, Dec 21, 2025 at 7:08 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Sat, Dec 20, 2025 at 02:03:25PM -0800, Alex Tran wrote:
>
>
> Thank you for your patch. There is something to discuss/improve.
>
>
> > +maintainers:
> > + - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > + - Sakari Ailus <sakari.ailus@iki.fi>
> > +
> > +description:
> > + The OMAP 3 ISP is an image signal processor present in OMAP 3 SoCs.
> > +
> > +properties:
> > + compatible:
> > + const: ti,omap3-isp
> > +
> > + reg:
> > + items:
> > + - description: Core ISP registers up to the end of the SBL block
> > + - description: CSI PHYs and receivers registers
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: the ISP interrupt specifier
>
> Drop description, obvious.
>
> > +
> > + iommus:
> > + maxItems: 1
> > + description: phandle and IOMMU specifier for the IOMMU that serves the ISP
>
> Ditto
>
> > +
> > + syscon:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + - items:
> > + - description: phandle to System Control Module
> > + - description: register offset to Complex I/O or CSI-PHY register
> > + description:
> > + Phandle and register offset to the Complex I/O or CSI-PHY register
> > +
> > + ti,phy-type:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1]
> > + description:
> > + 0 - OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. OMAP 3430)
> > + 1 - OMAP3ISP_PHY_TYPE_CSIPHY (e.g. OMAP 3630)
> > +
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + The ISP provides two external clocks, cam_xclka and cam_xclkb,
> > + at indices 0 and 1 respectively.
> > +
> > + vdd-csiphy1-supply:
> > + description: Voltage supply of the CSI-2 PHY 1
> > +
> > + vdd-csiphy2-supply:
> > + description: Voltage supply of the CSI-2 PHY 2
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: Parallel (CCDC) interface
> > +
> > + properties:
> > + endpoint:
> > + $ref: /schemas/media/video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: |
> > + CSIPHY1 interface:
> > + OMAP 3630: CSI2C / CCP2B
> > + OMAP 3430: CSI1 (CSIb)
> > +
> > + properties:
> > + endpoint:
> > + $ref: /schemas/media/video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + lane-polarities:
> > + description: |
> > + The lane polarity (required on CSI-2):
> > + 0 - not inverted
> > + 1 - inverted
>
> You do not need to describe standard properties. Are the values
> different than what video-interfaces define?
>
> Same everywhere else. Look at other bindings how these properties should
> be defined/written.
>
> > + minItems: 2
> > + maxItems: 3
> > + items:
> > + enum: [0, 1]
> > +
> > + data-lanes:
> > + description: Data lanes (required on CSI-2)
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + minimum: 1
> > + maximum: 3
> > +
> > + clock-lanes:
> > + description: The clock lane (required on CSI-2)
> > + maxItems: 1
> > + items:
> > + minimum: 1
> > + maximum: 3
> > +
> > + port@2:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: |
> > + CSIPHY2 interface:
> > + OMAP 3630: CSI2A / CCP2B
> > + OMAP 3430: CSI2 (CSIa)
> > +
> > + properties:
> > + endpoint:
> > + $ref: /schemas/media/video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + lane-polarities:
> > + description: |
> > + The lane polarity (required on CSI-2):
> > + 0 - not inverted
> > + 1 - inverted
> > + minItems: 2
> > + maxItems: 3
> > + items:
> > + enum: [0, 1]
> > +
> > + data-lanes:
> > + description: Data lanes (required on CSI-2)
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + minimum: 1
> > + maximum: 3
> > +
> > + clock-lanes:
> > + description: The clock lane (required on CSI-2)
> > + maxItems: 1
> > + items:
> > + minimum: 1
> > + maximum: 3
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - iommus
> > + - syscon
> > + - ti,phy-type
> > + - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/media/omap3-isp.h>
> > +
> > + isp@480bc000 {
> > + compatible = "ti,omap3-isp";
> > + reg = <0x480bc000 0x12fc>,
> > + <0x480bd800 0x0600>;
> > + interrupts = <24>;
> > + iommus = <&mmu_isp>;
> > + syscon = <&scm_conf 0x2f0>;
> > + ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
> > + #clock-cells = <1>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Make example complete, please.
>
>
> Best regards,
> Krzysztof
>
Thanks for the review. I'll address these in v2. Also the check patch
script seems to be giving false positive warnings about DT binding
docs and includes should be a separate patch. This patch series does
not touch any files under the include/dt-bindings directory at all.
--
Yours,
Alex Tran
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