[PATCH 1/4] dt-bindings: misc: agilex5-soc-fcs-config: Add binding

hangsuan.wang@altera.com posted 4 patches 1 day, 19 hours ago
[PATCH 1/4] dt-bindings: misc: agilex5-soc-fcs-config: Add binding
Posted by hangsuan.wang@altera.com 1 day, 19 hours ago
From: "Wang, Hang Suan" <hangsuan.wang@altera.com>

Soc/Hardware FPGA crypto services (fcs) by ensuring optimal performance,
secure isolation, and robust system management. This will allow dedicated
system resources to communicate with the high-speed FPGA hardware without
interruption or software overhead.

This results in faster, more secure, and consistent cryptographic
operations compared to running the services entirely on the
general-purpose CPU.

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
---
---
 .../misc/intel,agilex5-soc-fcs-config.yaml    | 32 +++++++++++++++++++
 MAINTAINERS                                   |  5 +++
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml

diff --git a/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml b/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
new file mode 100644
index 000000000000..10cd793f8fc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,agilex5-soc-fcs-config.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SoC FPGA Crypto Service features
+
+maintainers:
+  - Wang Hang Suan <hangsuan.wang@altera.com>
+  - Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
+  - Sagar Khadgi <sagar.khadgi@altera.com>
+  - Santosh Male <santosh.male@altera.com>
+  - Mahesh Rao <mahesh.rao@altera.com>
+
+properties:
+  compatible:
+    enum:
+      - intel,agilex5-soc-fcs-config
+      - intel,agilex-soc-fcs-config
+
+additionalProperties: false
+
+required:
+  - compatible
+
+examples:
+  - |
+    fcs_config: fcs-config {
+      compatible = "intel,agilex5-soc-fcs-config";
+    };
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 46126ce2f968..2208d611f73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -923,6 +923,11 @@ ALPS PS/2 TOUCHPAD DRIVER
 R:	Pali Rohár <pali@kernel.org>
 F:	drivers/input/mouse/alps.*
 
+ALTERA FPGA CRYPTO SERVICE DRIVER
+M:	Hang Suan Wang <hangsuan.wang@altera.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
+
 ALTERA MAILBOX DRIVER
 M:	Tien Sung Ang <tiensung.ang@altera.com>
 S:	Maintained
-- 
2.43.7

Re: [PATCH 1/4] dt-bindings: misc: agilex5-soc-fcs-config: Add binding
Posted by Krzysztof Kozlowski 1 day, 3 hours ago
On 12/12/2025 12:35, hangsuan.wang@altera.com wrote:
> From: "Wang, Hang Suan" <hangsuan.wang@altera.com>
> 
> Soc/Hardware FPGA crypto services (fcs) by ensuring optimal performance,
> secure isolation, and robust system management. This will allow dedicated
> system resources to communicate with the high-speed FPGA hardware without
> interruption or software overhead.
> 
> This results in faster, more secure, and consistent cryptographic
> operations compared to running the services entirely on the
> general-purpose CPU.
> 

You don't have resources there, so that's not a real device... And above
explanation does not help me at all. Please carefully read slides for
DTS 101 talk and writing bindings doc.

Best regards,
Krzysztof