Enable control of USB2.0 VBUSEN via the VBUS_SEL bit in the VBENCTL
register. According to the RZ/V2H(P) SoC hardware manual, OTG channels
require VBUS_SEL set, while HOST-only channels require it cleared.
Add `#mux-state-cell` to the usb20phyrst and usb21phyrst reset
nodes to expose them as mux controllers.
Set the required mux-states in usb2_phy0 (OTG: state 1) and usb2_phy1
(HOST: state 0) nodes.
This enables proper VBUSEN management for OTG and HOST-only USB2.0
channels.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v4->v5:
- No changes.
v3->v4:
- Switch back to v2 implementation.
- Improve commit body.
v2->v3:
- Manipulate the mux controller as an internal node, and update
commit body accordingly.
v1->v2:
- New patch
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 4df32d7e9998..b4bbcde33099 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1034,6 +1034,7 @@ usb2_phy0: usb-phy@15800200 {
resets = <&usb20phyrst>;
#phy-cells = <1>;
power-domains = <&cpg>;
+ mux-states = <&usb20phyrst 1>;
status = "disabled";
};
@@ -1047,6 +1048,7 @@ usb2_phy1: usb-phy@15810200 {
resets = <&usb21phyrst>;
#phy-cells = <1>;
power-domains = <&cpg>;
+ mux-states = <&usb21phyrst 0>;
status = "disabled";
};
@@ -1074,6 +1076,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
@@ -1084,6 +1087,7 @@ usb21phyrst: usb21phy-reset@15840000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
--
2.43.0