The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
Processor (VSPD), and Display Unit (DU).
- LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
- LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
and 'renesas,r9a09g047-du1'.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
.../bindings/display/renesas,rzg2l-du.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 2cc66dcef870..a68252ae02fb 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -20,6 +20,8 @@ properties:
- enum:
- renesas,r9a07g043u-du # RZ/G2UL
- renesas,r9a07g044-du # RZ/G2{L,LC}
+ - renesas,r9a09g047-du0 # RZ/G3E DU0
+ - renesas,r9a09g047-du1 # RZ/G3E DU1
- renesas,r9a09g057-du # RZ/V2H(P)
- items:
- enum:
@@ -137,6 +139,46 @@ allOf:
required:
- port@0
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-du0
+ then:
+ properties:
+ ports:
+ properties:
+ port@0:
+ description: DSI
+ port@1:
+ description: LVDS
+ port@2:
+ description: LVDS
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-du1
+ then:
+ properties:
+ ports:
+ properties:
+ port@0:
+ description: DSI
+ port@1:
+ description: LVDS
+ port@2:
+ description: DPAD
+
+ required:
+ - port@0
+ - port@1
+ - port@2
examples:
# RZ/G2L DU
--
2.43.0