[v1] Add support for DU and DSI on the Renesas RZ/G3E SoC

[PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

Posted by Tommaso Merciai 2 months, 2 weeks ago

The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
Processor (VSPD), and Display Unit (DU).

 - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
 - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.

Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
and 'renesas,r9a09g047-du1'.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 .../bindings/display/renesas,rzg2l-du.yaml    | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 2cc66dcef870..a68252ae02fb 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -20,6 +20,8 @@ properties:
       - enum:
           - renesas,r9a07g043u-du # RZ/G2UL
           - renesas,r9a07g044-du # RZ/G2{L,LC}
+          - renesas,r9a09g047-du0 # RZ/G3E DU0
+          - renesas,r9a09g047-du1 # RZ/G3E DU1
           - renesas,r9a09g057-du # RZ/V2H(P)
       - items:
           - enum:
@@ -137,6 +139,46 @@ allOf:
 
           required:
             - port@0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-du0
+    then:
+      properties:
+        ports:
+          properties:
+            port@0:
+              description: DSI
+            port@1:
+              description: LVDS
+            port@2:
+              description: LVDS
+
+          required:
+            - port@0
+            - port@1
+            - port@2
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-du1
+    then:
+      properties:
+        ports:
+          properties:
+            port@0:
+              description: DSI
+            port@1:
+              description: LVDS
+            port@2:
+              description: DPAD
+
+          required:
+            - port@0
+            - port@1
+            - port@2
 
 examples:
   # RZ/G2L DU
-- 
2.43.0

Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

Posted by Tommaso Merciai 1 month ago

Hi Krystoff, Laurent, Geert,

On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> Processor (VSPD), and Display Unit (DU).
> 
>  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
>  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> 
> Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> and 'renesas,r9a09g047-du1'.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  .../bindings/display/renesas,rzg2l-du.yaml    | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> index 2cc66dcef870..a68252ae02fb 100644
> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -20,6 +20,8 @@ properties:
>        - enum:
>            - renesas,r9a07g043u-du # RZ/G2UL
>            - renesas,r9a07g044-du # RZ/G2{L,LC}
> +          - renesas,r9a09g047-du0 # RZ/G3E DU0
> +          - renesas,r9a09g047-du1 # RZ/G3E DU1
>            - renesas,r9a09g057-du # RZ/V2H(P)
>        - items:
>            - enum:
> @@ -137,6 +139,46 @@ allOf:
>  
>            required:
>              - port@0
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g047-du0
> +    then:
> +      properties:
> +        ports:
> +          properties:
> +            port@0:
> +              description: DSI
> +            port@1:
> +              description: LVDS
> +            port@2:
> +              description: LVDS
> +
> +          required:
> +            - port@0
> +            - port@1
> +            - port@2
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g047-du1
> +    then:
> +      properties:
> +        ports:
> +          properties:
> +            port@0:
> +              description: DSI
> +            port@1:
> +              description: LVDS
> +            port@2:
> +              description: DPAD
> +
> +          required:
> +            - port@0
> +            - port@1
> +            - port@2
>  
>  examples:
>    # RZ/G2L DU
> -- 
> 2.43.0
> 

What is your opinion on this patch?
I posted some more HW details on [0]

Thanks & Regards,
Tommaso

[0] https://patchwork.kernel.org/comment/26686746/

Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

Posted by Krzysztof Kozlowski 2 months, 1 week ago

On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> Processor (VSPD), and Display Unit (DU).
> 
>  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
>  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> 
> Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> and 'renesas,r9a09g047-du1'.

LCDC0/1 but compatibles du0/du1...

What are the differences between DU0 and DU1? Just different outputs? Is
the programming model the same?

Best regards,
Krzysztof

Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

Posted by Tommaso Merciai 2 months, 1 week ago

Hi Krzysztof,
Thanks for your review!

On Wed, Dec 03, 2025 at 09:23:53AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > Processor (VSPD), and Display Unit (DU).
> > 
> >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > 
> > Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> > and 'renesas,r9a09g047-du1'.
> 
> LCDC0/1 but compatibles du0/du1...
> 
> What are the differences between DU0 and DU1? Just different outputs? Is
> the programming model the same?

The hardware configurations are different: these are two distinct hardware blocks.

Based on the block diagrams shown in Figures 9.4-2 (LCDC1) and 9.4-1 (LCDC0),
the only difference concerns the output, but this variation is internal to the
hardware blocks themselves.
Therefore, LCDC0 and LCDC1 are not identical blocks, and their programming models
differ as a result.

In summary, although most of the internal functions are the same, the two blocks
have output signals connected to different components within the SoC.
This requires different hardware configurations and inevitably leads to different
programming models for LCDC0 and LCDC1.

Kind Regards,
Tommaso

> 
> Best regards,
> Krzysztof
>

Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

Posted by Geert Uytterhoeven 3 weeks, 5 days ago

Hi Tommaso,

On Wed, 3 Dec 2025 at 14:42, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Dec 03, 2025 at 09:23:53AM +0100, Krzysztof Kozlowski wrote:
> > On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > Processor (VSPD), and Display Unit (DU).
> > >
> > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > >
> > > Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> > > and 'renesas,r9a09g047-du1'.
> >
> > LCDC0/1 but compatibles du0/du1...
> >
> > What are the differences between DU0 and DU1? Just different outputs? Is
> > the programming model the same?
>
> The hardware configurations are different: these are two distinct hardware blocks.
>
> Based on the block diagrams shown in Figures 9.4-2 (LCDC1) and 9.4-1 (LCDC0),
> the only difference concerns the output, but this variation is internal to the
> hardware blocks themselves.
> Therefore, LCDC0 and LCDC1 are not identical blocks, and their programming models
> differ as a result.
>
> In summary, although most of the internal functions are the same, the two blocks
> have output signals connected to different components within the SoC.
> This requires different hardware configurations and inevitably leads to different
> programming models for LCDC0 and LCDC1.

Isn't that merely an SoC integration issue?
Are there any differences in programming LCDC0 or LCDC1 for the
common output types supported by both (single channel LVDS and 4-lane
MIPI-DSI)?

Of there are no such differences, both instances should use the same
compatible value.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds