The Cadence HP NAND Flash Controller on Agilex5 device performs DMA
transactions through a coherent interconnect. dma-coherent property
presents in device tree will allow the kernel’s DMA subsystem
controller’s to performs DMA transaction in dma coherent mode.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index 73dc69cee4d8..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,8 @@ properties:
   dmas:
     maxItems: 1
 
+  dma-coherent: true
+
   iommus:
     maxItems: 1
 
-- 
2.43.7

On Wed, Nov 26, 2025 at 04:06:22PM +0800, Khairul Anuar Romli wrote:
> The Cadence HP NAND Flash Controller on Agilex5 device performs DMA
> transactions through a coherent interconnect. dma-coherent property
> presents in device tree will allow the kernel’s DMA subsystem
> controller’s to performs DMA transaction in dma coherent mode.

Last sentence is redundant. You say basically "dma-coherent means
dma coherent". Write informative commit msgs, so something which is not
obvious, e.g. why this is dma coherent NOW but wasn't before?

Best regards,
Krzysztof