[PATCH v6 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

Khairul Anuar Romli posted 2 patches 1 week, 6 days ago
[PATCH v6 1/2] dt-bindings: fpga: stratix10: add support for Agilex5
Posted by Khairul Anuar Romli 1 week, 6 days ago
Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. Agilex5 compatible allows stratix10-
FPGA manager driver to handle these changes.

Fallback is added for driver probe and init that rely on matching of table
and DT node.

Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v6:
	- Use items - const for Agilex5 to support fallback.
	- Validate bindings with dt-schema by itself and against fallback
	  and non-fallback.
Changes in v5:
	- Revert to oneOf and use enum without items.
Changes in v4:
	- Remove redundant "items - enum" as suggested in v3.
	- Simplify compatible property to use contains instead of oneOf.
	- Validate fallback and non-fallback DT. Also validate binding with
          dt_binding_check.
Changes in v3:
	- Add description for Agilex5 Device
	- Add and define fallback to "intel,agilex-soc-fpga-mgr"
	- Validate against Agilex and Stratix10 (non-fallback) and Agilex5
	  (fallback)
Changes in v2:
	- No changes in this patch
---
 .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml    | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
index 6e536d6b28a9..fff88c8e5e03 100644
--- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
+++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
@@ -20,9 +20,13 @@ description:
 
 properties:
   compatible:
-    enum:
-      - intel,stratix10-soc-fpga-mgr
-      - intel,agilex-soc-fpga-mgr
+    oneOf:
+      - enum:
+          - intel,stratix10-soc-fpga-mgr
+          - intel,agilex-soc-fpga-mgr
+      - items:
+          - const: intel,agilex5-soc-fpga-mgr
+          - const: intel,agilex-soc-fpga-mgr
 
 required:
   - compatible
-- 
2.43.7
Re: [PATCH v6 1/2] dt-bindings: fpga: stratix10: add support for Agilex5
Posted by Conor Dooley 1 week, 5 days ago
On Wed, Nov 19, 2025 at 10:26:05AM +0800, Khairul Anuar Romli wrote:
> Agilex5 introduces changes in how reserved memory is mapped and accessed
> compared to previous SoC generations. Agilex5 compatible allows stratix10-
> FPGA manager driver to handle these changes.
> 
> Fallback is added for driver probe and init that rely on matching of table
> and DT node.
> 
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>


Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable