Add a device tree overlay to enable support for the NXP P3T1085UK-ARD
board when connected to the RZ/G3E SMARC SoM via the RZ SMARC BREAKOUT
board.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  3 +
 .../r9a09g047e57-smarc-p3t1085uk-ard.dtso     | 83 +++++++++++++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 1fab1b50f20e..9e5b22343071 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -185,6 +185,9 @@ dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtbo
 r9a09g047e57-smarc-cru-csi-ov5645-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-cru-csi-ov5645.dtbo
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-p3t1085uk-ard.dtbo
+r9a09g047e57-smarc-p3t1085uk-ard-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-p3t1085uk-ard.dtbo
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-p3t1085uk-ard.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G056) += rzv2-evk-cn15-emmc.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso
new file mode 100644
index 000000000000..fcbdccc942a8
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-p3t1085uk-ard.dtso
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree overlay for the NXP P3T1085UK-ARD board connected
+ * to the R9A09G047E57 SMARC SoM board via the RZ SMARC BREAKOUT board.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ *
+ * [Connections]
+ *
+ * RZ SMARC Carrier II (CN1)  →  RZ SMARC BREAKOUT board
+ *
+ * RZ SMARC Carrier II (PMOD1_6)  →  P3T1085UK-ARD (J9)
+ * +--------------------------------------------------------+
+ * |    PWR_PMOD1  (pin 6)    →    (pin 9)   +3V3           |
+ * |    GND        (pin 5)    →    (pin 7)   GND            |
+ * +--------------------------------------------------------+
+ *
+ * RZ SMARC BREAKOUT board (CN1)  →  P3T1085UK-ARD (J13)
+ * +--------------------------------------------------------+
+ * |    GND      (pin 2)    →    (pin 4)   GND              |
+ * |    I3C_SCL  (pin 3)    →    (pin 1)   SCL_I3C          |
+ * |    I3C_SDA  (pin 4)    →    (pin 2)   SDA_I3C          |
+ * +--------------------------------------------------------+
+ *
+ * The following jumpers setup is required on the P3T1085UK-ARD board:
+ * - JP1: 1-2
+ * - JP2: 1-2
+ * - JP3: 1-2
+ *
+ * The following SW1(1,2) switch setup is required on the RZ SMARC BREAKOUT
+ * board:
+ * - SW1(1): 1
+ * - SW1(2): 1
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/i3c/i3c.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
+
+/*
+ * #define I3C_BUS_MODE_PURE 1 (for I3C bus mode pure - default)
+ * #define I3C_BUS_MODE_PURE 0 (for I3C bus mode mixed-fast)
+ */
+#define I3C_BUS_MODE_PURE	1
+
+#if I3C_BUS_MODE_PURE
+&i3c {
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+#else /* I3C_BUS_MODE_MIXED_FAST */
+&i3c {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+
+	eeprom@1a {
+		compatible = "atmel,24c02";
+		reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
+	};
+
+	/* U2 */
+	temperature-sensor@48 {
+		compatible = "nxp,p3t1085";
+		reg = <0x48 0 (I2C_FM | I2C_FILTER)>;
+	};
+
+	/* U1 NOT MOUNTED as default */
+	temp-sense@4c {
+		status = "disabled";
+		compatible = "national,lm75";
+		reg = <0x4c 0 (I2C_FM | I2C_FILTER)>;
+	};
+};
+#endif
-- 
2.43.0

Hi Tommaso,

> +/*
> + * #define I3C_BUS_MODE_PURE 1 (for I3C bus mode pure - default)
> + * #define I3C_BUS_MODE_PURE 0 (for I3C bus mode mixed-fast)
> + */
> +#define I3C_BUS_MODE_PURE	1

Sorry, but I really think this is configuration and not hardware
description. The board has only I3C capable devices, so unless you
connect more devices externally, you can always use pure-i3c-mode.
Enforcing mixed-mode is only for debugging.

> +
> +#if I3C_BUS_MODE_PURE
> +&i3c {
> +	i2c-scl-hz = <400000>;
> +	i3c-scl-hz = <12500000>;
> +	status = "okay";
> +};

So, the above is all that is needed. Which is the basic enablement for
the I3C bus in general. I mean, auto-detecting devices is a key feature
of I3C :) Which basically means IMHO that this overlay is superfluous.


> +#else /* I3C_BUS_MODE_MIXED_FAST */
> +&i3c {
> +	status = "okay";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	i2c-scl-hz = <400000>;
> +	i3c-scl-hz = <12500000>;

Despite this else block being debug only...

> +
> +	eeprom@1a {
> +		compatible = "atmel,24c02";
> +		reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
> +	};

... there is no device listening to 0x1a on this board? What do you see
there? Did I forget something?

> +
> +	/* U2 */
> +	temperature-sensor@48 {
> +		compatible = "nxp,p3t1085";
> +		reg = <0x48 0 (I2C_FM | I2C_FILTER)>;
> +	};
> +
> +	/* U1 NOT MOUNTED as default */
> +	temp-sense@4c {
> +		status = "disabled";
> +		compatible = "national,lm75";

Yes, mounting U1 is a hack I introduced. The compatible should be
"nxp,p3t1755" BTW. But as said, the whole MIXED_MODE block is not
hardware description, I'd say.

Happy hacking,

   Wolfram

Hi Wolfram,
Thank you for your review!

On Tue, Nov 18, 2025 at 05:43:44PM +0100, Wolfram Sang wrote:
> Hi Tommaso,
> 
> > +/*
> > + * #define I3C_BUS_MODE_PURE 1 (for I3C bus mode pure - default)
> > + * #define I3C_BUS_MODE_PURE 0 (for I3C bus mode mixed-fast)
> > + */
> > +#define I3C_BUS_MODE_PURE	1
> 
> Sorry, but I really think this is configuration and not hardware
> description. The board has only I3C capable devices, so unless you
> connect more devices externally, you can always use pure-i3c-mode.
> Enforcing mixed-mode is only for debugging.
> 
> > +
> > +#if I3C_BUS_MODE_PURE
> > +&i3c {
> > +	i2c-scl-hz = <400000>;
> > +	i3c-scl-hz = <12500000>;
> > +	status = "okay";
> > +};
> 
> So, the above is all that is needed. Which is the basic enablement for
> the I3C bus in general. I mean, auto-detecting devices is a key feature
> of I3C :) Which basically means IMHO that this overlay is superfluous.
> 
> 
> > +#else /* I3C_BUS_MODE_MIXED_FAST */
> > +&i3c {
> > +	status = "okay";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +
> > +	i2c-scl-hz = <400000>;
> > +	i3c-scl-hz = <12500000>;
> 
> Despite this else block being debug only...
> 
> > +
> > +	eeprom@1a {
> > +		compatible = "atmel,24c02";
> > +		reg = <0x1a 0 (I2C_FM | I2C_FILTER)>;
> > +	};
> 
> ... there is no device listening to 0x1a on this board? What do you see
> there? Did I forget something?

Ouch :'(
Sorry, my bad I forgot to remove this 0x1a (audio codec)
device from the bring-up/testing session.

> 
> > +
> > +	/* U2 */
> > +	temperature-sensor@48 {
> > +		compatible = "nxp,p3t1085";
> > +		reg = <0x48 0 (I2C_FM | I2C_FILTER)>;
> > +	};
> > +
> > +	/* U1 NOT MOUNTED as default */
> > +	temp-sense@4c {
> > +		status = "disabled";
> > +		compatible = "national,lm75";
> 
> Yes, mounting U1 is a hack I introduced. The compatible should be
> "nxp,p3t1755" BTW. But as said, the whole MIXED_MODE block is not
> hardware description, I'd say.

Ack, thanks.

Please correct me if I'm wrong.
Your suggestion is to keep only Patch 1/2 dropping alias line right?
Thanks in advance.

> 
> Happy hacking,
> 
>    Wolfram
> 

Kind Regards,
Tommaso

> Your suggestion is to keep only Patch 1/2 dropping alias line right?

Yes.

We could think about enabling I3C unconditionally by adding this to
rzg3e-smarc-som.dtsi:

+       i2c-scl-hz = <400000>;
+       i3c-scl-hz = <12500000>;
+       status = "okay";

So, I3C will just work when you connect devices to it. The I3C frequency
might be depending a bit on the I3C target board and how it is wired.
Maybe use 10Mhz as a safe value and add a comment?

Hi Wolfram,
Thanks for your review!

On Wed, Nov 19, 2025 at 07:12:56AM +0100, Wolfram Sang wrote:
> 
> > Your suggestion is to keep only Patch 1/2 dropping alias line right?
> 
> Yes.
> 
> We could think about enabling I3C unconditionally by adding this to
> rzg3e-smarc-som.dtsi:

Fine to me. Thank you.

> 
> +       i2c-scl-hz = <400000>;
> +       i3c-scl-hz = <12500000>;
> +       status = "okay";
> 
> So, I3C will just work when you connect devices to it. The I3C frequency
> might be depending a bit on the I3C target board and how it is wired.
> Maybe use 10Mhz as a safe value and add a comment?
> 

Since our current testing setup works fine with 12.5 MHz, I would go with that.
If another target board is used, it can override this value in its board overlay.

I will send v2 addressing your comments.

Kind Regards,
Tommaso