The Intel Agilex 5 SoC contains a programmable FPGA region that requires
proper device tree description to enable FPGA manager support in the Linux
kernel.
The fpga-region node is introduced to support FPGA partial reconfiguration
through the FPGA Manager framework. This node defines a region in the
device tree that can be dynamically programmed at runtime.
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v4:
- No changes.
- Validated with CHECK_DTBS=y as standalone and with
intel,stratix10-soc-fpga-mgr.yaml
Changes in v3:
- tested with intel,stratix10-soc-fpga-mgr.yaml
- Rephrase commit message to make it more concise.
Changes in v2:
- All fallback compatible string to ensure driver is still able to
initialize without new compatible string added in the driver.
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a5c2025a616e..1f5d560f97b2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -85,9 +85,21 @@ svc {
method = "smc";
memory-region = <&service_reserved>;
iommus = <&smmu 10>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,agilex5-soc-fpga-mgr",
+ "intel,agilex-soc-fpga-mgr";
+ };
};
};
+ fpga-region {
+ compatible = "fpga-region";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ fpga-mgr = <&fpga_mgr>;
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
--
2.43.7