Shawn Lin from Rockchip has reiterated that there may be danger in using
their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
from the default and drive at 2.5 GT/s only, even if the DT
max-link-speed property is invalid or inexistent.

This change is corroborated by RK3399 official datasheet [1], which
says maximum link speed for this platform is 2.5 GT/s.

[1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf

Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
Cc: stable@vger.kernel.org
Reported-by: Dragan Simic <dsimic@manjaro.org>
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
---
 drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 0f88da378805..992ccf4b139e 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 	}
 
 	rockchip->link_gen = of_pci_get_max_link_speed(node);
-	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
-		rockchip->link_gen = 2;
+	if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
+		rockchip->link_gen = 1;
+		dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
+	}
+	else if (rockchip->link_gen == 2) {
+		rockchip->link_gen = 1;
+		dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
+	}
 
 	for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++)
 		rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];
-- 
2.49.0

Hi Geraldo,

On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
<geraldogabriel@gmail.com> wrote:
>
> Shawn Lin from Rockchip has reiterated that there may be danger in using
> their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> from the default and drive at 2.5 GT/s only, even if the DT
> max-link-speed property is invalid or inexistent.
>
> This change is corroborated by RK3399 official datasheet [1], which
> says maximum link speed for this platform is 2.5 GT/s.
>
> [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
>
To accurately determine the operating speed, we can leverage the
PCIE_CLIENT_BASIC_STATUS0/1 fields.
This provides a dynamic mechanism to resolve the issue.

[1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595

Thanks
-Anand

> Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
> Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
> Cc: stable@vger.kernel.org
> Reported-by: Dragan Simic <dsimic@manjaro.org>
> Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> ---
>  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index 0f88da378805..992ccf4b139e 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>         }
>
>         rockchip->link_gen = of_pci_get_max_link_speed(node);
> -       if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> -               rockchip->link_gen = 2;
> +       if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
> +               rockchip->link_gen = 1;
> +               dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
> +       }
> +       else if (rockchip->link_gen == 2) {
> +               rockchip->link_gen = 1;
> +               dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
> +       }
>
>         for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++)
>                 rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];
> --
> 2.49.0
>
>

On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Geraldo,
>
> On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> <geraldogabriel@gmail.com> wrote:
> >
> > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > from the default and drive at 2.5 GT/s only, even if the DT
> > max-link-speed property is invalid or inexistent.
> >
> > This change is corroborated by RK3399 official datasheet [1], which
> > says maximum link speed for this platform is 2.5 GT/s.
> >
> > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> >
> To accurately determine the operating speed, we can leverage the
> PCIE_CLIENT_BASIC_STATUS0/1 fields.
> This provides a dynamic mechanism to resolve the issue.
>
> [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
>
> Thanks
> -Anand

Hi Anand,

not to put you down but I think your approach adds unnecessary complexity.

All I care really is that the Kernel Project isn't blamed in the
future if someone happens to lose their data.

Thanks,
Geraldo Nascimento

Hi Geraldo,

On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
<geraldogabriel@gmail.com> wrote:
>
> On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
> >
> > Hi Geraldo,
> >
> > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > <geraldogabriel@gmail.com> wrote:
> > >
> > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > from the default and drive at 2.5 GT/s only, even if the DT
> > > max-link-speed property is invalid or inexistent.
> > >
> > > This change is corroborated by RK3399 official datasheet [1], which
> > > says maximum link speed for this platform is 2.5 GT/s.
> > >
> > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > >
> > To accurately determine the operating speed, we can leverage the
> > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > This provides a dynamic mechanism to resolve the issue.
> >
> > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> >
> > Thanks
> > -Anand
>
> Hi Anand,
>
> not to put you down but I think your approach adds unnecessary complexity.
>
> All I care really is that the Kernel Project isn't blamed in the
> future if someone happens to lose their data.
>
Allow the hardware to negotiate the link speed based on the available
number of lanes.
I don’t anticipate any data loss, since PCIe will automatically
configure the device speed
with link training..

> Thanks,
> Geraldo Nascimento

Thanks
-Anand

Hello Anand,

On Wednesday, December 24, 2025 09:04 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
> <geraldogabriel@gmail.com> wrote:
> > On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
> > > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > > <geraldogabriel@gmail.com> wrote:
> > > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > > from the default and drive at 2.5 GT/s only, even if the DT
> > > > max-link-speed property is invalid or inexistent.
> > > >
> > > > This change is corroborated by RK3399 official datasheet [1], which
> > > > says maximum link speed for this platform is 2.5 GT/s.
> > > >
> > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > > >
> > > To accurately determine the operating speed, we can leverage the
> > > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > > This provides a dynamic mechanism to resolve the issue.
> > >
> > > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> >
> > not to put you down but I think your approach adds unnecessary complexity.
> >
> > All I care really is that the Kernel Project isn't blamed in the
> > future if someone happens to lose their data.
> >
> Allow the hardware to negotiate the link speed based on the
> available number of lanes.
> I don’t anticipate any data loss, since PCIe will automatically
> configure the device speed with link training..

Please, note that this isn't about performing auto negotiation
and following its results, but about "artificially" limiting the
PCIe link speed to 2.5 GT/s on RK3399, because it's well known
by Rockchip that 5 GT/s on RK3399's PCIe interface may cause
issues and data corruption in certain corner cases.

Hi Dragan,

On Wed, 24 Dec 2025 at 18:25, Dragan Simic <dsimic@manjaro.org> wrote:
>
> Hello Anand,
>
> On Wednesday, December 24, 2025 09:04 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> > On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
> > <geraldogabriel@gmail.com> wrote:
> > > On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
> > > > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > > > <geraldogabriel@gmail.com> wrote:
> > > > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > > > from the default and drive at 2.5 GT/s only, even if the DT
> > > > > max-link-speed property is invalid or inexistent.
> > > > >
> > > > > This change is corroborated by RK3399 official datasheet [1], which
> > > > > says maximum link speed for this platform is 2.5 GT/s.
> > > > >
> > > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > > > >
> > > > To accurately determine the operating speed, we can leverage the
> > > > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > > > This provides a dynamic mechanism to resolve the issue.
> > > >
> > > > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> > >
> > > not to put you down but I think your approach adds unnecessary complexity.
> > >
> > > All I care really is that the Kernel Project isn't blamed in the
> > > future if someone happens to lose their data.
> > >
> > Allow the hardware to negotiate the link speed based on the
> > available number of lanes.
> > I don’t anticipate any data loss, since PCIe will automatically
> > configure the device speed with link training..
>
> Please, note that this isn't about performing auto negotiation
> and following its results, but about "artificially" limiting the
> PCIe link speed to 2.5 GT/s on RK3399, because it's well known
> by Rockchip that 5 GT/s on RK3399's PCIe interface may cause
> issues and data corruption in certain corner cases.
>
It’s possible the link speed wasn’t properly tuned. On my older
development board,
which supports this configuration, I haven’t observed any data loss.

sudo lspci -vvv | grep Speed
                LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit
Latency L1 <8us
                LnkSta: Speed 5GT/s, Width x1
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1,
Exit Latency L0s unlimited, L1 <2us
                LnkSta: Speed 5GT/s, Width x1
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

Thanks
-Anand

On Wednesday, December 24, 2025 17:11 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> On Wed, 24 Dec 2025 at 18:25, Dragan Simic <dsimic@manjaro.org> wrote:
> > On Wednesday, December 24, 2025 09:04 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> > > On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
> > > <geraldogabriel@gmail.com> wrote:
> > > > On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
> > > > > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > > > > <geraldogabriel@gmail.com> wrote:
> > > > > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > > > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > > > > from the default and drive at 2.5 GT/s only, even if the DT
> > > > > > max-link-speed property is invalid or inexistent.
> > > > > >
> > > > > > This change is corroborated by RK3399 official datasheet [1], which
> > > > > > says maximum link speed for this platform is 2.5 GT/s.
> > > > > >
> > > > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > > > > >
> > > > > To accurately determine the operating speed, we can leverage the
> > > > > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > > > > This provides a dynamic mechanism to resolve the issue.
> > > > >
> > > > > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> > > >
> > > > not to put you down but I think your approach adds unnecessary complexity.
> > > >
> > > > All I care really is that the Kernel Project isn't blamed in the
> > > > future if someone happens to lose their data.
> > > >
> > > Allow the hardware to negotiate the link speed based on the
> > > available number of lanes.
> > > I don’t anticipate any data loss, since PCIe will automatically
> > > configure the device speed with link training..
> >
> > Please, note that this isn't about performing auto negotiation
> > and following its results, but about "artificially" limiting the
> > PCIe link speed to 2.5 GT/s on RK3399, because it's well known
> > by Rockchip that 5 GT/s on RK3399's PCIe interface may cause
> > issues and data corruption in certain corner cases.
> >
> It’s possible the link speed wasn’t properly tuned. On my older
> development board,
> which supports this configuration, I haven’t observed any data loss.
> 
> sudo lspci -vvv | grep Speed
>                 LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit
> Latency L1 <8us
>                 LnkSta: Speed 5GT/s, Width x1
>                 LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
>                 LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1,
> Exit Latency L0s unlimited, L1 <2us
>                 LnkSta: Speed 5GT/s, Width x1
>                 LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

Let me clarify, please...  This limitation to 2.5 GT/s came straight from
Rockchip a few years ago, described back then as an undisclosed errata.
Recently, we got some more details from Rockchip that confirmed 5 GT/s
as having issues in certain corner cases that cannot be validated by
performing some field tests or by observing the PCIe behavior under load.
Those corner cases with 5 GT/s, as described by Rockchip, are quite hard
to reach, but the possibility is still real.

To sum it up, yes, multiple people have reported 5 GT/s as "working for me"
on their RK3399-based boards and devices, but that unfortunately means
nothing in this case, due to the specific nature of the underlying issue.

On Wed, Dec 24, 2025 at 1:52 PM Dragan Simic <dsimic@manjaro.org> wrote:
>
> On Wednesday, December 24, 2025 17:11 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> > On Wed, 24 Dec 2025 at 18:25, Dragan Simic <dsimic@manjaro.org> wrote:
> > > On Wednesday, December 24, 2025 09:04 CET, Anand Moon <linux.amoon@gmail.com> wrote:
> > > > On Wed, 24 Dec 2025 at 11:08, Geraldo Nascimento
> > > > <geraldogabriel@gmail.com> wrote:
> > > > > On Wed, Dec 24, 2025 at 2:18 AM Anand Moon <linux.amoon@gmail.com> wrote:
> > > > > > On Tue, 18 Nov 2025 at 03:17, Geraldo Nascimento
> > > > > > <geraldogabriel@gmail.com> wrote:
> > > > > > > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > > > > > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > > > > > > from the default and drive at 2.5 GT/s only, even if the DT
> > > > > > > max-link-speed property is invalid or inexistent.
> > > > > > >
> > > > > > > This change is corroborated by RK3399 official datasheet [1], which
> > > > > > > says maximum link speed for this platform is 2.5 GT/s.
> > > > > > >
> > > > > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > > > > > >
> > > > > > To accurately determine the operating speed, we can leverage the
> > > > > > PCIE_CLIENT_BASIC_STATUS0/1 fields.
> > > > > > This provides a dynamic mechanism to resolve the issue.
> > > > > >
> > > > > > [1] https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-rockchip-ep.c#L533-L595
> > > > >
> > > > > not to put you down but I think your approach adds unnecessary complexity.
> > > > >
> > > > > All I care really is that the Kernel Project isn't blamed in the
> > > > > future if someone happens to lose their data.
> > > > >
> > > > Allow the hardware to negotiate the link speed based on the
> > > > available number of lanes.
> > > > I don’t anticipate any data loss, since PCIe will automatically
> > > > configure the device speed with link training..
> > >
> > > Please, note that this isn't about performing auto negotiation
> > > and following its results, but about "artificially" limiting the
> > > PCIe link speed to 2.5 GT/s on RK3399, because it's well known
> > > by Rockchip that 5 GT/s on RK3399's PCIe interface may cause
> > > issues and data corruption in certain corner cases.
> > >
> > It’s possible the link speed wasn’t properly tuned. On my older
> > development board,
> > which supports this configuration, I haven’t observed any data loss.
> >
> > sudo lspci -vvv | grep Speed
> >                 LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit
> > Latency L1 <8us
> >                 LnkSta: Speed 5GT/s, Width x1
> >                 LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
> >                 LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1,
> > Exit Latency L0s unlimited, L1 <2us
> >                 LnkSta: Speed 5GT/s, Width x1
> >                 LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
>
> Let me clarify, please...  This limitation to 2.5 GT/s came straight from
> Rockchip a few years ago, described back then as an undisclosed errata.
> Recently, we got some more details from Rockchip that confirmed 5 GT/s
> as having issues in certain corner cases that cannot be validated by
> performing some field tests or by observing the PCIe behavior under load.
> Those corner cases with 5 GT/s, as described by Rockchip, are quite hard
> to reach, but the possibility is still real.
>
> To sum it up, yes, multiple people have reported 5 GT/s as "working for me"
> on their RK3399-based boards and devices, but that unfortunately means
> nothing in this case, due to the specific nature of the underlying issue.
>

Not only that but the bandwidth actually earned is very small due to the
inherent limited interrupt processing capability of a single core, meaning
the 5 GT/s bandwidth / transfer speed is never fully utilized.

It's better than to force a slightly lower actual transfer speed than to risk
the liability of someone losing their data, period.

Regards,
Geraldo Nascimento

On Mon, Nov 17, 2025 at 06:47:05PM -0300, Geraldo Nascimento wrote:
> Shawn Lin from Rockchip has reiterated that there may be danger in using
> their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> from the default and drive at 2.5 GT/s only, even if the DT
> max-link-speed property is invalid or inexistent.
> 
> This change is corroborated by RK3399 official datasheet [1], which
> says maximum link speed for this platform is 2.5 GT/s.
> 
> [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> 
> Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
> Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
> Cc: stable@vger.kernel.org
> Reported-by: Dragan Simic <dsimic@manjaro.org>
> Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> ---
>  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index 0f88da378805..992ccf4b139e 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>  	}
>  
>  	rockchip->link_gen = of_pci_get_max_link_speed(node);
> -	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> -		rockchip->link_gen = 2;
> +	if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
> +		rockchip->link_gen = 1;
> +		dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
> +	}
> +	else if (rockchip->link_gen == 2) {
> +		rockchip->link_gen = 1;
> +		dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");

What does 'danger' really mean here? Link instability or something else?

Error messages should be precise and not fearmongering.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Heello Manivannan and Geraldo,

On Thursday, December 18, 2025 09:05 CET, Manivannan Sadhasivam <mani@kernel.org> wrote:
> On Mon, Nov 17, 2025 at 06:47:05PM -0300, Geraldo Nascimento wrote:
> > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > from the default and drive at 2.5 GT/s only, even if the DT
> > max-link-speed property is invalid or inexistent.
> > 
> > This change is corroborated by RK3399 official datasheet [1], which
> > says maximum link speed for this platform is 2.5 GT/s.
> > 
> > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > 
> > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
> > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
> > Cc: stable@vger.kernel.org
> > Reported-by: Dragan Simic <dsimic@manjaro.org>
> > Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
> > Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> > ---
> >  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > index 0f88da378805..992ccf4b139e 100644
> > --- a/drivers/pci/controller/pcie-rockchip.c
> > +++ b/drivers/pci/controller/pcie-rockchip.c
> > @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> >  	}
> >  
> >  	rockchip->link_gen = of_pci_get_max_link_speed(node);
> > -	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> > -		rockchip->link_gen = 2;
> > +	if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
> > +		rockchip->link_gen = 1;
> > +		dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
> > +	}
> > +	else if (rockchip->link_gen == 2) {
> > +		rockchip->link_gen = 1;
> > +		dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
> 
> What does 'danger' really mean here? Link instability or something else?
> Error messages should be precise and not fearmongering.

I agree that the original wording is a bit suboptimal, and I'd suggest
to Geraldo that the produced warning message is changed to

  "5.0 GT/s may cause data corruption, limited to to 2.5 GT/s\n"

or something similar, to better reflect the actual underlying issue.

On Thu Dec 18, 2025 at 10:47 AM CET, Dragan Simic wrote:
> Heello Manivannan and Geraldo,
>
> On Thursday, December 18, 2025 09:05 CET, Manivannan Sadhasivam <mani@kernel.org> wrote:
>> On Mon, Nov 17, 2025 at 06:47:05PM -0300, Geraldo Nascimento wrote:
>> > Shawn Lin from Rockchip has reiterated that there may be danger in using
>> > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
>> > from the default and drive at 2.5 GT/s only, even if the DT
>> > max-link-speed property is invalid or inexistent.
>> > 
>> > This change is corroborated by RK3399 official datasheet [1], which
>> > says maximum link speed for this platform is 2.5 GT/s.
>> > 
>> > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
>> > 
>> > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
>> > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
>> > Cc: stable@vger.kernel.org
>> > Reported-by: Dragan Simic <dsimic@manjaro.org>
>> > Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
>> > Reviewed-by: Dragan Simic <dsimic@manjaro.org>
>> > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
>> > ---
>> >  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
>> >  1 file changed, 8 insertions(+), 2 deletions(-)
>> > 
>> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
>> > index 0f88da378805..992ccf4b139e 100644
>> > --- a/drivers/pci/controller/pcie-rockchip.c
>> > +++ b/drivers/pci/controller/pcie-rockchip.c
>> > @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>> >  	}
>> >  
>> >  	rockchip->link_gen = of_pci_get_max_link_speed(node);
>> > -	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
>> > -		rockchip->link_gen = 2;
>> > +	if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
>> > +		rockchip->link_gen = 1;
>> > +		dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
>> > +	}
>> > +	else if (rockchip->link_gen == 2) {
>> > +		rockchip->link_gen = 1;
>> > +		dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
>> 
>> What does 'danger' really mean here? Link instability or something else?
>> Error messages should be precise and not fearmongering.
>
> I agree that the original wording is a bit suboptimal, and I'd suggest
> to Geraldo that the produced warning message is changed to
>
>   "5.0 GT/s may cause data corruption, limited to to 2.5 GT/s\n"
>
> or something similar, to better reflect the actual underlying issue.

s/limited to to/therefore limit speed to/ ?

Cheers,
  Diederik

Hello Diederik,

On Thursday, December 18, 2025 11:01 CET, "Diederik de Haas" <diederik@cknow-tech.com> wrote:
> On Thu Dec 18, 2025 at 10:47 AM CET, Dragan Simic wrote:
> > On Thursday, December 18, 2025 09:05 CET, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >> On Mon, Nov 17, 2025 at 06:47:05PM -0300, Geraldo Nascimento wrote:
> >> > Shawn Lin from Rockchip has reiterated that there may be danger in using
> >> > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> >> > from the default and drive at 2.5 GT/s only, even if the DT
> >> > max-link-speed property is invalid or inexistent.
> >> > 
> >> > This change is corroborated by RK3399 official datasheet [1], which
> >> > says maximum link speed for this platform is 2.5 GT/s.
> >> > 
> >> > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> >> > 
> >> > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
> >> > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
> >> > Cc: stable@vger.kernel.org
> >> > Reported-by: Dragan Simic <dsimic@manjaro.org>
> >> > Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
> >> > Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> >> > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> >> > ---
> >> >  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
> >> >  1 file changed, 8 insertions(+), 2 deletions(-)
> >> > 
> >> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> >> > index 0f88da378805..992ccf4b139e 100644
> >> > --- a/drivers/pci/controller/pcie-rockchip.c
> >> > +++ b/drivers/pci/controller/pcie-rockchip.c
> >> > @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> >> >  	}
> >> >  
> >> >  	rockchip->link_gen = of_pci_get_max_link_speed(node);
> >> > -	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> >> > -		rockchip->link_gen = 2;
> >> > +	if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
> >> > +		rockchip->link_gen = 1;
> >> > +		dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
> >> > +	}
> >> > +	else if (rockchip->link_gen == 2) {
> >> > +		rockchip->link_gen = 1;
> >> > +		dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
> >> 
> >> What does 'danger' really mean here? Link instability or something else?
> >> Error messages should be precise and not fearmongering.
> >
> > I agree that the original wording is a bit suboptimal, and I'd suggest
> > to Geraldo that the produced warning message is changed to
> >
> >   "5.0 GT/s may cause data corruption, limited to to 2.5 GT/s\n"
> >
> > or something similar, to better reflect the actual underlying issue.
> 
> s/limited to to/therefore limit speed to/ ?

That would work well in a book or an article, while slightly terse
wording is usually preferred in the messages produced by the kernel,
or in log messages in general.  Such an approach compacts as much
information as possible in as few words as possible, while still
remaining (mostly) grammatically correct.

Hello Mani, Dragan, Diederik, and all,

I'm currently facing banking issues in Brazil which means I'm
refraining from fetching my email through POP3 with mutt to do proper
kernel development.
I usually fetch my mail through POP3 and have the server delete it, to
save space on my free tier.
But I found out I have a 20-year old bank account open that I had
forgot about, and with this bureaucracy hell I can't have the server
delete the messages for now.
I'll send v3 with more proper and illustrative wording once I get this done.

Thanks,
Geraldo Nascimento

On Thu, Dec 18, 2025 at 7:13 AM Dragan Simic <dsimic@manjaro.org> wrote:
>
> Hello Diederik,
>
> On Thursday, December 18, 2025 11:01 CET, "Diederik de Haas" <diederik@cknow-tech.com> wrote:
> > On Thu Dec 18, 2025 at 10:47 AM CET, Dragan Simic wrote:
> > > On Thursday, December 18, 2025 09:05 CET, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >> On Mon, Nov 17, 2025 at 06:47:05PM -0300, Geraldo Nascimento wrote:
> > >> > Shawn Lin from Rockchip has reiterated that there may be danger in using
> > >> > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change
> > >> > from the default and drive at 2.5 GT/s only, even if the DT
> > >> > max-link-speed property is invalid or inexistent.
> > >> >
> > >> > This change is corroborated by RK3399 official datasheet [1], which
> > >> > says maximum link speed for this platform is 2.5 GT/s.
> > >> >
> > >> > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
> > >> >
> > >> > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver")
> > >> > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/
> > >> > Cc: stable@vger.kernel.org
> > >> > Reported-by: Dragan Simic <dsimic@manjaro.org>
> > >> > Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
> > >> > Reviewed-by: Dragan Simic <dsimic@manjaro.org>
> > >> > Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> > >> > ---
> > >> >  drivers/pci/controller/pcie-rockchip.c | 10 ++++++++--
> > >> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > >> >
> > >> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > >> > index 0f88da378805..992ccf4b139e 100644
> > >> > --- a/drivers/pci/controller/pcie-rockchip.c
> > >> > +++ b/drivers/pci/controller/pcie-rockchip.c
> > >> > @@ -66,8 +66,14 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> > >> >          }
> > >> >
> > >> >          rockchip->link_gen = of_pci_get_max_link_speed(node);
> > >> > -        if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> > >> > -                rockchip->link_gen = 2;
> > >> > +        if (rockchip->link_gen < 0 || rockchip->link_gen > 2) {
> > >> > +                rockchip->link_gen = 1;
> > >> > +                dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n");
> > >> > +        }
> > >> > +        else if (rockchip->link_gen == 2) {
> > >> > +                rockchip->link_gen = 1;
> > >> > +                dev_warn(dev, "5.0 GT/s is dangerous, set to 2.5 GT/s\n");
> > >>
> > >> What does 'danger' really mean here? Link instability or something else?
> > >> Error messages should be precise and not fearmongering.
> > >
> > > I agree that the original wording is a bit suboptimal, and I'd suggest
> > > to Geraldo that the produced warning message is changed to
> > >
> > >   "5.0 GT/s may cause data corruption, limited to to 2.5 GT/s\n"
> > >
> > > or something similar, to better reflect the actual underlying issue.
> >
> > s/limited to to/therefore limit speed to/ ?
>
> That would work well in a book or an article, while slightly terse
> wording is usually preferred in the messages produced by the kernel,
> or in log messages in general.  Such an approach compacts as much
> information as possible in as few words as possible, while still
> remaining (mostly) grammatically correct.
>