The Agilex 5 SoC FPGA manager introduces updated hardware features and
register maps that require explicit binding support to enable correct
initialization and control through the FPGA manager subsystem.

It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
properly. This changes also keep device tree bindings up to date with
hardware platforms changes.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
	- No changes in this patch
---
 .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
index 6e536d6b28a9..b531522cca07 100644
--- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
+++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
@@ -23,6 +23,7 @@ properties:
     enum:
       - intel,stratix10-soc-fpga-mgr
       - intel,agilex-soc-fpga-mgr
+      - intel,agilex5-soc-fpga-mgr
 
 required:
   - compatible
-- 
2.43.7

On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
> The Agilex 5 SoC FPGA manager introduces updated hardware features and
> register maps that require explicit binding support to enable correct
> initialization and control through the FPGA manager subsystem.
> 
> It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
> properly. This changes also keep device tree bindings up to date with
> hardware platforms changes.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v2:
> 	- No changes in this patch
> ---
>  .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> index 6e536d6b28a9..b531522cca07 100644
> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> @@ -23,6 +23,7 @@ properties:
>      enum:
>        - intel,stratix10-soc-fpga-mgr
>        - intel,agilex-soc-fpga-mgr
> +      - intel,agilex5-soc-fpga-mgr

Reviewed-by: Xu Yilun <yilun.xu@intel.com>

>  
>  required:
>    - compatible
> -- 
> 2.43.7
> 
>

On Thu, Nov 13, 2025 at 01:51:47PM +0800, Xu Yilun wrote:
> On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
> > The Agilex 5 SoC FPGA manager introduces updated hardware features and
> > register maps that require explicit binding support to enable correct
> > initialization and control through the FPGA manager subsystem.
> > 
> > It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
> > properly. This changes also keep device tree bindings up to date with
> > hardware platforms changes.
> > 
> > Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > ---
> > Changes in v2:
> > 	- No changes in this patch

Should have been changed to permit the fallback compatible as discussed.
pw-bot: changes-requested


> > ---
> >  .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > index 6e536d6b28a9..b531522cca07 100644
> > --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > @@ -23,6 +23,7 @@ properties:
> >      enum:
> >        - intel,stratix10-soc-fpga-mgr
> >        - intel,agilex-soc-fpga-mgr
> > +      - intel,agilex5-soc-fpga-mgr
> 
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> 
> >  
> >  required:
> >    - compatible
> > -- 
> > 2.43.7
> > 
> > 

On 13/11/2025 11:18 pm, Conor Dooley wrote:
> On Thu, Nov 13, 2025 at 01:51:47PM +0800, Xu Yilun wrote:
>> On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
>>> The Agilex 5 SoC FPGA manager introduces updated hardware features and
>>> register maps that require explicit binding support to enable correct
>>> initialization and control through the FPGA manager subsystem.
>>>
>>> It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
>>> properly. This changes also keep device tree bindings up to date with
>>> hardware platforms changes.
>>>
>>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>> ---
>>> Changes in v2:
>>> 	- No changes in this patch
> 
> Should have been changed to permit the fallback compatible as discussed.
> pw-bot: changes-requested
> 

Working on it right now. Will include the changes in the next version 
after test is done.

Thanks.

Best Regards,
Khairul
  >
>>> ---
>>>   .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> index 6e536d6b28a9..b531522cca07 100644
>>> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> @@ -23,6 +23,7 @@ properties:
>>>       enum:
>>>         - intel,stratix10-soc-fpga-mgr
>>>         - intel,agilex-soc-fpga-mgr
>>> +      - intel,agilex5-soc-fpga-mgr
>>
>> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
>>
>>>   
>>>   required:
>>>     - compatible
>>> -- 
>>> 2.43.7
>>>
>>>