.../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml | 1 + arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+)
This patch series adds device tree bindings, driver support, and DTS updates to enable FPGA Manager functionality for Intel Agilex5 SoC. These changes are intended to enable FPGA programming and management capabilities on Agilex5-based platforms. --- Notes: Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory region" from https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ This patch series is applied on socfpga maintainer's tree https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 Changes in v2: - Drop "fpga: stratix10-soc: Add support for Agilex5" - Add fallback compatible in DT --- Khairul Anuar Romli (2): dt-bindings: fpga: stratix10: add support for Agilex5 arm64: dts: agilex5: add fpga-region and fpga-mgr nodes .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml | 1 + arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+) -- 2.43.7
On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: > This patch series adds device tree bindings, driver support, and DTS > updates to enable FPGA Manager functionality for Intel Agilex5 SoC. > > These changes are intended to enable FPGA programming and management > capabilities on Agilex5-based platforms. > > --- > Notes: > Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory There is no patch #3 now. Should be Patch #2 ? > region" from > https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ > > This patch series is applied on socfpga maintainer's tree > https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 Given that, @Dinh Nguyen could you take the series if you are good? Thanks, Yilun > > Changes in v2: > - Drop "fpga: stratix10-soc: Add support for Agilex5" > - Add fallback compatible in DT > --- > Khairul Anuar Romli (2): > dt-bindings: fpga: stratix10: add support for Agilex5 > arm64: dts: agilex5: add fpga-region and fpga-mgr nodes > > .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml | 1 + > arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > -- > 2.43.7 > >
On 13/11/2025 07:01, Xu Yilun wrote: > On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: >> This patch series adds device tree bindings, driver support, and DTS >> updates to enable FPGA Manager functionality for Intel Agilex5 SoC. >> >> These changes are intended to enable FPGA programming and management >> capabilities on Agilex5-based platforms. >> >> --- >> Notes: >> Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory > > There is no patch #3 now. Should be Patch #2 ? > >> region" from >> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ >> >> This patch series is applied on socfpga maintainer's tree >> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 > > Given that, @Dinh Nguyen could you take the series if you are good? This was never tested, so series cannot be taken. NAK, Altera should test the code BEFORE sending it to upstream, not after we say it was not tested. Best regards, Krzysztof
On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote: > On 13/11/2025 07:01, Xu Yilun wrote: >> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: >>> This patch series adds device tree bindings, driver support, and DTS >>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC. >>> >>> These changes are intended to enable FPGA programming and management >>> capabilities on Agilex5-based platforms. >>> >>> --- >>> Notes: >>> Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory >> >> There is no patch #3 now. Should be Patch #2 ? >> >>> region" from >>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ >>> >>> This patch series is applied on socfpga maintainer's tree >>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 >> >> Given that, @Dinh Nguyen could you take the series if you are good? > > This was never tested, so series cannot be taken. > > NAK, Altera should test the code BEFORE sending it to upstream, not > after we say it was not tested. > > Best regards, > Krzysztof If you are referring to the code being tested on the Agilex5, it was tested. I even take the measure to add the debug print the in init to see if the fallback is working, which it did. Of course I took clock manager patch from Dinh's clock manager driver for Agilex5 have local defconfig instead of using default defconfig for testing the code. https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/ Are you referring to different kind of test? Thanks. Best Regards, Khairul
On 13/11/2025 10:07, Romli, Khairul Anuar wrote: > On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote: >> On 13/11/2025 07:01, Xu Yilun wrote: >>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: >>>> This patch series adds device tree bindings, driver support, and DTS >>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC. >>>> >>>> These changes are intended to enable FPGA programming and management >>>> capabilities on Agilex5-based platforms. >>>> >>>> --- >>>> Notes: >>>> Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory >>> >>> There is no patch #3 now. Should be Patch #2 ? >>> >>>> region" from >>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ >>>> >>>> This patch series is applied on socfpga maintainer's tree >>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 >>> >>> Given that, @Dinh Nguyen could you take the series if you are good? >> >> This was never tested, so series cannot be taken. >> >> NAK, Altera should test the code BEFORE sending it to upstream, not >> after we say it was not tested. >> >> Best regards, >> Krzysztof > > If you are referring to the code being tested on the Agilex5, it was > tested. I even take the measure to add the debug print the in init to > see if the fallback is working, which it did. > > Of course I took clock manager patch from Dinh's clock manager driver > for Agilex5 have local defconfig instead of using default defconfig for > testing the code. > > https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/ > > Are you referring to different kind of test? Yes, test by tools, because you certainly do not want to engage reviewers if computers do the job fine. see any DT talk (there where like four last years!) or Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ Best regards, Krzysztof
On 13/11/2025 5:10 pm, Krzysztof Kozlowski wrote: > On 13/11/2025 10:07, Romli, Khairul Anuar wrote: >> On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote: >>> On 13/11/2025 07:01, Xu Yilun wrote: >>>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: >>>>> This patch series adds device tree bindings, driver support, and DTS >>>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC. >>>>> >>>>> These changes are intended to enable FPGA programming and management >>>>> capabilities on Agilex5-based platforms. >>>>> >>>>> --- >>>>> Notes: >>>>> Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory >>>> >>>> There is no patch #3 now. Should be Patch #2 ? >>>> >>>>> region" from >>>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ >>>>> >>>>> This patch series is applied on socfpga maintainer's tree >>>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 >>>> >>>> Given that, @Dinh Nguyen could you take the series if you are good? >>> >>> This was never tested, so series cannot be taken. >>> >>> NAK, Altera should test the code BEFORE sending it to upstream, not >>> after we say it was not tested. >>> >>> Best regards, >>> Krzysztof >> >> If you are referring to the code being tested on the Agilex5, it was >> tested. I even take the measure to add the debug print the in init to >> see if the fallback is working, which it did. >> >> Of course I took clock manager patch from Dinh's clock manager driver >> for Agilex5 have local defconfig instead of using default defconfig for >> testing the code. >> >> https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/ >> >> Are you referring to different kind of test? > > Yes, test by tools, because you certainly do not want to engage > reviewers if computers do the job fine. > > see any DT talk (there where like four last years!) or > Documentation/devicetree/bindings/writing-schema.rst or > https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ > > Best regards, > Krzysztof Thanks, I can see the error with make -j48 CHECK_DTBS=y DT_SCHEMA_FILES=intel,stratix10-soc-fpga-mgr.yaml intel/socfpga_agilex5_socdk.dtb; If i revert back without adding "intel,agilex-soc-fpga-mgr"", the tool is able to pass without any issue. But we need the driver entry to make it able to load as it compare the entry from dts and the compatible entry in the driver. Should we add back the entry in the driver like in the v1? Or, shall we defer the driver changes for now? Thanks. Best Regards, Khairul
On 13/11/2025 10:38, Romli, Khairul Anuar wrote: > On 13/11/2025 5:10 pm, Krzysztof Kozlowski wrote: >> On 13/11/2025 10:07, Romli, Khairul Anuar wrote: >>> On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote: >>>> On 13/11/2025 07:01, Xu Yilun wrote: >>>>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote: >>>>>> This patch series adds device tree bindings, driver support, and DTS >>>>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC. >>>>>> >>>>>> These changes are intended to enable FPGA programming and management >>>>>> capabilities on Agilex5-based platforms. >>>>>> >>>>>> --- >>>>>> Notes: >>>>>> Patch #3 depends on "arm64: dts: intel: Add Agilex5 SVC node with memory >>>>> >>>>> There is no patch #3 now. Should be Patch #2 ? >>>>> >>>>>> region" from >>>>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/ >>>>>> >>>>>> This patch series is applied on socfpga maintainer's tree >>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 >>>>> >>>>> Given that, @Dinh Nguyen could you take the series if you are good? >>>> >>>> This was never tested, so series cannot be taken. >>>> >>>> NAK, Altera should test the code BEFORE sending it to upstream, not >>>> after we say it was not tested. >>>> >>>> Best regards, >>>> Krzysztof >>> >>> If you are referring to the code being tested on the Agilex5, it was >>> tested. I even take the measure to add the debug print the in init to >>> see if the fallback is working, which it did. >>> >>> Of course I took clock manager patch from Dinh's clock manager driver >>> for Agilex5 have local defconfig instead of using default defconfig for >>> testing the code. >>> >>> https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/ >>> >>> Are you referring to different kind of test? >> >> Yes, test by tools, because you certainly do not want to engage >> reviewers if computers do the job fine. >> >> see any DT talk (there where like four last years!) or >> Documentation/devicetree/bindings/writing-schema.rst or >> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >> >> Best regards, >> Krzysztof > > Thanks, I can see the error with make -j48 CHECK_DTBS=y > DT_SCHEMA_FILES=intel,stratix10-soc-fpga-mgr.yaml > intel/socfpga_agilex5_socdk.dtb; > > If i revert back without adding "intel,agilex-soc-fpga-mgr"", the tool > is able to pass without any issue. But we need the driver entry to make > it able to load as it compare the entry from dts and the compatible > entry in the driver. > > Should we add back the entry in the driver like in the v1? Or, shall we > defer the driver changes for now? You ask now about basics of DT, so sorry but doing homework is your task. Maybe the beginners DTS talk from this year's OSSEU will be helpful here. Or one of many other resources... Best regards, Krzysztof
© 2016 - 2025 Red Hat, Inc.