From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add support for configuring the DMA addressable bit width in the
Synopsys DesignWare USB3 (DWC3) core driver.

Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
DMA mask (such as the default 64-bit) can lead to address truncation or
translation faults when the SMMU is enabled.

This commit introduces a new field, dma_addressable_bits, in the dwc3
structure to track the platform’s supported DMA width. The default value
is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
value is overridden to 40 bits. This field is then used when setting the
DMA mask to ensure compatibility with the system’s actual address bus
capabilities.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/usb/dwc3/core.c | 9 ++++++++-
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ae140c356295..20e655364135 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 	dwc->xhci_resources[0].flags = res->flags;
 	dwc->xhci_resources[0].name = res->name;
 
+	/* Initialize dma addressable bit to 64 bits as default */
+	dwc->dma_addressable_bits = 64;
+
 	/*
 	 * Request memory region but exclude xHCI regs,
 	 * since it will be requested by the xhci-plat driver.
@@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
 		}
 
+		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))
+			dwc->dma_addressable_bits = 40;
+
 		of_node_put(parent);
 	}
 
@@ -2243,7 +2249,8 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 
 	if (!dwc->sysdev_is_parent &&
 	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
-		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
+		ret = dma_set_mask_and_coherent(dwc->sysdev,
+						DMA_BIT_MASK(dwc->dma_addressable_bits));
 		if (ret)
 			goto err_disable_clks;
 	}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a5fc92c4ffa3..ddc42c88da93 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1180,6 +1180,8 @@ struct dwc3_glue_ops {
  * @wakeup_pending_funcs: Indicates whether any interface has requested for
  *			 function wakeup in bitmap format where bit position
  *			 represents interface_id.
+ * @dma_addressable_bits: set if we need to configure a different
+ *			dma-bit-mask other than 64 bits.
  */
 struct dwc3 {
 	struct work_struct	drd_work;
@@ -1414,6 +1416,7 @@ struct dwc3 {
 	struct dentry		*debug_root;
 	u32			gsbuscfg0_reqinfo;
 	u32			wakeup_pending_funcs;
+	u32			dma_addressable_bits;
 };
 
 #define INCRX_BURST_MODE 0
-- 
2.49.GIT

On Tue, Nov 11, 2025 at 02:18:48PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add support for configuring the DMA addressable bit width in the
> Synopsys DesignWare USB3 (DWC3) core driver.
> 
> Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
> DMA mask (such as the default 64-bit) can lead to address truncation or
> translation faults when the SMMU is enabled.
> 
> This commit introduces a new field, dma_addressable_bits, in the dwc3
> structure to track the platform’s supported DMA width. The default value
> is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
> value is overridden to 40 bits. This field is then used when setting the
> DMA mask to ensure compatibility with the system’s actual address bus
> capabilities.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/usb/dwc3/core.c | 9 ++++++++-
>  drivers/usb/dwc3/core.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ae140c356295..20e655364135 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  	dwc->xhci_resources[0].flags = res->flags;
>  	dwc->xhci_resources[0].name = res->name;
>  
> +	/* Initialize dma addressable bit to 64 bits as default */
> +	dwc->dma_addressable_bits = 64;
> +
>  	/*
>  	 * Request memory region but exclude xHCI regs,
>  	 * since it will be requested by the xhci-plat driver.
> @@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
>  		}
>  
> +		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))

No, this does not scale. Don't sprinkle compatible all over driver code.
You have driver match data for that.

Best regards,
Krzysztof